Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3380003

1

T1

116

T3

187

T6

56717

full_word

2152524

1

T1

13

T3

19

T5

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5532227	1			T1	129		T3	206		T5	2
auto[TlIntgErrCmd]	107	1			T54	9		T55	3		T56	5
auto[TlIntgErrData]	103	1			T54	6		T55	6		T56	9
auto[TlIntgErrBoth]	90	1			T54	5		T55	1		T56	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

878816

1

T1

129

T3

206

T5

2

auto[1]

4653711

1

T6

78787

T14

616208

T15

253551

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	369592	1			T1	116		T3	187		T6	5787
auto[TlIntgErrNone]	partial	auto[1]	3010145	1			T6	50930		T14	396856		T15	165588
auto[TlIntgErrNone]	full_word	auto[0]	509107	1			T1	13		T3	19		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	1643383	1			T6	27857		T14	219352		T15	87963
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T54	3		T56	2		T120	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T54	5		T55	2		T56	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T54	1		T121	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T55	1		T129	3		T131	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T54	3		T55	3		T56	4
auto[TlIntgErrData]	partial	auto[1]	54	1			T54	3		T55	3		T56	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T125	1		T129	1		T131	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T120	1		T121	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T56	2		T120	2		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T54	5		T56	4		T120	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T122	1		T128	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T55	1		T124	1		T125	1