Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.43	96.97	93.01	97.88	100.00	98.69	98.03

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.15	91.60	84.78	99.07		95.29	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	438	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
208	1	1
254	1	1
309	1	1
410	8	8
411	8	8
413	8	8
414	8	8
416	8	8
417	8	8
421	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
434	1	1
438	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       254
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T12
1	1	Covered	T1,T3,T5

 LINE       414
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       421
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
1	0	Not Covered

 LINE       423
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T5,T7,T8

 LINE       434
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T30
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T30

 LINE       438
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T7,T12
0	1	0	Covered	T5,T7,T8
1	0	0	Covered	T27,T28,T29

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
rom_tl_o.a_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T6,T14,T15	Yes	T6,T14,T15	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,*T5	Yes	T1,T3,T5	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T6,*T14,*T15	Yes	T6,T14,T15	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_error	Yes	Yes	T6,T14,T15	Yes	T6,T14,T15	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T3,T5,T6	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T3,*T5,*T6	Yes	T3,T5,T6	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T3,T5,T6	OUTPUT
keymgr_data_o.valid	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T3,T5,T6	Yes	T1,T3,T5	OUTPUT
kmac_data_i.error	No	Yes	T8,T22,T23	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T3,T5,T6	Yes	T5,T6,T7	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T5,T6,T7	Yes	T3,T5,T6	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	208	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	208	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	201368213	201197261	0	0
BusRomIndicesMatch_A	201356000	201190900	0	0
FpvSecCmFifoRptrCheck_A	201368213	0	0	0
FpvSecCmFifoWptrCheck_A	201368213	0	0	0
FpvSecCmRegWeOnehotCheck_A	201368213	70	0	0
KeymgrDataODataKnown_A	201368213	68516255	0	0
KeymgrDataODataKnown_AKnownEnable	201368213	201197261	0	0
KeymgrDataOValidKnown_A	201368213	201197261	0	0
KeymgrValidChk_A	201368213	0	0	320
KmacDataODataKnown_A	201368213	132562086	0	0
KmacDataODataKnown_AKnownEnable	201368213	201197261	0	0
KmacDataOValidKnown_A	201368213	201197261	0	0
PwrmgrDataChk_A	201368213	0	0	320
PwrmgrDataOKnown_A	201368213	201197261	0	0
RegsTlOAReadyKnown_A	201368213	201197261	0	0
RegsTlODDataKnown_A	201368213	8066302	0	0
RegsTlODDataKnown_AKnownEnable	201368213	201197261	0	0
RegsTlODValidKnown_A	201368213	201197261	0	0
RomTlOAReadyKnown_A	201368213	201197261	0	0
RomTlODDataKnown_A	201368213	7866209	0	0
RomTlODDataKnown_AKnownEnable	201368213	201197261	0	0
RomTlODValidKnown_A	201368213	201197261	0	0
StabilityChkKmac_A	201368213	132559715	0	0
StabilityChkkeymgr_A	201368213	68515089	0	0
TlAccessChk_A	201368213	132681006	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	201368213	70	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	201368213	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	201368213	447	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	201368213	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201356000	201190900	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441516	440238	0	0
T6	150544	150532	0	0
T7	178029	177801	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	70	0	0
T16	16700	0	0	0
T27	83371	20	0	0
T28	0	10	0	0
T29	0	10	0	0
T31	0	20	0	0
T32	0	10	0	0
T33	161398	0	0	0
T34	109053	0	0	0
T35	369567	0	0	0
T36	246730	0	0	0
T37	88196	0	0	0
T38	114004	0	0	0
T39	8560	0	0	0
T40	417191	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	68516255	0	0
T1	196275	868	0	0
T2	81766	64	0	0
T3	537933	6189	0	0
T4	175524	139	0	0
T5	441618	8514	0	0
T6	150544	133330	0	0
T7	178037	10427	0	0
T8	366908	289	0	0
T9	279982	1197	0	0
T10	84044	1682	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	0	0	320

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	132562086	0	0
T1	196275	195238	0	0
T2	81766	81596	0	0
T3	537933	531127	0	0
T4	175524	175247	0	0
T5	441618	430512	0	0
T6	150544	171713	0	0
T7	178037	176606	0	0
T8	366908	366217	0	0
T9	279982	278565	0	0
T10	84044	82004	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	0	0	320

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	8066302	0	0
T2	81766	8	0	0
T3	537933	278	0	0
T4	175524	33	0	0
T5	441618	15	0	0
T6	150544	364090	0	0
T7	178037	26	0	0
T8	366908	1	0	0
T9	279982	32	0	0
T10	84044	32	0	0
T11	836516	299	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	7866209	0	0
T1	196275	129	0	0
T2	81766	0	0	0
T3	537933	1156	0	0
T4	175524	0	0	0
T5	441618	5	0	0
T6	150544	513278	0	0
T7	178037	3	0	0
T8	366908	0	0	0
T9	279982	86	0	0
T10	84044	65	0	0
T11	0	1083	0	0
T12	0	7	0	0
T13	0	94	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	201197261	0	0
T1	196275	196194	0	0
T2	81766	81709	0	0
T3	537933	537536	0	0
T4	175524	175427	0	0
T5	441618	440257	0	0
T6	150544	150532	0	0
T7	178037	177803	0	0
T8	366908	366712	0	0
T9	279982	279868	0	0
T10	84044	83881	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	132559715	0	0
T1	196275	195237	0	0
T2	81766	81595	0	0
T3	537933	531122	0	0
T4	175524	175246	0	0
T5	441618	430493	0	0
T6	150544	171707	0	0
T7	178037	176603	0	0
T8	366908	366215	0	0
T9	279982	278563	0	0
T10	84044	82002	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	68515089	0	0
T1	196275	867	0	0
T2	81766	63	0	0
T3	537933	6184	0	0
T4	175524	138	0	0
T5	441618	8501	0	0
T6	150544	133330	0	0
T7	178037	10413	0	0
T8	366908	288	0	0
T9	279982	1195	0	0
T10	84044	1680	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	132681006	0	0
T1	196275	195326	0	0
T2	81766	81645	0	0
T3	537933	531347	0	0
T4	175524	175288	0	0
T5	441618	431743	0	0
T6	150544	172016	0	0
T7	178037	176760	0	0
T8	366908	366423	0	0
T9	279982	278671	0	0
T10	84044	82199	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	70	0	0
T16	16700	0	0	0
T27	83371	20	0	0
T28	0	10	0	0
T29	0	10	0	0
T31	0	20	0	0
T32	0	10	0	0
T33	161398	0	0	0
T34	109053	0	0	0
T35	369567	0	0	0
T36	246730	0	0	0
T37	88196	0	0	0
T38	114004	0	0	0
T39	8560	0	0	0
T40	417191	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	447	0	0
T7	178037	5	0	0
T8	366908	0	0	0
T9	279982	0	0	0
T10	84044	0	0	0
T11	836516	0	0	0
T12	607289	21	0	0
T13	198317	0	0	0
T19	0	5	0	0
T20	0	10	0	0
T24	0	10	0	0
T25	0	6	0	0
T26	0	10	0	0
T30	149720	0	0	0
T41	0	10	0	0
T42	0	10	0	0
T43	0	5	0	0
T44	206082	0	0	0
T45	151509	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201368213	0	0	0