ROM_CTRL/32KB Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.990s	4.109ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.490s	5.950ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.330s	7.737ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.460s	8.435ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.910s	1.903ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.320s	8.237ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.330s	7.737ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.910s	1.903ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.360s	1.807ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.090s	2.458ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.420s	4.300ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.999m	22.355ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.560s	17.382ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.920s	2.129ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.950s	1.936ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.950s	1.936ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.490s	5.950ms	5	5	100.00
		rom_ctrl_csr_rw	15.330s	7.737ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.910s	1.903ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.160s	2.121ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.490s	5.950ms	5	5	100.00
		rom_ctrl_csr_rw	15.330s	7.737ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.910s	1.903ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.160s	2.121ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.739m	53.226ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.787m	1.939ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.317m	9.184ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.787m	1.939ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.787m	1.939ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.787m	1.939ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.990s	4.109ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.990s	4.109ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.990s	4.109ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.317m	9.184ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.560s	17.382ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.584m	63.261ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.739m	53.226ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.787m	1.939ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.694h	70.055ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	96.97	93.01	97.88	100.00	98.69	98.03	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.16845053835841096445320657182691269171810156625215797179981965498431099082096
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 108479697 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 108479697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.rom_ctrl_stress_all_with_rand_reset.28038687620980899628867865575891279777006685098229705296863228223544065363172
      Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 442280615 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 442280615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.18312484715570383327067083224414948731156857980549706566078750627333146363698
      Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10515539658 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x4d0ebaff
        UVM_INFO @ 10515539658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.rom_ctrl_stress_all_with_rand_reset.72333769156537788796706264788650211613708218912934787761507663161755766599817
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11542803524 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc58ae125
        UVM_INFO @ 11542803524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

    • 8.rom_ctrl_stress_all_with_rand_reset.34957704630003630601396719630610229251819127200290850004185540026033723970189
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:7ffa1ab9-63d4-4651-bf80-a026a53bd046
      

    • 21.rom_ctrl_stress_all_with_rand_reset.101627616162710258194710524818617748419738221573698349568884093882444347671232
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:572e1547-e007-469b-bb1d-dd6b25324b9e
      

    • ... and 2 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

  • Test rom_ctrl_tl_errors has 1 failures.

    • 5.rom_ctrl_tl_errors.110978243628705331798250331096733914471175724677934537559845583867255681703123
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest/run.log

        UVM_ERROR @ 1382054098 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 1382054098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.rom_ctrl_stress_all_with_rand_reset.64595105397002225905360226718389663211966558057608541176488008685545811375096
      Line 375, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 145402083534 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 145402083534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.22_07.31.13