Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

988119

1

T6

333

T7

94872

T8

241

full_word

611596

1

T1

4

T6

40

T7

57344

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1599415	1			T1	4		T6	373		T7	152216
auto[TlIntgErrCmd]	111	1			T57	4		T58	4		T59	7
auto[TlIntgErrData]	96	1			T57	2		T58	5		T59	8
auto[TlIntgErrBoth]	93	1			T57	4		T58	1		T59	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267446

1

T1

4

T6

373

T7

23424

auto[1]

1332269

1

T7

128792

T19

35648

T20

227563

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	121698	1			T6	333		T7	10080		T8	241
auto[TlIntgErrNone]	partial	auto[1]	866154	1			T7	84792		T19	21903		T20	148442
auto[TlIntgErrNone]	full_word	auto[0]	145610	1			T1	4		T6	40		T7	13344
auto[TlIntgErrNone]	full_word	auto[1]	465953	1			T7	44000		T19	13745		T20	79121
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T58	2		T59	4		T116	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T57	4		T58	2		T59	2
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T59	1		T117	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T118	1		T121	2		T122	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T58	1		T117	3		T118	4
auto[TlIntgErrData]	partial	auto[1]	37	1			T58	4		T59	7		T117	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T57	1		T117	1		T123	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T57	1		T59	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T57	3		T58	1		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T57	1		T59	3		T116	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T124	1		T121	1		T125	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T117	1		T124	1