Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2034722

1

T1

73

T2

265

T4

169

full_word

1292332

1

T1

8

T2

33

T4

15

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3326784	1			T1	81		T2	298		T4	184
auto[TlIntgErrCmd]	86	1			T52	1		T53	6		T54	4
auto[TlIntgErrData]	95	1			T52	4		T53	8		T54	2
auto[TlIntgErrBoth]	89	1			T52	5		T53	6		T54	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

541060

1

T1

81

T2

298

T4

184

auto[1]

2785994

1

T6

166962

T8

53142

T29

314072

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	233602	1			T1	73		T2	265		T4	169
auto[TlIntgErrNone]	partial	auto[1]	1800871	1			T6	107292		T8	34330		T29	203131
auto[TlIntgErrNone]	full_word	auto[0]	307332	1			T1	8		T2	33		T4	15
auto[TlIntgErrNone]	full_word	auto[1]	984979	1			T6	59670		T8	18812		T29	110941
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T53	3		T54	3		T108	2
auto[TlIntgErrCmd]	partial	auto[1]	36	1			T52	1		T53	3		T54	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T111	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T108	1		T109	2		T113	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T52	1		T53	3		T108	4
auto[TlIntgErrData]	partial	auto[1]	50	1			T52	3		T53	2		T54	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T53	1		T112	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T53	2		T112	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T53	1		T54	2		T108	4
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T52	5		T53	3		T54	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T106	1		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T53	2		T54	1		T116	1