Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
ALWAYS | 113 | 7 | 7 | 100.00 |
ALWAYS | 125 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
41 |
1 |
1 |
42 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
61 |
1 |
1 |
68 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
115 |
1 |
1 |
116 |
|
unreachable |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
|
|
|
MISSING_ELSE |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
41 |
1 |
1 |
42 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
61 |
1 |
1 |
68 |
1 |
1 |
109 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 20 | 20 | 100.00 |
Logical | 20 | 20 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 51
SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 52
EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 52
SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 59
EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 61
EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 68
EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 68
SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 68
SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 23 | 21 | 91.30 |
Logical | 23 | 21 | 91.30 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 51
SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 52
EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 52
SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 59
EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 61
EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 68
EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 68
SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T6,T11,T12 |
1 | Covered | T1,T2,T3 |
LINE 68
SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T6,T11,T12 |
1 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
11 |
11 |
100.00 |
TERNARY |
68 |
3 |
3 |
100.00 |
IF |
113 |
4 |
4 |
100.00 |
IF |
125 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 (full_o) ?
-2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T11,T12 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 113 if ((!rst_ni))
-2-: 115 if (clr_i)
-3-: 117 if (wptr_wrap_set)
-4-: 119 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 125 if ((!rst_ni))
-2-: 127 if (clr_i)
-3-: 129 if (rptr_wrap_set)
-4-: 131 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
68 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 (full_o) ?
-2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T11,T12 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T6,T11,T12 |
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
ALWAYS | 113 | 7 | 7 | 100.00 |
ALWAYS | 125 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
41 |
1 |
1 |
42 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
61 |
1 |
1 |
68 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
115 |
1 |
1 |
116 |
|
unreachable |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
|
|
|
MISSING_ELSE |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 20 | 18 | 90.00 |
Logical | 20 | 18 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 51
SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 52
EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 52
SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 59
EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 61
EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 68
EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 68
SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 68
SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
11 |
10 |
90.91 |
TERNARY |
68 |
3 |
2 |
66.67 |
IF |
113 |
4 |
4 |
100.00 |
IF |
125 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 (full_o) ?
-2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 113 if ((!rst_ni))
-2-: 115 if (clr_i)
-3-: 117 if (wptr_wrap_set)
-4-: 119 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 125 if ((!rst_ni))
-2-: 127 if (clr_i)
-3-: 129 if (rptr_wrap_set)
-4-: 131 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
41 |
1 |
1 |
42 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
61 |
1 |
1 |
68 |
1 |
1 |
109 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 23 | 21 | 91.30 |
Logical | 23 | 21 | 91.30 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 51
SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 52
EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 52
SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 59
EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 61
EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 68
EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 68
SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T6,T11,T12 |
1 | Covered | T1,T2,T3 |
LINE 68
SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T6,T11,T12 |
1 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
TERNARY |
68 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 (full_o) ?
-2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T11,T12 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T6,T11,T12 |
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
ALWAYS | 113 | 7 | 7 | 100.00 |
ALWAYS | 125 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
41 |
1 |
1 |
42 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
61 |
1 |
1 |
68 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
115 |
1 |
1 |
116 |
|
unreachable |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
|
|
|
MISSING_ELSE |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 20 | 20 | 100.00 |
Logical | 20 | 20 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 51
EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 51
SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 52
EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
-----1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 52
SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 59
EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 61
EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 68
EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T11,T12 |
LINE 68
SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 68
SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
11 |
11 |
100.00 |
TERNARY |
68 |
3 |
3 |
100.00 |
IF |
113 |
4 |
4 |
100.00 |
IF |
125 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 68 (full_o) ?
-2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T11,T12 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 113 if ((!rst_ni))
-2-: 115 if (clr_i)
-3-: 117 if (wptr_wrap_set)
-4-: 119 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 125 if ((!rst_ni))
-2-: 127 if (clr_i)
-3-: 129 if (rptr_wrap_set)
-4-: 131 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |