Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3342330

1

T1

111

T2

338

T3

43

full_word

2155058

1

T1

7

T2

38

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5497058	1			T1	118		T2	376		T3	47
auto[TlIntgErrCmd]	116	1			T61	3		T62	7		T63	6
auto[TlIntgErrData]	107	1			T61	4		T62	6		T63	2
auto[TlIntgErrBoth]	107	1			T61	3		T62	7		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875514

1

T1

118

T2

376

T3

47

auto[1]

4621874

1

T22

393001

T12

234228

T23

91204

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	365656	1			T1	111		T2	338		T3	43
auto[TlIntgErrNone]	partial	auto[1]	2976382	1			T22	255598		T12	151559		T23	58949
auto[TlIntgErrNone]	full_word	auto[0]	509705	1			T1	7		T2	38		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	1645315	1			T22	137403		T12	82669		T23	32255
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T61	2		T62	2		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T61	1		T62	4		T63	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T62	1		T122	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T63	1		T116	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T61	1		T62	3		T116	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T61	1		T62	3		T63	1
auto[TlIntgErrData]	full_word	auto[0]	10	1			T61	1		T63	1		T116	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T61	1		T119	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T62	3		T63	1		T112	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T61	3		T62	2		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T113	1		T114	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T62	2		T119	1		T122	1