Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1551184

1

T5

144

T6

76

T8

68

full_word

1007349

1

T5

16

T6

9

T8

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2558223	1			T5	160		T6	85		T8	77
auto[TlIntgErrCmd]	82	1			T55	2		T56	3		T57	5
auto[TlIntgErrData]	125	1			T55	4		T56	6		T57	6
auto[TlIntgErrBoth]	103	1			T55	4		T56	1		T57	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417872

1

T5

160

T6

85

T8

77

auto[1]

2140661

1

T11

521743

T22

186817

T23

71939

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	178128	1			T5	144		T6	76		T8	68
auto[TlIntgErrNone]	partial	auto[1]	1372773	1			T11	334341		T22	121706		T23	44548
auto[TlIntgErrNone]	full_word	auto[0]	239606	1			T5	16		T6	9		T8	9
auto[TlIntgErrNone]	full_word	auto[1]	767716	1			T11	187402		T22	65111		T23	27391
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T57	2		T102	1		T97	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T55	2		T56	3		T57	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T100	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T102	1		T103	2		T108	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T55	1		T56	3		T57	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T55	1		T56	3		T57	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T55	2		T103	1		T104	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T57	1		T107	1		T104	3
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T55	2		T57	4		T102	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T55	2		T56	1		T57	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T97	1		T104	1		T100	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T109	1		T108	1		T101	1