Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67147	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2201354

1

T1

7

T2

146890

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	573501	1			T1	83		T2	37467		T3	42
values[0x0]	832271	1			T2	55861		T12	69988		T13	49756
values[0x1]	862729	1			T2	57225		T12	72786		T13	51446

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2231764

1

T1

45

T2

148516

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8858	1			T1	1		T2	574		T7	7
valid_sources[0x01]	8996	1			T2	591		T12	745		T73	41
valid_sources[0x02]	8843	1			T2	574		T12	714		T13	499
valid_sources[0x03]	9277	1			T2	639		T3	2		T12	706
valid_sources[0x04]	10219	1			T2	589		T7	3		T12	688
valid_sources[0x05]	8966	1			T1	1		T2	583		T12	812
valid_sources[0x06]	10031	1			T2	562		T3	1		T7	1
valid_sources[0x07]	8928	1			T2	577		T7	1		T19	1
valid_sources[0x08]	9032	1			T1	1		T2	671		T7	1
valid_sources[0x09]	8750	1			T2	555		T12	655		T97	2
valid_sources[0x0a]	8651	1			T2	599		T7	2		T12	702
valid_sources[0x0b]	8855	1			T2	588		T20	2		T12	761
valid_sources[0x0c]	8841	1			T2	579		T19	1		T20	4
valid_sources[0x0d]	9500	1			T2	586		T3	1		T7	1
valid_sources[0x0e]	9309	1			T1	1		T2	594		T19	2
valid_sources[0x0f]	8260	1			T2	565		T12	705		T13	575
valid_sources[0x10]	8688	1			T2	593		T20	2		T12	752
valid_sources[0x11]	8467	1			T1	1		T2	604		T19	1
valid_sources[0x12]	8673	1			T2	647		T19	1		T20	1
valid_sources[0x13]	8813	1			T2	593		T3	1		T19	1
valid_sources[0x14]	9935	1			T2	655		T12	690		T13	498
valid_sources[0x15]	8591	1			T2	642		T3	1		T44	1
valid_sources[0x16]	8639	1			T1	1		T2	617		T4	2
valid_sources[0x17]	8920	1			T1	1		T2	515		T7	1
valid_sources[0x18]	8891	1			T2	588		T44	3		T12	746
valid_sources[0x19]	8698	1			T2	605		T20	2		T12	700
valid_sources[0x1a]	9094	1			T2	560		T19	2		T20	2
valid_sources[0x1b]	8656	1			T2	578		T7	1		T19	1
valid_sources[0x1c]	9310	1			T2	576		T19	2		T20	1
valid_sources[0x1d]	9085	1			T1	1		T2	600		T12	776
valid_sources[0x1e]	8912	1			T2	610		T7	1		T20	3
valid_sources[0x1f]	8288	1			T2	601		T7	1		T20	1
valid_sources[0x20]	8298	1			T2	567		T12	745		T13	549
valid_sources[0x21]	8761	1			T2	588		T7	4		T12	763
valid_sources[0x22]	8910	1			T2	598		T7	1		T19	1
valid_sources[0x23]	9595	1			T2	563		T19	1		T20	2
valid_sources[0x24]	8942	1			T2	599		T20	1		T12	826
valid_sources[0x25]	8471	1			T1	1		T2	619		T7	2
valid_sources[0x26]	9310	1			T2	589		T20	1		T12	680
valid_sources[0x27]	8388	1			T2	611		T19	1		T12	762
valid_sources[0x28]	8392	1			T2	590		T7	1		T12	748
valid_sources[0x29]	8803	1			T2	581		T12	773		T13	515
valid_sources[0x2a]	8593	1			T2	549		T7	3		T20	1
valid_sources[0x2b]	9889	1			T2	587		T19	2		T12	744
valid_sources[0x2c]	8165	1			T2	559		T12	705		T13	481
valid_sources[0x2d]	8656	1			T1	1		T2	596		T19	1
valid_sources[0x2e]	8821	1			T2	547		T7	1		T12	781
valid_sources[0x2f]	8351	1			T2	582		T7	2		T12	710
valid_sources[0x30]	8367	1			T2	574		T12	780		T13	533
valid_sources[0x31]	8794	1			T2	570		T7	1		T19	1
valid_sources[0x32]	8858	1			T2	625		T3	1		T7	2
valid_sources[0x33]	9044	1			T2	543		T20	2		T12	739
valid_sources[0x34]	8570	1			T1	2		T2	596		T19	1
valid_sources[0x35]	8375	1			T2	565		T19	1		T12	753
valid_sources[0x36]	9290	1			T1	1		T2	599		T7	3
valid_sources[0x37]	8749	1			T2	595		T20	1		T12	620
valid_sources[0x38]	9047	1			T1	3		T2	594		T7	3
valid_sources[0x39]	9980	1			T2	550		T3	1		T7	4
valid_sources[0x3a]	9370	1			T2	575		T12	758		T13	579
valid_sources[0x3b]	8966	1			T1	2		T2	588		T19	1
valid_sources[0x3c]	8741	1			T2	587		T96	19		T12	786
valid_sources[0x3d]	8524	1			T2	597		T12	714		T13	503
valid_sources[0x3e]	8802	1			T2	602		T7	1		T12	753
valid_sources[0x3f]	9371	1			T1	1		T2	628		T12	801
valid_sources[0x40]	8478	1			T1	3		T2	545		T7	1
valid_sources[0x41]	8682	1			T2	625		T20	2		T12	714
valid_sources[0x42]	8454	1			T2	589		T20	1		T12	635
valid_sources[0x43]	9704	1			T2	597		T20	1		T12	699
valid_sources[0x44]	8944	1			T2	575		T3	1		T19	1
valid_sources[0x45]	8982	1			T2	571		T3	2		T44	4
valid_sources[0x46]	8227	1			T2	618		T7	2		T12	744
valid_sources[0x47]	8470	1			T2	623		T20	1		T12	728
valid_sources[0x48]	8748	1			T2	580		T19	1		T12	792
valid_sources[0x49]	8745	1			T2	573		T12	778		T13	465
valid_sources[0x4a]	8927	1			T1	3		T2	555		T7	2
valid_sources[0x4b]	8484	1			T2	575		T12	701		T13	512
valid_sources[0x4c]	9171	1			T2	530		T7	6		T20	1
valid_sources[0x4d]	8388	1			T2	562		T12	751		T13	522
valid_sources[0x4e]	8450	1			T2	625		T7	1		T12	738
valid_sources[0x4f]	8729	1			T2	576		T19	1		T20	1
valid_sources[0x50]	8505	1			T2	578		T7	2		T12	752
valid_sources[0x51]	9219	1			T2	566		T20	3		T12	784
valid_sources[0x52]	9300	1			T1	2		T2	620		T7	2
valid_sources[0x53]	8812	1			T2	607		T4	2		T12	740
valid_sources[0x54]	8585	1			T2	582		T7	1		T19	1
valid_sources[0x55]	8580	1			T2	597		T7	2		T19	2
valid_sources[0x56]	9847	1			T2	552		T7	2		T18	2
valid_sources[0x57]	8888	1			T2	564		T44	6		T12	740
valid_sources[0x58]	8721	1			T2	591		T12	842		T13	476
valid_sources[0x59]	8412	1			T1	2		T2	580		T7	4
valid_sources[0x5a]	8475	1			T2	574		T7	1		T20	2
valid_sources[0x5b]	8300	1			T1	1		T2	598		T20	1
valid_sources[0x5c]	8423	1			T2	571		T44	2		T12	769
valid_sources[0x5d]	8523	1			T2	539		T12	731		T13	537
valid_sources[0x5e]	9028	1			T2	565		T4	7		T11	41
valid_sources[0x5f]	8745	1			T2	564		T44	5		T12	758
valid_sources[0x60]	8783	1			T2	610		T20	1		T12	740
valid_sources[0x61]	8488	1			T2	559		T19	2		T20	4
valid_sources[0x62]	8484	1			T2	583		T7	1		T19	1
valid_sources[0x63]	8940	1			T2	595		T7	2		T12	719
valid_sources[0x64]	8428	1			T2	582		T12	810		T13	511
valid_sources[0x65]	8422	1			T2	545		T19	1		T20	2
valid_sources[0x66]	9361	1			T2	574		T19	1		T12	822
valid_sources[0x67]	8316	1			T2	565		T7	3		T20	3
valid_sources[0x68]	8799	1			T1	1		T2	596		T19	1
valid_sources[0x69]	9065	1			T2	593		T4	1		T20	2
valid_sources[0x6a]	8793	1			T1	1		T2	626		T7	5
valid_sources[0x6b]	8836	1			T2	561		T7	2		T12	822
valid_sources[0x6c]	8700	1			T2	626		T4	1		T20	1
valid_sources[0x6d]	8791	1			T2	634		T20	1		T12	757
valid_sources[0x6e]	8319	1			T1	1		T2	623		T3	1
valid_sources[0x6f]	8486	1			T2	577		T7	5		T14	3
valid_sources[0x70]	8723	1			T2	588		T12	709		T13	493
valid_sources[0x71]	8872	1			T1	1		T2	579		T4	13
valid_sources[0x72]	8899	1			T2	591		T7	4		T12	763
valid_sources[0x73]	9346	1			T2	582		T12	743		T13	604
valid_sources[0x74]	9172	1			T2	635		T7	1		T19	1
valid_sources[0x75]	9103	1			T2	581		T20	1		T12	760
valid_sources[0x76]	9462	1			T2	527		T20	2		T12	741
valid_sources[0x77]	8493	1			T2	571		T12	712		T13	557
valid_sources[0x78]	8800	1			T2	599		T19	1		T20	1
valid_sources[0x79]	9223	1			T1	1		T2	630		T7	2
valid_sources[0x7a]	9491	1			T2	603		T7	5		T11	16
valid_sources[0x7b]	9170	1			T1	1		T2	565		T7	2
valid_sources[0x7c]	9114	1			T2	589		T7	1		T19	2
valid_sources[0x7d]	9955	1			T1	1		T2	578		T12	743
valid_sources[0x7e]	8269	1			T1	2		T2	597		T12	758
valid_sources[0x7f]	8833	1			T2	615		T20	2		T12	751
valid_sources[0x80]	9076	1			T2	587		T4	6		T12	762

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

551903

1

T1

7

T2

36776

T3

6

values[0x0]

all_enables

biggest_size

824858

1

T2

55389

T12

69368

T13

49317

values[0x1]

all_enables

biggest_size

824593

1

T2

54725

T12

69555

T13

49275

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1656804

1

T1

16

T2

107999

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	446270	1			T1	32		T2	28957		T3	16
values[0x0]	633743	1			T2	41144		T5	2		T9	2
values[0x1]	736774	1			T2	48385		T5	4		T9	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	69468	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1747319

1

T1

23

T2

114098

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7190	1			T2	540		T44	2		T12	631
valid_sources[0x01]	6490	1			T2	499		T12	636		T13	420
valid_sources[0x02]	7017	1			T2	522		T12	584		T13	498
valid_sources[0x03]	6648	1			T1	2		T2	484		T12	646
valid_sources[0x04]	7106	1			T2	649		T9	2		T12	610
valid_sources[0x05]	6315	1			T2	443		T3	7		T12	635
valid_sources[0x06]	7326	1			T1	4		T2	486		T44	3
valid_sources[0x07]	7819	1			T2	379		T12	624		T13	384
valid_sources[0x08]	7022	1			T2	425		T43	3		T12	639
valid_sources[0x09]	6002	1			T2	465		T12	557		T22	1
valid_sources[0x0a]	6294	1			T2	538		T10	1		T12	565
valid_sources[0x0b]	7183	1			T2	529		T18	1		T12	649
valid_sources[0x0c]	7299	1			T2	453		T12	651		T13	502
valid_sources[0x0d]	6412	1			T1	2		T2	368		T12	594
valid_sources[0x0e]	7053	1			T2	445		T12	549		T13	440
valid_sources[0x0f]	7731	1			T2	495		T12	633		T13	538
valid_sources[0x10]	7126	1			T2	389		T12	629		T13	449
valid_sources[0x11]	7861	1			T2	634		T12	559		T13	398
valid_sources[0x12]	7960	1			T2	473		T12	625		T13	471
valid_sources[0x13]	6348	1			T1	2		T2	536		T12	633
valid_sources[0x14]	7088	1			T2	579		T12	609		T22	1
valid_sources[0x15]	8056	1			T2	548		T12	634		T13	441
valid_sources[0x16]	7265	1			T2	489		T12	602		T59	1
valid_sources[0x17]	6681	1			T2	547		T12	651		T13	465
valid_sources[0x18]	7086	1			T2	501		T3	1		T12	624
valid_sources[0x19]	7036	1			T2	370		T12	586		T13	371
valid_sources[0x1a]	6315	1			T2	608		T12	663		T13	479
valid_sources[0x1b]	7889	1			T2	484		T43	4		T12	590
valid_sources[0x1c]	7655	1			T2	393		T12	597		T13	425
valid_sources[0x1d]	7999	1			T2	585		T12	650		T13	536
valid_sources[0x1e]	6113	1			T2	507		T12	631		T13	388
valid_sources[0x1f]	6931	1			T1	1		T2	388		T12	605
valid_sources[0x20]	7211	1			T2	392		T9	2		T18	1
valid_sources[0x21]	6993	1			T2	373		T12	589		T13	515
valid_sources[0x22]	7393	1			T1	2		T2	463		T12	608
valid_sources[0x23]	7289	1			T2	485		T12	602		T13	508
valid_sources[0x24]	7285	1			T2	470		T12	569		T13	500
valid_sources[0x25]	5989	1			T2	309		T12	599		T73	1
valid_sources[0x26]	6154	1			T2	512		T43	1		T12	630
valid_sources[0x27]	7119	1			T2	448		T18	1		T12	619
valid_sources[0x28]	7262	1			T2	568		T12	583		T13	521
valid_sources[0x29]	7639	1			T1	2		T2	477		T12	623
valid_sources[0x2a]	5741	1			T2	316		T18	1		T14	4
valid_sources[0x2b]	7238	1			T2	401		T12	595		T59	2
valid_sources[0x2c]	6012	1			T2	438		T12	592		T73	1
valid_sources[0x2d]	6408	1			T2	457		T12	584		T13	280
valid_sources[0x2e]	6795	1			T2	550		T12	621		T13	397
valid_sources[0x2f]	6689	1			T2	370		T12	604		T13	391
valid_sources[0x30]	6932	1			T2	376		T18	1		T12	634
valid_sources[0x31]	7554	1			T2	507		T12	618		T97	48
valid_sources[0x32]	6603	1			T2	371		T18	1		T12	632
valid_sources[0x33]	6758	1			T2	494		T18	1		T12	611
valid_sources[0x34]	8316	1			T2	481		T12	644		T59	2
valid_sources[0x35]	7127	1			T2	550		T12	627		T73	1
valid_sources[0x36]	7349	1			T2	519		T12	604		T13	397
valid_sources[0x37]	7300	1			T2	441		T12	642		T13	451
valid_sources[0x38]	7355	1			T2	442		T18	1		T12	584
valid_sources[0x39]	6867	1			T2	418		T12	609		T22	1
valid_sources[0x3a]	7311	1			T2	548		T12	653		T13	423
valid_sources[0x3b]	6554	1			T2	328		T42	4		T12	626
valid_sources[0x3c]	6918	1			T2	360		T12	654		T22	1
valid_sources[0x3d]	7187	1			T2	479		T12	609		T13	449
valid_sources[0x3e]	7835	1			T2	466		T9	1		T12	653
valid_sources[0x3f]	6809	1			T2	407		T12	630		T22	1
valid_sources[0x40]	7238	1			T2	392		T10	3		T12	597
valid_sources[0x41]	7750	1			T2	447		T12	667		T13	535
valid_sources[0x42]	7298	1			T2	442		T18	1		T44	1
valid_sources[0x43]	7583	1			T2	685		T44	1		T12	621
valid_sources[0x44]	7326	1			T2	587		T3	2		T12	590
valid_sources[0x45]	6476	1			T2	584		T18	1		T12	609
valid_sources[0x46]	7530	1			T2	391		T12	553		T59	1
valid_sources[0x47]	7055	1			T2	469		T12	621		T13	433
valid_sources[0x48]	7535	1			T2	491		T12	610		T13	370
valid_sources[0x49]	6768	1			T2	454		T12	595		T13	622
valid_sources[0x4a]	6773	1			T2	416		T44	2		T12	609
valid_sources[0x4b]	6817	1			T2	510		T18	1		T12	634
valid_sources[0x4c]	6797	1			T2	459		T44	2		T12	663
valid_sources[0x4d]	7201	1			T2	496		T18	3		T12	586
valid_sources[0x4e]	7604	1			T2	511		T12	609		T13	472
valid_sources[0x4f]	7754	1			T2	444		T12	614		T13	432
valid_sources[0x50]	6400	1			T2	370		T12	656		T13	464
valid_sources[0x51]	7254	1			T2	402		T12	647		T13	430
valid_sources[0x52]	7974	1			T2	457		T12	649		T13	466
valid_sources[0x53]	7087	1			T2	471		T18	1		T12	610
valid_sources[0x54]	6471	1			T2	339		T12	617		T13	417
valid_sources[0x55]	5979	1			T2	597		T10	1		T12	606
valid_sources[0x56]	7649	1			T2	564		T3	1		T12	642
valid_sources[0x57]	7748	1			T2	524		T14	3		T12	637
valid_sources[0x58]	6468	1			T2	393		T12	625		T13	415
valid_sources[0x59]	7353	1			T2	492		T12	633		T22	1
valid_sources[0x5a]	6228	1			T2	460		T12	568		T73	1
valid_sources[0x5b]	7587	1			T2	543		T12	655		T13	441
valid_sources[0x5c]	6887	1			T2	519		T18	1		T12	593
valid_sources[0x5d]	7584	1			T2	465		T12	622		T73	1
valid_sources[0x5e]	6570	1			T2	420		T12	628		T22	1
valid_sources[0x5f]	7819	1			T2	498		T12	623		T13	461
valid_sources[0x60]	6638	1			T2	507		T12	627		T13	479
valid_sources[0x61]	7027	1			T2	636		T12	616		T13	267
valid_sources[0x62]	7662	1			T2	480		T12	569		T59	1
valid_sources[0x63]	7713	1			T2	506		T12	625		T59	1
valid_sources[0x64]	8040	1			T2	519		T12	640		T13	500
valid_sources[0x65]	7713	1			T2	427		T12	596		T22	2
valid_sources[0x66]	7471	1			T2	520		T18	1		T12	627
valid_sources[0x67]	6784	1			T2	369		T12	643		T13	424
valid_sources[0x68]	7184	1			T2	470		T12	649		T13	484
valid_sources[0x69]	6742	1			T2	502		T12	571		T13	385
valid_sources[0x6a]	7467	1			T2	440		T10	2		T18	1
valid_sources[0x6b]	8243	1			T2	479		T12	609		T13	396
valid_sources[0x6c]	7465	1			T2	475		T10	1		T18	1
valid_sources[0x6d]	7627	1			T2	531		T9	2		T12	616
valid_sources[0x6e]	6745	1			T2	358		T44	5		T12	611
valid_sources[0x6f]	6629	1			T2	485		T12	651		T73	2
valid_sources[0x70]	6707	1			T2	511		T18	1		T12	578
valid_sources[0x71]	7408	1			T2	451		T3	2		T12	606
valid_sources[0x72]	7833	1			T1	1		T2	389		T12	599
valid_sources[0x73]	6732	1			T2	404		T12	587		T22	1
valid_sources[0x74]	7775	1			T2	483		T12	608		T22	1
valid_sources[0x75]	6233	1			T2	233		T12	593		T13	505
valid_sources[0x76]	6525	1			T2	416		T44	1		T12	618
valid_sources[0x77]	7207	1			T2	379		T12	636		T13	389
valid_sources[0x78]	7833	1			T2	554		T12	543		T13	468
valid_sources[0x79]	7317	1			T2	567		T8	1		T44	1
valid_sources[0x7a]	7558	1			T2	451		T12	598		T13	380
valid_sources[0x7b]	6386	1			T2	419		T12	648		T13	432
valid_sources[0x7c]	7638	1			T2	549		T12	602		T13	475
valid_sources[0x7d]	6860	1			T2	479		T18	1		T12	617
valid_sources[0x7e]	6879	1			T2	421		T12	547		T13	505
valid_sources[0x7f]	7180	1			T2	539		T12	603		T13	378
valid_sources[0x80]	7225	1			T2	471		T12	635		T13	465

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

415416

1

T1

16

T2

27184

T3

7

values[0x0]

all_enables

biggest_size

620666

1

T2

40301

T5

1

T10

4

values[0x1]

all_enables

biggest_size

620722

1

T2

40514

T5

1

T9

2