Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4031536

1

T1

76

T2

266009

T3

36

full_word

2572832

1

T1

7

T2

171212

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6604038	1			T1	83		T2	437221		T3	42
auto[TlIntgErrCmd]	113	1			T56	9		T57	8		T58	5
auto[TlIntgErrData]	110	1			T56	6		T57	7		T58	3
auto[TlIntgErrBoth]	107	1			T56	5		T57	5		T58	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025702

1

T1

83

T2

67495

T3

42

auto[1]

5578666

1

T2

369726

T12

465558

T13

334919

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	419653	1			T1	76		T2	27192		T3	36
auto[TlIntgErrNone]	partial	auto[1]	3611576	1			T2	238817		T12	300474		T13	217072
auto[TlIntgErrNone]	full_word	auto[0]	605899	1			T1	7		T2	40303		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	1966910	1			T2	130909		T12	165084		T13	117847
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T56	5		T57	3		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T56	4		T57	5		T58	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T100	1		T101	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T99	1		T101	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T56	3		T57	4		T58	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T56	3		T57	3		T58	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T104	2		T102	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T100	1		T101	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T56	2		T57	4		T58	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T56	3		T57	1		T58	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T99	1		T105	1		T103	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T110	1		T111	1		-	-