Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60016	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1782146

1

T3

6

T6

7

T7

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	469571	1			T3	6		T6	95		T7	100
values[0x0]	674419	1			T10	78302		T12	18804		T23	37936
values[0x1]	698172	1			T10	81146		T12	19872		T23	39513

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1809926

1

T3

6

T6

61

T7

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7309	1			T10	628		T15	1		T12	178
valid_sources[0x01]	6974	1			T10	943		T12	209		T71	1
valid_sources[0x02]	7429	1			T9	27		T10	624		T12	207
valid_sources[0x03]	7462	1			T7	1		T8	3		T10	1041
valid_sources[0x04]	6725	1			T10	695		T12	181		T71	3
valid_sources[0x05]	6982	1			T8	1		T10	978		T12	219
valid_sources[0x06]	8684	1			T8	2		T10	900		T12	188
valid_sources[0x07]	7406	1			T10	1031		T11	1		T12	175
valid_sources[0x08]	7205	1			T10	611		T12	212		T48	2
valid_sources[0x09]	7176	1			T8	4		T10	1020		T12	189
valid_sources[0x0a]	7262	1			T10	671		T12	236		T48	2
valid_sources[0x0b]	7221	1			T8	1		T10	832		T12	184
valid_sources[0x0c]	7315	1			T10	785		T12	178		T116	2
valid_sources[0x0d]	7274	1			T10	1199		T12	206		T48	1
valid_sources[0x0e]	7083	1			T8	1		T10	955		T12	201
valid_sources[0x0f]	7207	1			T9	23		T10	728		T12	194
valid_sources[0x10]	7550	1			T10	870		T12	196		T71	2
valid_sources[0x11]	6735	1			T7	2		T10	621		T12	227
valid_sources[0x12]	6754	1			T10	770		T15	2		T12	180
valid_sources[0x13]	6674	1			T8	1		T10	636		T11	2
valid_sources[0x14]	6655	1			T10	660		T12	191		T48	1
valid_sources[0x15]	7091	1			T10	767		T12	219		T48	1
valid_sources[0x16]	6898	1			T10	819		T15	1		T12	228
valid_sources[0x17]	7019	1			T10	785		T12	191		T71	1
valid_sources[0x18]	7487	1			T8	1		T10	917		T12	243
valid_sources[0x19]	7528	1			T10	831		T12	182		T48	1
valid_sources[0x1a]	7098	1			T6	31		T10	713		T12	193
valid_sources[0x1b]	6997	1			T8	1		T10	760		T11	1
valid_sources[0x1c]	8136	1			T10	882		T12	173		T48	2
valid_sources[0x1d]	6953	1			T8	3		T10	762		T12	179
valid_sources[0x1e]	7095	1			T10	702		T15	1		T12	213
valid_sources[0x1f]	7456	1			T10	886		T12	178		T48	1
valid_sources[0x20]	7263	1			T10	981		T12	208		T71	2
valid_sources[0x21]	7080	1			T7	2		T9	34		T10	832
valid_sources[0x22]	7068	1			T10	1016		T12	175		T19	1
valid_sources[0x23]	7381	1			T8	1		T10	945		T12	196
valid_sources[0x24]	8179	1			T10	1058		T12	204		T48	1
valid_sources[0x25]	6982	1			T10	589		T12	234		T48	1
valid_sources[0x26]	7539	1			T10	967		T12	194		T72	1
valid_sources[0x27]	7002	1			T7	4		T10	901		T12	196
valid_sources[0x28]	7226	1			T10	994		T11	4		T12	231
valid_sources[0x29]	6841	1			T8	2		T10	727		T15	4
valid_sources[0x2a]	7842	1			T8	2		T10	781		T15	2
valid_sources[0x2b]	6947	1			T10	694		T12	207		T48	2
valid_sources[0x2c]	7157	1			T8	2		T10	818		T12	209
valid_sources[0x2d]	7904	1			T10	879		T12	185		T48	3
valid_sources[0x2e]	7691	1			T8	1		T10	723		T15	1
valid_sources[0x2f]	6874	1			T10	947		T12	207		T48	1
valid_sources[0x30]	7261	1			T7	1		T10	1019		T12	172
valid_sources[0x31]	6857	1			T10	927		T12	170		T48	2
valid_sources[0x32]	6788	1			T8	2		T10	664		T12	201
valid_sources[0x33]	7110	1			T10	968		T12	222		T44	1
valid_sources[0x34]	7140	1			T8	2		T10	933		T12	215
valid_sources[0x35]	6950	1			T10	843		T12	199		T48	2
valid_sources[0x36]	7143	1			T10	1055		T12	217		T71	2
valid_sources[0x37]	6661	1			T8	1		T10	668		T12	195
valid_sources[0x38]	7669	1			T8	1		T10	813		T12	196
valid_sources[0x39]	7398	1			T8	2		T10	918		T12	175
valid_sources[0x3a]	6808	1			T7	14		T10	776		T15	1
valid_sources[0x3b]	6824	1			T8	1		T10	723		T15	1
valid_sources[0x3c]	7150	1			T10	751		T12	199		T116	2
valid_sources[0x3d]	7364	1			T8	2		T10	1023		T12	196
valid_sources[0x3e]	7203	1			T8	1		T10	847		T12	231
valid_sources[0x3f]	7223	1			T7	1		T10	1057		T15	2
valid_sources[0x40]	7195	1			T10	1088		T15	1		T12	218
valid_sources[0x41]	8074	1			T8	2		T10	819		T12	236
valid_sources[0x42]	6917	1			T10	752		T12	160		T48	1
valid_sources[0x43]	7101	1			T8	1		T10	622		T15	1
valid_sources[0x44]	7513	1			T8	1		T10	785		T12	189
valid_sources[0x45]	7564	1			T8	4		T10	698		T12	215
valid_sources[0x46]	7076	1			T7	1		T8	1		T10	766
valid_sources[0x47]	6678	1			T8	1		T10	624		T12	190
valid_sources[0x48]	6868	1			T10	764		T12	167		T48	3
valid_sources[0x49]	7269	1			T10	985		T15	1		T12	248
valid_sources[0x4a]	7299	1			T10	947		T12	234		T71	1
valid_sources[0x4b]	6628	1			T8	3		T10	769		T15	2
valid_sources[0x4c]	7087	1			T10	838		T15	1		T12	198
valid_sources[0x4d]	8145	1			T10	853		T15	1		T12	167
valid_sources[0x4e]	7181	1			T10	953		T12	181		T48	1
valid_sources[0x4f]	6751	1			T8	3		T10	677		T12	180
valid_sources[0x50]	7629	1			T10	743		T12	202		T48	5
valid_sources[0x51]	6976	1			T8	1		T10	710		T15	1
valid_sources[0x52]	6925	1			T8	1		T10	889		T12	204
valid_sources[0x53]	6592	1			T10	599		T12	196		T81	1
valid_sources[0x54]	7544	1			T10	873		T12	218		T48	1
valid_sources[0x55]	7643	1			T10	1001		T14	17		T12	189
valid_sources[0x56]	7310	1			T8	1		T10	1038		T12	235
valid_sources[0x57]	7755	1			T10	710		T12	220		T19	1
valid_sources[0x58]	7963	1			T8	1		T10	777		T11	3
valid_sources[0x59]	7293	1			T7	1		T8	3		T10	838
valid_sources[0x5a]	6623	1			T8	1		T10	692		T12	199
valid_sources[0x5b]	7399	1			T8	3		T10	955		T12	215
valid_sources[0x5c]	6948	1			T10	865		T12	199		T116	1
valid_sources[0x5d]	6920	1			T10	930		T15	1		T12	193
valid_sources[0x5e]	7281	1			T10	815		T12	195		T71	1
valid_sources[0x5f]	7019	1			T7	1		T8	1		T10	915
valid_sources[0x60]	7399	1			T8	3		T10	1104		T15	2
valid_sources[0x61]	6793	1			T10	913		T12	228		T132	3
valid_sources[0x62]	7284	1			T10	857		T12	199		T48	2
valid_sources[0x63]	7866	1			T8	1		T10	943		T15	1
valid_sources[0x64]	6999	1			T10	815		T12	183		T44	1
valid_sources[0x65]	7248	1			T8	1		T10	1161		T11	1
valid_sources[0x66]	7024	1			T8	2		T10	872		T12	198
valid_sources[0x67]	7337	1			T10	973		T12	215		T48	2
valid_sources[0x68]	7073	1			T10	761		T12	188		T48	2
valid_sources[0x69]	7148	1			T8	2		T10	547		T12	193
valid_sources[0x6a]	6811	1			T10	735		T15	2		T12	200
valid_sources[0x6b]	6947	1			T10	870		T12	203		T48	4
valid_sources[0x6c]	6776	1			T10	618		T12	232		T48	1
valid_sources[0x6d]	6975	1			T8	1		T10	888		T12	204
valid_sources[0x6e]	7148	1			T10	914		T12	205		T72	2
valid_sources[0x6f]	7087	1			T3	1		T8	1		T10	945
valid_sources[0x70]	6973	1			T7	2		T10	885		T12	209
valid_sources[0x71]	7116	1			T8	3		T10	892		T12	203
valid_sources[0x72]	8304	1			T10	1261		T12	209		T71	1
valid_sources[0x73]	7756	1			T7	2		T8	2		T10	850
valid_sources[0x74]	6806	1			T10	783		T12	179		T48	1
valid_sources[0x75]	8173	1			T10	823		T12	210		T48	1
valid_sources[0x76]	7732	1			T8	1		T10	848		T12	179
valid_sources[0x77]	7543	1			T8	2		T10	893		T14	43
valid_sources[0x78]	7346	1			T10	665		T12	227		T71	3
valid_sources[0x79]	7773	1			T10	684		T12	234		T72	1
valid_sources[0x7a]	6857	1			T8	2		T10	795		T12	205
valid_sources[0x7b]	7285	1			T7	6		T8	2		T10	1055
valid_sources[0x7c]	6973	1			T7	16		T8	1		T10	951
valid_sources[0x7d]	7040	1			T10	719		T12	192		T132	1
valid_sources[0x7e]	7084	1			T10	893		T12	178		T48	2
valid_sources[0x7f]	7371	1			T10	954		T14	24		T12	189
valid_sources[0x80]	7179	1			T8	1		T10	1070		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

446808

1

T3

6

T6

7

T7

10

values[0x0]

all_enables

biggest_size

668349

1

T10

77599

T12

18634

T23

37587

values[0x1]

all_enables

biggest_size

666989

1

T10

77425

T12

18960

T23

37686

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1346695

1

T2

1

T3

15

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	363338	1			T2	1		T3	24		T10	42307
values[0x0]	514614	1			T4	4		T5	5		T10	59835
values[0x1]	596684	1			T4	5		T5	3		T10	69331

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56135	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1418501

1

T2

1

T3

16

T4

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4989	1			T10	547		T15	2		T12	51
valid_sources[0x01]	6074	1			T10	1458		T12	108		T71	2
valid_sources[0x02]	5377	1			T10	889		T60	2		T23	332
valid_sources[0x03]	4926	1			T10	365		T12	172		T23	323
valid_sources[0x04]	5855	1			T10	548		T12	9		T23	332
valid_sources[0x05]	5237	1			T10	217		T23	335		T56	348
valid_sources[0x06]	4542	1			T10	308		T60	2		T38	3
valid_sources[0x07]	6159	1			T10	758		T23	322		T56	15
valid_sources[0x08]	5806	1			T10	508		T23	346		T56	20
valid_sources[0x09]	6283	1			T10	407		T12	477		T23	327
valid_sources[0x0a]	6609	1			T10	869		T12	566		T60	1
valid_sources[0x0b]	6456	1			T10	549		T12	101		T23	345
valid_sources[0x0c]	5853	1			T10	446		T12	144		T71	1
valid_sources[0x0d]	5889	1			T10	418		T12	198		T23	327
valid_sources[0x0e]	7366	1			T10	1323		T12	630		T71	3
valid_sources[0x0f]	5337	1			T10	707		T12	1		T23	376
valid_sources[0x10]	6051	1			T10	875		T12	301		T23	332
valid_sources[0x11]	5326	1			T10	689		T12	152		T23	341
valid_sources[0x12]	5444	1			T10	656		T37	6		T23	327
valid_sources[0x13]	5097	1			T10	418		T69	1		T24	1
valid_sources[0x14]	6063	1			T10	977		T38	1		T23	317
valid_sources[0x15]	7034	1			T10	900		T12	251		T80	6
valid_sources[0x16]	5524	1			T10	886		T12	170		T71	1
valid_sources[0x17]	6954	1			T10	1077		T15	4		T12	185
valid_sources[0x18]	5382	1			T10	526		T12	160		T23	331
valid_sources[0x19]	6193	1			T5	1		T10	507		T12	240
valid_sources[0x1a]	5753	1			T10	693		T23	334		T56	79
valid_sources[0x1b]	7148	1			T10	993		T12	422		T81	2
valid_sources[0x1c]	5660	1			T10	583		T12	217		T23	319
valid_sources[0x1d]	5984	1			T10	672		T12	125		T60	1
valid_sources[0x1e]	5797	1			T10	501		T12	319		T23	290
valid_sources[0x1f]	5263	1			T10	402		T14	32		T12	478
valid_sources[0x20]	4570	1			T10	267		T17	1		T12	1
valid_sources[0x21]	5344	1			T10	679		T15	3		T12	232
valid_sources[0x22]	5653	1			T10	767		T12	369		T71	1
valid_sources[0x23]	6344	1			T10	345		T12	3		T23	345
valid_sources[0x24]	5440	1			T10	310		T12	32		T23	324
valid_sources[0x25]	5830	1			T10	860		T12	471		T23	310
valid_sources[0x26]	4585	1			T10	456		T12	202		T133	1
valid_sources[0x27]	6263	1			T10	588		T12	13		T23	331
valid_sources[0x28]	5588	1			T10	187		T12	349		T23	292
valid_sources[0x29]	6124	1			T10	921		T12	271		T23	321
valid_sources[0x2a]	5362	1			T10	544		T12	126		T23	322
valid_sources[0x2b]	5240	1			T10	558		T12	153		T71	1
valid_sources[0x2c]	5677	1			T10	823		T12	45		T23	370
valid_sources[0x2d]	5021	1			T5	1		T10	314		T11	16
valid_sources[0x2e]	5566	1			T10	362		T12	7		T23	327
valid_sources[0x2f]	6276	1			T10	673		T12	206		T55	1
valid_sources[0x30]	6095	1			T10	656		T23	331		T56	247
valid_sources[0x31]	5578	1			T10	1256		T12	98		T80	2
valid_sources[0x32]	5568	1			T10	561		T60	1		T19	25
valid_sources[0x33]	6652	1			T10	910		T15	1		T12	594
valid_sources[0x34]	6303	1			T10	713		T12	74		T23	318
valid_sources[0x35]	6572	1			T10	953		T12	523		T23	293
valid_sources[0x36]	7244	1			T10	879		T12	99		T71	4
valid_sources[0x37]	6557	1			T10	446		T12	648		T25	1
valid_sources[0x38]	6421	1			T10	426		T12	82		T23	335
valid_sources[0x39]	5753	1			T10	606		T12	506		T23	320
valid_sources[0x3a]	6394	1			T2	1		T10	1292		T36	1
valid_sources[0x3b]	6631	1			T10	387		T12	802		T81	1
valid_sources[0x3c]	6168	1			T10	473		T17	1		T12	4
valid_sources[0x3d]	5207	1			T10	619		T12	182		T23	319
valid_sources[0x3e]	5403	1			T3	24		T10	454		T12	524
valid_sources[0x3f]	6186	1			T10	508		T12	4		T23	319
valid_sources[0x40]	5394	1			T10	385		T12	197		T60	1
valid_sources[0x41]	5334	1			T10	811		T12	94		T23	336
valid_sources[0x42]	6181	1			T10	847		T12	135		T23	305
valid_sources[0x43]	5098	1			T10	579		T12	84		T23	357
valid_sources[0x44]	5652	1			T5	1		T10	1036		T12	130
valid_sources[0x45]	5683	1			T10	438		T12	3		T23	324
valid_sources[0x46]	6502	1			T10	381		T12	506		T23	300
valid_sources[0x47]	5774	1			T10	526		T12	254		T23	351
valid_sources[0x48]	6123	1			T10	368		T12	146		T23	325
valid_sources[0x49]	6150	1			T10	356		T12	435		T71	1
valid_sources[0x4a]	6299	1			T10	371		T12	147		T55	1
valid_sources[0x4b]	6287	1			T10	347		T12	494		T23	301
valid_sources[0x4c]	6441	1			T10	989		T23	360		T56	41
valid_sources[0x4d]	6061	1			T10	752		T12	385		T23	335
valid_sources[0x4e]	6121	1			T10	1088		T12	239		T67	1
valid_sources[0x4f]	4487	1			T10	330		T69	2		T23	319
valid_sources[0x50]	6618	1			T10	1043		T12	580		T67	2
valid_sources[0x51]	4916	1			T4	1		T10	1115		T12	25
valid_sources[0x52]	5436	1			T10	273		T12	423		T23	328
valid_sources[0x53]	5104	1			T5	1		T10	557		T12	262
valid_sources[0x54]	5616	1			T10	344		T12	284		T23	346
valid_sources[0x55]	6319	1			T10	353		T12	698		T71	2
valid_sources[0x56]	6482	1			T10	827		T12	258		T38	1
valid_sources[0x57]	6427	1			T10	1081		T12	779		T23	295
valid_sources[0x58]	5894	1			T10	481		T12	658		T23	295
valid_sources[0x59]	7307	1			T10	967		T15	1		T12	501
valid_sources[0x5a]	5425	1			T10	593		T12	434		T23	352
valid_sources[0x5b]	5279	1			T10	518		T12	726		T38	3
valid_sources[0x5c]	6837	1			T10	1294		T12	427		T23	337
valid_sources[0x5d]	5319	1			T10	250		T12	169		T55	1
valid_sources[0x5e]	5968	1			T10	840		T12	2		T23	326
valid_sources[0x5f]	5457	1			T10	300		T12	5		T23	344
valid_sources[0x60]	5025	1			T10	645		T12	96		T23	323
valid_sources[0x61]	4797	1			T10	471		T12	229		T23	320
valid_sources[0x62]	5732	1			T10	607		T12	237		T23	310
valid_sources[0x63]	5496	1			T10	894		T12	1		T38	2
valid_sources[0x64]	5482	1			T10	595		T12	209		T81	21
valid_sources[0x65]	5426	1			T10	560		T12	2		T23	317
valid_sources[0x66]	5311	1			T10	749		T15	12		T69	1
valid_sources[0x67]	5864	1			T10	810		T12	6		T23	342
valid_sources[0x68]	5691	1			T10	280		T12	298		T18	26
valid_sources[0x69]	6077	1			T10	364		T12	691		T71	1
valid_sources[0x6a]	5653	1			T10	936		T12	136		T23	329
valid_sources[0x6b]	4810	1			T10	618		T12	120		T23	326
valid_sources[0x6c]	5865	1			T4	1		T10	936		T12	215
valid_sources[0x6d]	5300	1			T10	513		T12	120		T23	362
valid_sources[0x6e]	5471	1			T10	132		T12	280		T71	1
valid_sources[0x6f]	6387	1			T10	827		T12	282		T23	311
valid_sources[0x70]	4430	1			T10	434		T23	305		T56	66
valid_sources[0x71]	5498	1			T10	812		T12	135		T67	1
valid_sources[0x72]	6175	1			T10	1072		T12	6		T70	2
valid_sources[0x73]	5129	1			T5	1		T10	359		T12	204
valid_sources[0x74]	5655	1			T10	898		T23	323		T56	201
valid_sources[0x75]	6147	1			T10	935		T12	117		T23	327
valid_sources[0x76]	5311	1			T10	819		T23	293		T56	32
valid_sources[0x77]	5079	1			T10	497		T12	276		T23	362
valid_sources[0x78]	6536	1			T10	1046		T12	112		T71	4
valid_sources[0x79]	5829	1			T10	618		T12	5		T23	321
valid_sources[0x7a]	5635	1			T10	1012		T12	3		T67	1
valid_sources[0x7b]	4894	1			T10	463		T12	72		T23	270
valid_sources[0x7c]	6116	1			T10	410		T12	225		T67	1
valid_sources[0x7d]	5856	1			T10	944		T12	98		T23	333
valid_sources[0x7e]	5181	1			T10	537		T12	1		T71	2
valid_sources[0x7f]	5468	1			T10	436		T17	4		T23	348
valid_sources[0x80]	5199	1			T10	505		T12	4		T69	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

337982

1

T2

1

T3

15

T10

39786

values[0x0]

all_enables

biggest_size

504118

1

T4

2

T10

58615

T17

1

values[0x1]

all_enables

biggest_size

504595

1

T10

58725

T17

4

T12

15591