Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3247212

1

T6

88

T7

90

T8

202

full_word

2079908

1

T3

4

T6

7

T7

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5326830	1			T3	4		T6	95		T7	100
auto[TlIntgErrCmd]	88	1			T61	1		T62	5		T63	9
auto[TlIntgErrData]	93	1			T61	4		T62	4		T63	6
auto[TlIntgErrBoth]	109	1			T61	5		T62	11		T63	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

829176

1

T3

4

T6

95

T7

100

auto[1]

4497944

1

T10

531707

T12

128247

T23

261517

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	338849	1			T6	88		T7	90		T8	202
auto[TlIntgErrNone]	partial	auto[1]	2908094	1			T10	346251		T12	83356		T23	171344
auto[TlIntgErrNone]	full_word	auto[0]	490193	1			T3	4		T6	7		T7	10
auto[TlIntgErrNone]	full_word	auto[1]	1589694	1			T10	185456		T12	44891		T23	90173
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T62	3		T63	1		T119	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T61	1		T62	1		T63	8
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T62	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T125	1		T121	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T61	2		T62	1		T63	5
auto[TlIntgErrData]	partial	auto[1]	39	1			T61	2		T62	3		T63	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T120	2		T126	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T119	1		T120	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T61	3		T62	4		T63	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T61	2		T62	6		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T128	1		T120	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T62	1		T124	1		T127	1