Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1972743

1

T1

6

T2

9

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	514493	1			T1	69		T2	9		T3	3
values[0x0]	747165	1			T13	21332		T15	12354		T16	14258
values[0x1]	771649	1			T13	21797		T15	12709		T16	14779

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2000334

1

T1

36

T2

9

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7198	1			T13	241		T15	142		T70	1
valid_sources[0x01]	8473	1			T12	12		T13	251		T15	165
valid_sources[0x02]	7887	1			T13	196		T54	3		T15	115
valid_sources[0x03]	7734	1			T1	35		T13	248		T54	1
valid_sources[0x04]	7754	1			T13	279		T17	10		T54	2
valid_sources[0x05]	7054	1			T13	213		T15	117		T106	2
valid_sources[0x06]	7345	1			T13	233		T54	4		T15	137
valid_sources[0x07]	7743	1			T13	162		T15	127		T68	38
valid_sources[0x08]	9868	1			T13	235		T15	137		T16	206
valid_sources[0x09]	7873	1			T2	1		T13	205		T54	3
valid_sources[0x0a]	8363	1			T13	210		T15	135		T70	2
valid_sources[0x0b]	9266	1			T13	215		T54	4		T15	120
valid_sources[0x0c]	10107	1			T13	254		T15	137		T16	120
valid_sources[0x0d]	7544	1			T13	215		T54	1		T15	134
valid_sources[0x0e]	6860	1			T13	221		T54	1		T15	106
valid_sources[0x0f]	7480	1			T13	208		T15	144		T56	1
valid_sources[0x10]	7457	1			T12	2		T13	204		T15	123
valid_sources[0x11]	7651	1			T12	8		T13	210		T54	3
valid_sources[0x12]	7822	1			T13	242		T15	161		T106	5
valid_sources[0x13]	6660	1			T12	2		T13	213		T15	114
valid_sources[0x14]	9279	1			T13	261		T15	118		T56	1
valid_sources[0x15]	7795	1			T13	292		T20	1		T54	4
valid_sources[0x16]	9716	1			T13	157		T54	4		T15	119
valid_sources[0x17]	7111	1			T13	212		T15	146		T16	192
valid_sources[0x18]	7013	1			T13	215		T54	2		T15	114
valid_sources[0x19]	7060	1			T13	138		T55	48		T15	99
valid_sources[0x1a]	7223	1			T13	255		T54	1		T15	143
valid_sources[0x1b]	7534	1			T12	3		T13	308		T15	147
valid_sources[0x1c]	7234	1			T13	191		T15	145		T16	172
valid_sources[0x1d]	9096	1			T13	239		T54	1		T15	135
valid_sources[0x1e]	8001	1			T9	1		T13	238		T54	2
valid_sources[0x1f]	7173	1			T12	8		T13	288		T15	104
valid_sources[0x20]	7392	1			T13	226		T15	125		T106	3
valid_sources[0x21]	8438	1			T13	183		T15	111		T18	2
valid_sources[0x22]	6955	1			T13	223		T15	117		T19	1
valid_sources[0x23]	7343	1			T13	167		T54	3		T15	132
valid_sources[0x24]	8133	1			T13	216		T15	148		T70	3
valid_sources[0x25]	7843	1			T13	199		T15	105		T70	2
valid_sources[0x26]	7552	1			T9	3		T13	212		T54	2
valid_sources[0x27]	7624	1			T9	1		T13	225		T15	127
valid_sources[0x28]	7964	1			T13	205		T54	3		T15	123
valid_sources[0x29]	7123	1			T13	178		T15	126		T56	1
valid_sources[0x2a]	8041	1			T13	222		T15	112		T42	1
valid_sources[0x2b]	8751	1			T13	180		T15	128		T56	2
valid_sources[0x2c]	8059	1			T13	292		T15	150		T16	164
valid_sources[0x2d]	8040	1			T13	186		T15	124		T70	1
valid_sources[0x2e]	8149	1			T13	194		T20	1		T21	1
valid_sources[0x2f]	8010	1			T13	198		T15	126		T16	134
valid_sources[0x30]	8383	1			T13	252		T54	1		T15	131
valid_sources[0x31]	6363	1			T13	247		T15	146		T56	1
valid_sources[0x32]	7570	1			T9	1		T13	162		T54	3
valid_sources[0x33]	8730	1			T12	3		T13	208		T14	1
valid_sources[0x34]	6750	1			T13	272		T54	2		T15	159
valid_sources[0x35]	7182	1			T13	276		T15	137		T19	1
valid_sources[0x36]	8204	1			T9	1		T13	223		T54	2
valid_sources[0x37]	6933	1			T13	226		T54	1		T15	119
valid_sources[0x38]	7720	1			T13	241		T15	125		T81	1
valid_sources[0x39]	8910	1			T13	188		T15	142		T56	1
valid_sources[0x3a]	7465	1			T13	191		T54	1		T15	119
valid_sources[0x3b]	8187	1			T13	251		T15	119		T70	6
valid_sources[0x3c]	7089	1			T13	152		T15	146		T16	112
valid_sources[0x3d]	8693	1			T13	266		T15	110		T81	1
valid_sources[0x3e]	6906	1			T13	244		T15	178		T16	166
valid_sources[0x3f]	6662	1			T13	234		T54	1		T15	133
valid_sources[0x40]	6897	1			T13	245		T54	1		T15	127
valid_sources[0x41]	7628	1			T2	2		T13	217		T54	3
valid_sources[0x42]	8223	1			T13	192		T54	1		T15	116
valid_sources[0x43]	7199	1			T13	310		T54	1		T15	115
valid_sources[0x44]	9175	1			T13	226		T54	4		T15	130
valid_sources[0x45]	8292	1			T13	202		T54	1		T15	122
valid_sources[0x46]	7507	1			T13	222		T54	3		T15	138
valid_sources[0x47]	7493	1			T13	238		T15	123		T106	3
valid_sources[0x48]	7773	1			T13	224		T15	110		T70	2
valid_sources[0x49]	8439	1			T13	206		T54	2		T15	125
valid_sources[0x4a]	8311	1			T13	229		T54	2		T15	154
valid_sources[0x4b]	8960	1			T12	16		T13	159		T54	1
valid_sources[0x4c]	7474	1			T13	259		T15	132		T56	1
valid_sources[0x4d]	8211	1			T13	276		T54	2		T15	121
valid_sources[0x4e]	10734	1			T12	18		T13	296		T54	1
valid_sources[0x4f]	10100	1			T12	16		T13	219		T54	8
valid_sources[0x50]	8719	1			T13	280		T54	1		T15	171
valid_sources[0x51]	8954	1			T13	212		T14	2		T54	1
valid_sources[0x52]	8567	1			T13	234		T54	1		T15	147
valid_sources[0x53]	7370	1			T12	18		T13	213		T54	1
valid_sources[0x54]	7485	1			T13	175		T54	5		T15	122
valid_sources[0x55]	7424	1			T13	170		T15	141		T70	1
valid_sources[0x56]	9525	1			T12	8		T13	196		T15	131
valid_sources[0x57]	6834	1			T13	300		T20	1		T15	123
valid_sources[0x58]	9716	1			T13	148		T15	138		T16	172
valid_sources[0x59]	6272	1			T13	228		T15	132		T106	1
valid_sources[0x5a]	7702	1			T13	237		T54	5		T15	118
valid_sources[0x5b]	7051	1			T1	12		T13	260		T15	116
valid_sources[0x5c]	6425	1			T13	153		T15	136		T16	99
valid_sources[0x5d]	9527	1			T13	244		T15	134		T70	2
valid_sources[0x5e]	7701	1			T13	237		T15	133		T70	2
valid_sources[0x5f]	8544	1			T13	246		T54	2		T15	146
valid_sources[0x60]	8006	1			T13	241		T15	146		T19	1
valid_sources[0x61]	7974	1			T13	224		T54	2		T15	134
valid_sources[0x62]	7117	1			T13	228		T15	149		T18	1
valid_sources[0x63]	8359	1			T12	13		T13	243		T54	1
valid_sources[0x64]	6943	1			T13	235		T15	145		T16	104
valid_sources[0x65]	6778	1			T13	176		T15	126		T81	2
valid_sources[0x66]	7571	1			T13	219		T54	1		T15	139
valid_sources[0x67]	8836	1			T12	19		T13	187		T54	1
valid_sources[0x68]	8486	1			T9	1		T13	248		T15	131
valid_sources[0x69]	7011	1			T13	243		T54	1		T15	137
valid_sources[0x6a]	7625	1			T13	183		T15	142		T70	4
valid_sources[0x6b]	7949	1			T13	271		T54	1		T15	123
valid_sources[0x6c]	7800	1			T13	160		T15	128		T16	149
valid_sources[0x6d]	8239	1			T13	253		T15	129		T56	1
valid_sources[0x6e]	7766	1			T13	237		T15	119		T81	2
valid_sources[0x6f]	7745	1			T13	242		T54	1		T15	118
valid_sources[0x70]	7864	1			T12	6		T13	170		T54	3
valid_sources[0x71]	9202	1			T13	210		T15	116		T42	1
valid_sources[0x72]	7103	1			T13	248		T54	1		T15	143
valid_sources[0x73]	9164	1			T13	282		T54	2		T15	112
valid_sources[0x74]	8150	1			T13	220		T54	2		T15	153
valid_sources[0x75]	7513	1			T13	309		T54	5		T15	124
valid_sources[0x76]	7958	1			T3	3		T13	191		T17	19
valid_sources[0x77]	7517	1			T13	241		T15	155		T56	1
valid_sources[0x78]	8741	1			T13	193		T54	1		T15	133
valid_sources[0x79]	7650	1			T13	189		T54	1		T15	122
valid_sources[0x7a]	9208	1			T13	210		T15	140		T70	1
valid_sources[0x7b]	9518	1			T2	1		T13	262		T54	2
valid_sources[0x7c]	8552	1			T13	186		T15	135		T16	148
valid_sources[0x7d]	8676	1			T13	223		T54	2		T15	114
valid_sources[0x7e]	7090	1			T9	1		T13	245		T54	1
valid_sources[0x7f]	7276	1			T13	173		T15	148		T70	2
valid_sources[0x80]	8280	1			T13	220		T15	154		T70	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

493742

1

T1

6

T2

9

T3

3

values[0x0]

all_enables

biggest_size

740673

1

T13

21120

T15

12254

T16

14136

values[0x1]

all_enables

biggest_size

738328

1

T13

20791

T15

12146

T16

14137

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144398	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1476729

1

T1

21

T2

10

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	397766	1			T1	32		T2	16		T3	16
values[0x0]	565335	1			T10	2		T27	1		T13	16276
values[0x1]	658026	1			T10	9		T27	3		T13	18751

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1558390

1

T1

23

T2

12

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6161	1			T13	117		T15	101		T106	2
valid_sources[0x01]	6202	1			T13	122		T14	3		T55	1
valid_sources[0x02]	7087	1			T13	329		T15	105		T41	1
valid_sources[0x03]	6146	1			T2	8		T13	84		T15	109
valid_sources[0x04]	6962	1			T13	184		T20	1		T15	78
valid_sources[0x05]	6541	1			T2	1		T9	1		T13	342
valid_sources[0x06]	6059	1			T9	1		T13	206		T15	109
valid_sources[0x07]	6103	1			T2	2		T13	97		T15	141
valid_sources[0x08]	6444	1			T13	335		T15	49		T42	35
valid_sources[0x09]	5539	1			T13	199		T15	67		T68	1
valid_sources[0x0a]	6208	1			T13	219		T15	73		T16	121
valid_sources[0x0b]	6252	1			T13	208		T55	1		T15	59
valid_sources[0x0c]	6557	1			T13	98		T15	85		T16	98
valid_sources[0x0d]	7105	1			T13	152		T15	56		T41	1
valid_sources[0x0e]	6021	1			T13	263		T15	72		T16	86
valid_sources[0x0f]	6371	1			T27	3		T13	21		T15	182
valid_sources[0x10]	6197	1			T13	104		T15	114		T43	1
valid_sources[0x11]	5774	1			T13	154		T21	1		T15	109
valid_sources[0x12]	6116	1			T3	1		T13	86		T15	103
valid_sources[0x13]	6512	1			T11	6		T13	142		T15	75
valid_sources[0x14]	6040	1			T13	124		T15	103		T16	94
valid_sources[0x15]	5972	1			T13	191		T15	58		T16	106
valid_sources[0x16]	6075	1			T11	1		T13	254		T15	87
valid_sources[0x17]	6304	1			T13	113		T15	64		T16	104
valid_sources[0x18]	6101	1			T13	431		T55	1		T15	50
valid_sources[0x19]	6112	1			T13	277		T55	1		T15	185
valid_sources[0x1a]	6412	1			T13	181		T15	117		T16	123
valid_sources[0x1b]	6822	1			T13	217		T15	81		T16	105
valid_sources[0x1c]	6142	1			T13	130		T20	1		T15	111
valid_sources[0x1d]	5941	1			T13	200		T20	2		T21	1
valid_sources[0x1e]	6310	1			T13	79		T15	55		T16	133
valid_sources[0x1f]	5999	1			T13	325		T21	1		T15	136
valid_sources[0x20]	6536	1			T3	1		T13	196		T15	64
valid_sources[0x21]	6095	1			T13	110		T15	98		T125	1
valid_sources[0x22]	6394	1			T11	3		T13	322		T15	68
valid_sources[0x23]	5731	1			T13	229		T15	70		T22	34
valid_sources[0x24]	5800	1			T11	2		T13	308		T15	91
valid_sources[0x25]	6025	1			T13	199		T20	1		T15	101
valid_sources[0x26]	6317	1			T13	256		T15	104		T68	3
valid_sources[0x27]	6439	1			T13	101		T15	115		T41	1
valid_sources[0x28]	5882	1			T13	188		T15	125		T68	1
valid_sources[0x29]	6874	1			T13	371		T15	153		T16	150
valid_sources[0x2a]	5816	1			T3	1		T13	456		T15	133
valid_sources[0x2b]	6758	1			T9	1		T13	173		T15	86
valid_sources[0x2c]	6738	1			T13	234		T55	1		T15	64
valid_sources[0x2d]	7020	1			T13	182		T15	87		T16	132
valid_sources[0x2e]	6127	1			T13	88		T15	87		T16	134
valid_sources[0x2f]	6394	1			T13	223		T55	1		T15	83
valid_sources[0x30]	5870	1			T13	71		T15	170		T69	1
valid_sources[0x31]	6501	1			T9	1		T13	532		T15	104
valid_sources[0x32]	6216	1			T11	1		T13	34		T55	1
valid_sources[0x33]	6522	1			T13	191		T15	107		T41	1
valid_sources[0x34]	5654	1			T9	1		T13	196		T55	1
valid_sources[0x35]	6499	1			T11	2		T13	145		T15	105
valid_sources[0x36]	6502	1			T13	247		T20	2		T15	116
valid_sources[0x37]	6182	1			T13	226		T15	110		T16	127
valid_sources[0x38]	6255	1			T13	162		T15	115		T16	148
valid_sources[0x39]	6578	1			T3	1		T13	52		T15	72
valid_sources[0x3a]	6124	1			T13	228		T15	92		T43	1
valid_sources[0x3b]	6503	1			T13	203		T15	118		T68	1
valid_sources[0x3c]	6085	1			T13	155		T15	59		T16	120
valid_sources[0x3d]	6467	1			T13	330		T15	141		T16	97
valid_sources[0x3e]	5848	1			T13	164		T55	1		T15	120
valid_sources[0x3f]	6295	1			T9	1		T13	225		T20	1
valid_sources[0x40]	5993	1			T13	181		T15	152		T19	1
valid_sources[0x41]	5909	1			T13	231		T15	45		T41	1
valid_sources[0x42]	6268	1			T13	192		T15	84		T68	1
valid_sources[0x43]	7050	1			T13	219		T15	122		T16	118
valid_sources[0x44]	6889	1			T3	1		T13	97		T15	159
valid_sources[0x45]	6386	1			T13	207		T15	65		T16	137
valid_sources[0x46]	6804	1			T13	165		T15	94		T68	1
valid_sources[0x47]	6432	1			T13	259		T15	72		T16	112
valid_sources[0x48]	6633	1			T8	1		T13	176		T55	1
valid_sources[0x49]	6452	1			T13	173		T17	64		T55	1
valid_sources[0x4a]	6928	1			T3	1		T9	1		T13	260
valid_sources[0x4b]	5445	1			T13	87		T15	122		T106	1
valid_sources[0x4c]	6820	1			T13	330		T15	51		T16	112
valid_sources[0x4d]	6050	1			T9	2		T13	158		T15	57
valid_sources[0x4e]	5677	1			T13	37		T15	57		T68	1
valid_sources[0x4f]	6534	1			T13	299		T15	132		T16	132
valid_sources[0x50]	7409	1			T13	101		T15	77		T16	128
valid_sources[0x51]	6307	1			T13	95		T15	62		T16	95
valid_sources[0x52]	6274	1			T13	347		T15	144		T16	119
valid_sources[0x53]	5743	1			T13	107		T21	1		T15	64
valid_sources[0x54]	6774	1			T27	1		T13	211		T15	74
valid_sources[0x55]	6653	1			T13	160		T15	73		T16	148
valid_sources[0x56]	6443	1			T13	113		T15	67		T16	120
valid_sources[0x57]	7051	1			T13	206		T55	1		T15	109
valid_sources[0x58]	6986	1			T13	336		T55	1		T15	111
valid_sources[0x59]	6301	1			T13	163		T15	79		T19	1
valid_sources[0x5a]	6343	1			T13	235		T15	44		T16	109
valid_sources[0x5b]	5595	1			T13	263		T20	1		T15	51
valid_sources[0x5c]	6487	1			T13	98		T15	137		T16	83
valid_sources[0x5d]	5849	1			T13	100		T15	123		T16	120
valid_sources[0x5e]	6237	1			T11	2		T13	175		T15	93
valid_sources[0x5f]	6293	1			T3	1		T13	81		T15	84
valid_sources[0x60]	5382	1			T13	60		T15	82		T16	107
valid_sources[0x61]	6044	1			T13	229		T20	1		T15	170
valid_sources[0x62]	6592	1			T13	256		T15	76		T106	3
valid_sources[0x63]	5948	1			T10	1		T13	78		T55	1
valid_sources[0x64]	6667	1			T11	7		T13	220		T15	107
valid_sources[0x65]	6161	1			T13	80		T20	2		T15	107
valid_sources[0x66]	6616	1			T13	182		T15	96		T29	3
valid_sources[0x67]	6427	1			T13	214		T15	144		T41	1
valid_sources[0x68]	6122	1			T9	1		T13	86		T20	2
valid_sources[0x69]	6117	1			T13	65		T15	141		T16	129
valid_sources[0x6a]	6096	1			T13	73		T55	1		T15	111
valid_sources[0x6b]	6283	1			T9	2		T13	227		T15	129
valid_sources[0x6c]	5854	1			T13	202		T15	50		T68	2
valid_sources[0x6d]	5736	1			T13	40		T15	105		T106	2
valid_sources[0x6e]	6545	1			T13	112		T15	109		T46	19
valid_sources[0x6f]	6661	1			T9	1		T13	304		T21	1
valid_sources[0x70]	5508	1			T13	38		T20	1		T15	75
valid_sources[0x71]	6691	1			T10	1		T13	172		T15	133
valid_sources[0x72]	6278	1			T13	144		T15	79		T16	111
valid_sources[0x73]	6319	1			T13	178		T15	109		T16	101
valid_sources[0x74]	6128	1			T13	174		T55	1		T15	79
valid_sources[0x75]	5848	1			T13	81		T15	101		T16	103
valid_sources[0x76]	6356	1			T13	177		T15	101		T68	1
valid_sources[0x77]	5991	1			T13	329		T15	137		T19	1
valid_sources[0x78]	5975	1			T9	1		T13	205		T21	1
valid_sources[0x79]	6437	1			T13	129		T15	111		T68	2
valid_sources[0x7a]	7075	1			T13	201		T15	145		T16	81
valid_sources[0x7b]	5914	1			T3	1		T13	90		T55	1
valid_sources[0x7c]	6310	1			T10	1		T13	63		T15	162
valid_sources[0x7d]	5899	1			T13	241		T15	112		T16	152
valid_sources[0x7e]	6165	1			T13	159		T55	1		T15	110
valid_sources[0x7f]	6059	1			T13	358		T15	105		T68	1
valid_sources[0x80]	5977	1			T13	60		T15	79		T68	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

369790

1

T1

21

T2

10

T3

7

values[0x0]

all_enables

biggest_size

553449

1

T10

1

T27

1

T13

15948

values[0x1]

all_enables

biggest_size

553490

1

T10

1

T13

15822

T15

8773