Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3546820

1

T1

63

T12

227

T13

102093

full_word

2299458

1

T1

6

T2

6

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5845938	1			T1	69		T2	6		T3	2
auto[TlIntgErrCmd]	109	1			T57	5		T58	4		T59	4
auto[TlIntgErrData]	124	1			T57	5		T58	10		T59	2
auto[TlIntgErrBoth]	107	1			T57	10		T58	6		T59	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

913578

1

T1

69

T2

6

T3

2

auto[1]

4932700

1

T13

141769

T15

80621

T16

95501

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	372317	1			T1	63		T12	227		T13	10324
auto[TlIntgErrNone]	partial	auto[1]	3174198	1			T13	91769		T15	51625		T16	61786
auto[TlIntgErrNone]	full_word	auto[0]	541101	1			T1	6		T2	6		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	1758322	1			T13	50000		T15	28996		T16	33715
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T57	2		T59	1		T112	4
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T57	3		T58	4		T59	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T112	1		T117	2		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T59	1		T111	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T57	2		T58	2		T59	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T57	2		T58	8		T111	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T57	1		T111	1		T112	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T119	1		T120	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T57	3		T58	1		T59	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T57	5		T58	5		T59	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T57	2		T119	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T111	1		-	-		-	-