Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

364193

1

T2

6

T3

19

T4

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	124160	1			T2	74		T3	234		T4	199
values[0x0]	136268	1			T9	1283		T13	4316		T14	2130
values[0x1]	142026	1			T9	1335		T13	4527		T14	2129

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18019	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

384435

1

T2

43

T3

136

T4

108

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1462	1			T2	5		T3	1		T4	1
valid_sources[0x01]	1484	1			T9	9		T13	2		T14	20
valid_sources[0x02]	2634	1			T3	1		T9	18		T13	1218
valid_sources[0x03]	1668	1			T3	1		T4	1		T9	21
valid_sources[0x04]	1408	1			T3	1		T4	3		T9	13
valid_sources[0x05]	1492	1			T4	2		T8	1		T9	15
valid_sources[0x06]	1529	1			T4	1		T9	8		T14	36
valid_sources[0x07]	1651	1			T3	1		T9	23		T13	93
valid_sources[0x08]	1637	1			T4	1		T9	5		T14	21
valid_sources[0x09]	1933	1			T9	31		T14	23		T45	33
valid_sources[0x0a]	1744	1			T3	3		T4	1		T9	13
valid_sources[0x0b]	1438	1			T9	9		T13	10		T14	38
valid_sources[0x0c]	1749	1			T3	4		T4	1		T9	17
valid_sources[0x0d]	2159	1			T8	1		T9	23		T14	13
valid_sources[0x0e]	1899	1			T4	2		T8	2		T9	12
valid_sources[0x0f]	1408	1			T3	1		T4	1		T9	17
valid_sources[0x10]	1447	1			T3	1		T9	23		T13	39
valid_sources[0x11]	1568	1			T2	2		T3	1		T8	1
valid_sources[0x12]	1524	1			T4	1		T9	22		T13	18
valid_sources[0x13]	1554	1			T3	3		T4	1		T9	15
valid_sources[0x14]	1365	1			T3	2		T4	1		T9	23
valid_sources[0x15]	1396	1			T9	12		T14	30		T45	26
valid_sources[0x16]	1419	1			T3	1		T7	5		T9	12
valid_sources[0x17]	1936	1			T2	3		T3	1		T4	1
valid_sources[0x18]	1435	1			T4	1		T9	8		T14	30
valid_sources[0x19]	1481	1			T9	14		T14	30		T45	56
valid_sources[0x1a]	1415	1			T3	1		T9	6		T14	27
valid_sources[0x1b]	1765	1			T9	25		T14	20		T45	52
valid_sources[0x1c]	1813	1			T3	1		T9	4		T13	118
valid_sources[0x1d]	1474	1			T6	40		T8	1		T9	19
valid_sources[0x1e]	1549	1			T9	10		T14	17		T45	47
valid_sources[0x1f]	1602	1			T3	1		T4	1		T9	25
valid_sources[0x20]	1657	1			T9	14		T14	23		T45	45
valid_sources[0x21]	1379	1			T8	1		T9	15		T14	34
valid_sources[0x22]	1250	1			T3	2		T9	6		T14	24
valid_sources[0x23]	1365	1			T3	1		T4	1		T9	11
valid_sources[0x24]	1361	1			T8	1		T9	5		T14	24
valid_sources[0x25]	1328	1			T4	1		T9	9		T14	29
valid_sources[0x26]	1415	1			T9	13		T14	25		T45	49
valid_sources[0x27]	1523	1			T2	8		T9	18		T13	1
valid_sources[0x28]	1469	1			T3	1		T9	19		T13	6
valid_sources[0x29]	1345	1			T4	1		T9	13		T14	32
valid_sources[0x2a]	1847	1			T9	31		T14	12		T45	28
valid_sources[0x2b]	1924	1			T3	1		T4	2		T9	8
valid_sources[0x2c]	1425	1			T9	15		T14	20		T45	38
valid_sources[0x2d]	1877	1			T3	3		T9	16		T13	344
valid_sources[0x2e]	1624	1			T3	1		T4	3		T9	12
valid_sources[0x2f]	1501	1			T3	3		T9	15		T14	15
valid_sources[0x30]	1486	1			T3	3		T9	7		T13	4
valid_sources[0x31]	1710	1			T3	2		T4	1		T9	16
valid_sources[0x32]	1423	1			T3	2		T4	2		T9	1
valid_sources[0x33]	2555	1			T3	1		T4	1		T9	13
valid_sources[0x34]	1460	1			T3	1		T4	4		T9	19
valid_sources[0x35]	1427	1			T4	2		T9	6		T13	3
valid_sources[0x36]	1681	1			T4	2		T9	19		T14	66
valid_sources[0x37]	1385	1			T9	14		T14	18		T45	39
valid_sources[0x38]	1571	1			T9	26		T13	120		T14	19
valid_sources[0x39]	1311	1			T4	1		T9	25		T13	5
valid_sources[0x3a]	1433	1			T9	16		T14	16		T45	37
valid_sources[0x3b]	2159	1			T3	1		T4	2		T9	14
valid_sources[0x3c]	2673	1			T3	3		T9	14		T14	19
valid_sources[0x3d]	1442	1			T3	1		T4	3		T9	13
valid_sources[0x3e]	1516	1			T3	2		T9	28		T13	3
valid_sources[0x3f]	1537	1			T3	1		T9	11		T13	136
valid_sources[0x40]	1430	1			T3	1		T9	8		T14	21
valid_sources[0x41]	1412	1			T4	1		T9	4		T14	12
valid_sources[0x42]	1743	1			T3	2		T9	14		T13	210
valid_sources[0x43]	1360	1			T3	1		T9	27		T13	2
valid_sources[0x44]	1346	1			T4	1		T9	2		T14	24
valid_sources[0x45]	1757	1			T3	1		T9	2		T13	191
valid_sources[0x46]	1326	1			T4	2		T9	12		T14	26
valid_sources[0x47]	1495	1			T9	13		T14	20		T45	39
valid_sources[0x48]	1552	1			T3	1		T4	1		T9	16
valid_sources[0x49]	1309	1			T9	15		T14	21		T45	38
valid_sources[0x4a]	1607	1			T4	2		T9	5		T13	208
valid_sources[0x4b]	1626	1			T3	2		T4	1		T9	25
valid_sources[0x4c]	1826	1			T3	1		T4	2		T7	7
valid_sources[0x4d]	1438	1			T4	3		T9	15		T14	16
valid_sources[0x4e]	1470	1			T3	3		T4	1		T9	13
valid_sources[0x4f]	1508	1			T3	3		T4	1		T6	12
valid_sources[0x50]	1471	1			T2	3		T3	1		T9	14
valid_sources[0x51]	1527	1			T2	1		T3	1		T4	1
valid_sources[0x52]	1411	1			T9	9		T13	13		T14	25
valid_sources[0x53]	1573	1			T3	2		T9	25		T13	124
valid_sources[0x54]	1313	1			T4	1		T9	6		T13	3
valid_sources[0x55]	1455	1			T2	10		T3	1		T6	36
valid_sources[0x56]	2032	1			T3	1		T4	1		T6	59
valid_sources[0x57]	1352	1			T4	2		T9	10		T14	17
valid_sources[0x58]	1384	1			T4	3		T9	11		T14	31
valid_sources[0x59]	1845	1			T9	3		T13	47		T14	15
valid_sources[0x5a]	1280	1			T3	2		T4	1		T7	7
valid_sources[0x5b]	1589	1			T2	4		T9	17		T13	153
valid_sources[0x5c]	1641	1			T3	1		T4	1		T9	14
valid_sources[0x5d]	1611	1			T3	2		T4	1		T9	18
valid_sources[0x5e]	1335	1			T3	3		T8	1		T9	31
valid_sources[0x5f]	1577	1			T3	2		T9	17		T14	15
valid_sources[0x60]	1497	1			T9	18		T14	21		T45	48
valid_sources[0x61]	1477	1			T2	8		T9	23		T14	13
valid_sources[0x62]	1379	1			T2	1		T3	3		T9	3
valid_sources[0x63]	1458	1			T9	28		T13	2		T14	17
valid_sources[0x64]	1700	1			T9	27		T14	24		T45	45
valid_sources[0x65]	2112	1			T3	2		T9	13		T13	744
valid_sources[0x66]	1891	1			T4	2		T9	10		T14	21
valid_sources[0x67]	1319	1			T3	2		T4	1		T9	20
valid_sources[0x68]	1749	1			T2	3		T4	1		T9	19
valid_sources[0x69]	1547	1			T3	1		T9	11		T13	2
valid_sources[0x6a]	1583	1			T3	1		T4	1		T9	14
valid_sources[0x6b]	1892	1			T4	1		T9	9		T14	15
valid_sources[0x6c]	1351	1			T3	1		T9	14		T13	24
valid_sources[0x6d]	1386	1			T3	1		T9	12		T13	5
valid_sources[0x6e]	1838	1			T9	2		T14	16		T38	1
valid_sources[0x6f]	2204	1			T9	16		T14	14		T45	31
valid_sources[0x70]	1703	1			T9	10		T14	29		T45	39
valid_sources[0x71]	1405	1			T3	2		T9	11		T13	5
valid_sources[0x72]	1272	1			T9	16		T14	21		T45	59
valid_sources[0x73]	2306	1			T3	2		T4	1		T9	22
valid_sources[0x74]	1757	1			T9	27		T14	22		T45	56
valid_sources[0x75]	1957	1			T9	8		T13	401		T14	19
valid_sources[0x76]	1548	1			T3	1		T4	1		T9	19
valid_sources[0x77]	1524	1			T4	1		T9	4		T14	14
valid_sources[0x78]	1383	1			T3	1		T9	4		T14	24
valid_sources[0x79]	1674	1			T3	1		T9	8		T13	7
valid_sources[0x7a]	1403	1			T9	15		T14	31		T45	41
valid_sources[0x7b]	2109	1			T9	16		T14	30		T45	42
valid_sources[0x7c]	1335	1			T3	2		T4	1		T9	10
valid_sources[0x7d]	1521	1			T3	1		T4	1		T9	16
valid_sources[0x7e]	1512	1			T9	9		T14	32		T45	33
valid_sources[0x7f]	1458	1			T3	2		T4	1		T9	17
valid_sources[0x80]	1349	1			T3	1		T4	2		T9	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93700

1

T2

6

T3

19

T4

14

values[0x0]

all_enables

biggest_size

134990

1

T9

1269

T13

4280

T14

2112

values[0x1]

all_enables

biggest_size

135503

1

T9

1267

T13

4342

T14

2019

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35959	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

312658

1

T1

5

T5

2

T7

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93285	1			T7	16		T8	16		T9	788
values[0x0]	118936	1			T1	12		T5	6		T9	983
values[0x1]	136396	1			T1	7		T5	3		T9	1142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

330002

1

T1

6

T5

2

T7

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1601	1			T9	2		T16	1		T13	32
valid_sources[0x01]	1480	1			T13	42		T14	5		T45	3
valid_sources[0x02]	1518	1			T13	43		T14	4		T20	1
valid_sources[0x03]	1201	1			T1	1		T13	38		T45	21
valid_sources[0x04]	1588	1			T9	2		T13	37		T14	1
valid_sources[0x05]	1387	1			T5	1		T9	1		T13	51
valid_sources[0x06]	1252	1			T13	48		T14	10		T45	89
valid_sources[0x07]	1052	1			T9	1		T13	46		T14	1
valid_sources[0x08]	1131	1			T8	1		T9	1		T13	44
valid_sources[0x09]	1747	1			T10	1		T13	56		T14	2
valid_sources[0x0a]	1078	1			T9	1		T13	52		T38	1
valid_sources[0x0b]	1796	1			T9	3		T13	56		T20	1
valid_sources[0x0c]	1359	1			T13	33		T14	3		T45	85
valid_sources[0x0d]	948	1			T13	44		T14	1		T45	57
valid_sources[0x0e]	1108	1			T9	2		T13	52		T38	3
valid_sources[0x0f]	1680	1			T9	20		T13	43		T14	142
valid_sources[0x10]	1281	1			T9	1		T13	41		T14	1
valid_sources[0x11]	1437	1			T9	2		T13	34		T14	1
valid_sources[0x12]	1204	1			T8	1		T9	1		T15	2
valid_sources[0x13]	1197	1			T9	4		T13	45		T45	100
valid_sources[0x14]	1341	1			T8	1		T9	20		T13	51
valid_sources[0x15]	1355	1			T9	3		T13	41		T14	4
valid_sources[0x16]	1089	1			T9	29		T13	44		T14	6
valid_sources[0x17]	1145	1			T13	45		T14	96		T45	64
valid_sources[0x18]	1209	1			T9	8		T13	32		T14	2
valid_sources[0x19]	1215	1			T13	34		T14	1		T45	6
valid_sources[0x1a]	990	1			T13	52		T14	1		T45	11
valid_sources[0x1b]	1281	1			T13	31		T45	64		T11	36
valid_sources[0x1c]	1072	1			T8	1		T13	43		T14	2
valid_sources[0x1d]	1182	1			T13	34		T14	2		T45	61
valid_sources[0x1e]	1091	1			T9	2		T13	53		T14	11
valid_sources[0x1f]	1003	1			T9	1		T13	47		T45	34
valid_sources[0x20]	1337	1			T13	47		T45	16		T11	28
valid_sources[0x21]	1171	1			T9	1		T13	49		T14	1
valid_sources[0x22]	1434	1			T5	1		T13	39		T45	50
valid_sources[0x23]	1565	1			T1	1		T9	87		T13	44
valid_sources[0x24]	1073	1			T9	1		T10	1		T13	42
valid_sources[0x25]	1575	1			T13	50		T45	100		T11	39
valid_sources[0x26]	1233	1			T9	36		T13	45		T14	1
valid_sources[0x27]	1000	1			T9	1		T13	35		T14	5
valid_sources[0x28]	1484	1			T9	20		T13	42		T14	149
valid_sources[0x29]	1125	1			T9	3		T13	32		T14	5
valid_sources[0x2a]	1292	1			T9	1		T13	48		T14	7
valid_sources[0x2b]	1478	1			T8	1		T13	34		T45	112
valid_sources[0x2c]	1244	1			T7	16		T13	40		T14	64
valid_sources[0x2d]	2005	1			T13	45		T14	1		T45	79
valid_sources[0x2e]	1153	1			T13	43		T14	1		T45	9
valid_sources[0x2f]	1093	1			T13	58		T14	8		T45	62
valid_sources[0x30]	1103	1			T13	53		T14	57		T38	1
valid_sources[0x31]	1539	1			T9	3		T13	30		T14	2
valid_sources[0x32]	1306	1			T9	79		T13	52		T14	1
valid_sources[0x33]	1024	1			T13	38		T45	46		T11	36
valid_sources[0x34]	1264	1			T9	4		T13	47		T14	1
valid_sources[0x35]	1347	1			T9	58		T13	39		T45	24
valid_sources[0x36]	1154	1			T13	27		T14	1		T45	31
valid_sources[0x37]	1334	1			T1	2		T13	55		T14	2
valid_sources[0x38]	1492	1			T9	1		T13	37		T14	2
valid_sources[0x39]	1394	1			T13	39		T20	1		T45	20
valid_sources[0x3a]	1379	1			T1	1		T9	1		T13	37
valid_sources[0x3b]	1205	1			T9	117		T13	34		T14	1
valid_sources[0x3c]	1188	1			T9	2		T13	45		T14	9
valid_sources[0x3d]	1658	1			T8	1		T9	18		T13	37
valid_sources[0x3e]	1105	1			T9	1		T13	48		T45	51
valid_sources[0x3f]	1376	1			T9	2		T13	50		T14	16
valid_sources[0x40]	1741	1			T13	39		T14	129		T45	46
valid_sources[0x41]	1379	1			T13	36		T14	188		T45	29
valid_sources[0x42]	1536	1			T9	173		T13	36		T14	2
valid_sources[0x43]	1477	1			T13	39		T45	76		T11	30
valid_sources[0x44]	1510	1			T9	2		T13	42		T14	6
valid_sources[0x45]	1464	1			T9	232		T13	41		T14	1
valid_sources[0x46]	1358	1			T9	9		T13	37		T14	1
valid_sources[0x47]	1139	1			T9	2		T13	42		T38	1
valid_sources[0x48]	1799	1			T9	129		T13	44		T45	68
valid_sources[0x49]	1482	1			T13	44		T14	54		T20	2
valid_sources[0x4a]	1329	1			T9	4		T13	40		T14	6
valid_sources[0x4b]	955	1			T13	34		T45	49		T11	32
valid_sources[0x4c]	1167	1			T9	2		T13	43		T14	4
valid_sources[0x4d]	931	1			T15	2		T13	44		T14	13
valid_sources[0x4e]	1509	1			T13	47		T14	4		T45	7
valid_sources[0x4f]	1265	1			T9	3		T13	40		T45	14
valid_sources[0x50]	1047	1			T9	1		T13	32		T38	2
valid_sources[0x51]	1292	1			T9	44		T13	45		T45	16
valid_sources[0x52]	1615	1			T9	1		T13	47		T14	1
valid_sources[0x53]	1434	1			T9	2		T13	41		T45	36
valid_sources[0x54]	1509	1			T9	174		T10	1		T13	43
valid_sources[0x55]	1333	1			T1	1		T9	17		T13	40
valid_sources[0x56]	1872	1			T9	91		T13	56		T14	3
valid_sources[0x57]	1197	1			T13	54		T45	5		T11	22
valid_sources[0x58]	1641	1			T13	43		T45	71		T11	25
valid_sources[0x59]	1482	1			T9	2		T15	4		T13	42
valid_sources[0x5a]	1139	1			T5	1		T13	42		T45	35
valid_sources[0x5b]	1374	1			T13	46		T14	3		T45	65
valid_sources[0x5c]	1493	1			T9	1		T13	42		T14	32
valid_sources[0x5d]	1387	1			T9	4		T13	47		T14	9
valid_sources[0x5e]	1238	1			T9	2		T13	43		T45	75
valid_sources[0x5f]	1477	1			T8	1		T9	1		T13	52
valid_sources[0x60]	970	1			T1	1		T8	1		T13	52
valid_sources[0x61]	1432	1			T13	29		T20	1		T45	115
valid_sources[0x62]	1737	1			T9	2		T13	32		T45	24
valid_sources[0x63]	1489	1			T9	2		T13	41		T14	8
valid_sources[0x64]	1152	1			T9	3		T13	51		T45	58
valid_sources[0x65]	1776	1			T9	1		T13	38		T45	47
valid_sources[0x66]	1723	1			T8	1		T9	44		T13	42
valid_sources[0x67]	1235	1			T9	4		T13	41		T14	94
valid_sources[0x68]	1408	1			T13	44		T14	173		T20	1
valid_sources[0x69]	1244	1			T9	2		T13	30		T14	1
valid_sources[0x6a]	1730	1			T13	38		T14	196		T45	49
valid_sources[0x6b]	1612	1			T13	41		T45	53		T11	47
valid_sources[0x6c]	1267	1			T13	48		T14	21		T45	29
valid_sources[0x6d]	1164	1			T9	1		T13	59		T14	1
valid_sources[0x6e]	1354	1			T9	1		T15	1		T13	44
valid_sources[0x6f]	2312	1			T13	52		T45	56		T11	33
valid_sources[0x70]	1369	1			T9	1		T13	42		T20	2
valid_sources[0x71]	1090	1			T9	24		T13	45		T14	4
valid_sources[0x72]	1773	1			T9	1		T13	44		T14	1
valid_sources[0x73]	1392	1			T13	42		T14	18		T45	7
valid_sources[0x74]	1412	1			T9	1		T13	43		T45	66
valid_sources[0x75]	1610	1			T9	3		T13	58		T14	1
valid_sources[0x76]	1982	1			T9	73		T13	55		T20	1
valid_sources[0x77]	928	1			T13	31		T14	13		T45	23
valid_sources[0x78]	1370	1			T13	47		T45	45		T11	41
valid_sources[0x79]	1138	1			T9	4		T13	38		T14	1
valid_sources[0x7a]	1492	1			T9	1		T13	36		T14	2
valid_sources[0x7b]	1742	1			T9	85		T13	40		T14	13
valid_sources[0x7c]	1127	1			T13	44		T14	1		T45	5
valid_sources[0x7d]	1341	1			T13	37		T14	50		T45	25
valid_sources[0x7e]	1536	1			T9	3		T13	25		T45	20
valid_sources[0x7f]	1486	1			T1	1		T13	42		T20	1
valid_sources[0x80]	1382	1			T9	11		T13	37		T45	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80540

1

T7

9

T8

6

T9

680

values[0x0]

all_enables

biggest_size

116022

1

T1

5

T5

2

T9

955

values[0x1]

all_enables

biggest_size

116096

1

T9

929

T15

2

T13

3810