Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

687004

1

T2

68

T3

215

T4

185

full_word

424682

1

T2

6

T3

19

T4

14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1111396	1			T2	74		T3	234		T4	199
auto[TlIntgErrCmd]	93	1			T55	4		T56	8		T57	1
auto[TlIntgErrData]	114	1			T55	5		T56	7		T57	4
auto[TlIntgErrBoth]	83	1			T55	1		T56	5		T57	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197006

1

T2

74

T3

234

T4

199

auto[1]

914680

1

T9

9006

T13

29445

T14

14613

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	94458	1			T2	68		T3	215		T4	185
auto[TlIntgErrNone]	partial	auto[1]	592283	1			T9	5945		T13	19195		T14	9613
auto[TlIntgErrNone]	full_word	auto[0]	102407	1			T2	6		T3	19		T4	14
auto[TlIntgErrNone]	full_word	auto[1]	322248	1			T9	3061		T13	10250		T14	5000
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T56	5		T57	1		T94	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T55	4		T56	2		T94	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T96	1		T98	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T56	1		T99	1		T97	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T55	1		T56	4		T57	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T55	3		T56	3		T57	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T100	1		T97	1		T101	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T55	1		T95	1		T100	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T56	4		T94	4		T95	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T55	1		T56	1		T57	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T57	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T95	1		T97	1		T102	1