Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

302021

1

T1

8

T2

30

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	104459	1			T1	91		T2	392		T3	9
values[0x0]	113441	1			T4	2239		T8	753		T11	1975
values[0x1]	117192	1			T4	2425		T8	734		T11	2096

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15557	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

319535

1

T1

52

T2

242

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1311	1			T4	33		T8	3		T11	1
valid_sources[0x01]	1185	1			T4	34		T8	9		T11	24
valid_sources[0x02]	1369	1			T1	1		T4	32		T8	11
valid_sources[0x03]	1557	1			T4	37		T8	6		T47	7
valid_sources[0x04]	1196	1			T4	39		T8	8		T11	17
valid_sources[0x05]	1192	1			T4	21		T8	9		T47	15
valid_sources[0x06]	1464	1			T1	1		T4	22		T5	4
valid_sources[0x07]	1093	1			T4	25		T8	14		T47	11
valid_sources[0x08]	1117	1			T1	1		T4	26		T8	12
valid_sources[0x09]	1080	1			T4	36		T8	1		T47	28
valid_sources[0x0a]	1170	1			T4	25		T8	5		T47	26
valid_sources[0x0b]	1305	1			T4	25		T8	8		T11	282
valid_sources[0x0c]	1524	1			T4	27		T8	17		T11	50
valid_sources[0x0d]	1177	1			T1	1		T4	25		T8	9
valid_sources[0x0e]	1265	1			T4	24		T8	6		T47	18
valid_sources[0x0f]	1422	1			T4	25		T8	7		T47	17
valid_sources[0x10]	1237	1			T4	31		T8	5		T47	17
valid_sources[0x11]	1138	1			T4	29		T8	13		T47	14
valid_sources[0x12]	2645	1			T2	12		T4	26		T8	11
valid_sources[0x13]	1568	1			T4	38		T8	12		T15	22
valid_sources[0x14]	1340	1			T4	30		T5	1		T8	1
valid_sources[0x15]	1225	1			T4	28		T8	10		T47	9
valid_sources[0x16]	1269	1			T4	24		T8	6		T47	21
valid_sources[0x17]	1156	1			T1	2		T4	21		T8	9
valid_sources[0x18]	1325	1			T1	1		T4	27		T8	4
valid_sources[0x19]	1057	1			T4	25		T8	8		T47	20
valid_sources[0x1a]	1243	1			T1	2		T4	18		T5	6
valid_sources[0x1b]	1290	1			T4	21		T8	10		T11	125
valid_sources[0x1c]	1143	1			T1	1		T4	31		T8	5
valid_sources[0x1d]	1083	1			T4	21		T8	7		T47	11
valid_sources[0x1e]	1057	1			T1	2		T4	13		T8	8
valid_sources[0x1f]	1578	1			T4	31		T8	12		T47	15
valid_sources[0x20]	1146	1			T1	1		T4	34		T8	5
valid_sources[0x21]	1765	1			T4	27		T8	6		T47	8
valid_sources[0x22]	1062	1			T1	1		T4	34		T8	8
valid_sources[0x23]	2209	1			T4	27		T8	3		T11	400
valid_sources[0x24]	1075	1			T4	31		T8	11		T47	15
valid_sources[0x25]	1390	1			T4	27		T8	5		T47	19
valid_sources[0x26]	1297	1			T1	1		T4	25		T8	4
valid_sources[0x27]	1043	1			T4	33		T8	12		T47	12
valid_sources[0x28]	1296	1			T1	2		T4	33		T8	4
valid_sources[0x29]	1612	1			T1	1		T4	26		T8	10
valid_sources[0x2a]	1441	1			T1	1		T4	30		T8	8
valid_sources[0x2b]	1212	1			T4	25		T8	5		T11	33
valid_sources[0x2c]	1481	1			T4	31		T8	7		T11	183
valid_sources[0x2d]	1347	1			T4	31		T8	14		T47	9
valid_sources[0x2e]	1512	1			T4	21		T8	9		T47	16
valid_sources[0x2f]	1252	1			T1	2		T4	36		T8	5
valid_sources[0x30]	1871	1			T4	20		T8	2		T47	10
valid_sources[0x31]	1583	1			T4	24		T8	7		T11	1
valid_sources[0x32]	1084	1			T4	21		T8	7		T11	1
valid_sources[0x33]	1153	1			T1	1		T4	29		T6	2
valid_sources[0x34]	1406	1			T1	1		T4	31		T47	11
valid_sources[0x35]	1244	1			T1	1		T4	23		T8	9
valid_sources[0x36]	1178	1			T4	24		T8	12		T47	14
valid_sources[0x37]	1128	1			T4	24		T8	3		T47	16
valid_sources[0x38]	1367	1			T4	27		T8	7		T11	12
valid_sources[0x39]	1145	1			T1	1		T4	23		T8	5
valid_sources[0x3a]	1300	1			T4	32		T8	7		T47	11
valid_sources[0x3b]	1354	1			T4	19		T8	5		T47	22
valid_sources[0x3c]	1200	1			T1	1		T4	24		T8	4
valid_sources[0x3d]	1116	1			T1	1		T4	17		T8	9
valid_sources[0x3e]	1436	1			T4	25		T8	11		T47	7
valid_sources[0x3f]	1006	1			T1	1		T4	23		T8	16
valid_sources[0x40]	1187	1			T2	11		T4	25		T8	8
valid_sources[0x41]	1134	1			T4	32		T8	12		T47	26
valid_sources[0x42]	1458	1			T4	24		T8	11		T47	17
valid_sources[0x43]	1343	1			T4	29		T6	1		T8	10
valid_sources[0x44]	1197	1			T4	35		T8	5		T47	15
valid_sources[0x45]	1273	1			T1	1		T4	25		T8	6
valid_sources[0x46]	1186	1			T4	23		T8	14		T47	25
valid_sources[0x47]	1507	1			T3	1		T4	20		T8	6
valid_sources[0x48]	1189	1			T2	15		T4	22		T8	4
valid_sources[0x49]	1056	1			T4	19		T8	15		T47	20
valid_sources[0x4a]	1189	1			T1	1		T4	30		T8	4
valid_sources[0x4b]	1050	1			T4	20		T8	5		T11	9
valid_sources[0x4c]	1220	1			T4	26		T8	7		T9	2
valid_sources[0x4d]	1178	1			T1	1		T4	21		T5	3
valid_sources[0x4e]	1094	1			T1	1		T4	29		T8	6
valid_sources[0x4f]	1162	1			T1	1		T4	26		T8	8
valid_sources[0x50]	1376	1			T4	34		T5	2		T8	7
valid_sources[0x51]	1208	1			T4	23		T8	8		T47	10
valid_sources[0x52]	1307	1			T1	1		T4	31		T8	6
valid_sources[0x53]	1237	1			T1	1		T4	27		T8	10
valid_sources[0x54]	1287	1			T2	17		T4	32		T8	12
valid_sources[0x55]	1149	1			T4	26		T5	1		T8	6
valid_sources[0x56]	1791	1			T1	1		T4	25		T8	9
valid_sources[0x57]	1458	1			T4	31		T8	6		T47	14
valid_sources[0x58]	1151	1			T4	23		T8	7		T11	38
valid_sources[0x59]	1178	1			T4	32		T8	11		T47	9
valid_sources[0x5a]	1097	1			T2	7		T4	28		T8	6
valid_sources[0x5b]	1101	1			T4	33		T8	8		T47	10
valid_sources[0x5c]	1094	1			T1	1		T4	22		T8	15
valid_sources[0x5d]	1189	1			T4	19		T8	11		T47	10
valid_sources[0x5e]	1181	1			T4	15		T8	11		T47	12
valid_sources[0x5f]	1139	1			T4	25		T5	7		T8	5
valid_sources[0x60]	1337	1			T4	17		T8	10		T11	39
valid_sources[0x61]	1523	1			T1	2		T4	30		T8	6
valid_sources[0x62]	1048	1			T4	29		T8	17		T47	17
valid_sources[0x63]	1485	1			T4	29		T8	8		T11	99
valid_sources[0x64]	1295	1			T4	36		T8	9		T47	15
valid_sources[0x65]	1256	1			T1	2		T4	22		T8	7
valid_sources[0x66]	1396	1			T4	22		T8	7		T47	17
valid_sources[0x67]	1340	1			T4	19		T8	14		T47	30
valid_sources[0x68]	1367	1			T2	13		T4	17		T5	1
valid_sources[0x69]	2540	1			T1	2		T4	24		T8	11
valid_sources[0x6a]	1139	1			T4	29		T8	13		T47	22
valid_sources[0x6b]	1025	1			T3	1		T4	29		T8	8
valid_sources[0x6c]	1936	1			T4	20		T5	6		T8	7
valid_sources[0x6d]	1371	1			T4	30		T8	14		T15	44
valid_sources[0x6e]	1565	1			T1	1		T2	57		T4	32
valid_sources[0x6f]	1474	1			T1	1		T4	28		T8	7
valid_sources[0x70]	1032	1			T1	1		T4	31		T8	7
valid_sources[0x71]	1052	1			T4	29		T8	7		T47	21
valid_sources[0x72]	1639	1			T4	25		T8	11		T47	16
valid_sources[0x73]	1011	1			T4	16		T8	7		T11	8
valid_sources[0x74]	1132	1			T4	26		T8	13		T11	2
valid_sources[0x75]	1165	1			T4	13		T8	3		T11	2
valid_sources[0x76]	1534	1			T4	23		T8	5		T47	20
valid_sources[0x77]	1242	1			T1	1		T4	26		T8	12
valid_sources[0x78]	1215	1			T4	20		T8	10		T47	12
valid_sources[0x79]	1193	1			T4	23		T8	6		T47	14
valid_sources[0x7a]	2331	1			T1	1		T4	38		T8	16
valid_sources[0x7b]	1080	1			T4	31		T8	1		T47	16
valid_sources[0x7c]	1296	1			T4	28		T5	2		T8	10
valid_sources[0x7d]	1451	1			T3	1		T4	30		T5	1
valid_sources[0x7e]	2011	1			T4	29		T8	12		T47	11
valid_sources[0x7f]	1339	1			T2	24		T4	43		T8	7
valid_sources[0x80]	1171	1			T4	28		T8	7		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77495

1

T1

8

T2

30

T3

9

values[0x0]

all_enables

biggest_size

112421

1

T4

2213

T8

744

T11

1966

values[0x1]

all_enables

biggest_size

112105

1

T4

2303

T8

716

T11

2038

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261953

1

T3

10

T4

5925

T5

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	78667	1			T3	22		T4	1827		T5	32
values[0x0]	99471	1			T4	2146		T7	2		T8	719
values[0x1]	114232	1			T4	2632		T7	2		T8	786

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15995	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

276375

1

T3

12

T4

6279

T5

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	979	1			T4	23		T8	9		T47	10
valid_sources[0x01]	1036	1			T4	23		T8	8		T47	9
valid_sources[0x02]	1221	1			T4	30		T8	6		T11	74
valid_sources[0x03]	1121	1			T4	37		T8	3		T47	17
valid_sources[0x04]	1251	1			T4	24		T8	9		T47	11
valid_sources[0x05]	1093	1			T4	25		T8	8		T47	7
valid_sources[0x06]	1285	1			T4	25		T8	7		T11	4
valid_sources[0x07]	906	1			T4	19		T8	6		T11	5
valid_sources[0x08]	1506	1			T4	15		T8	8		T11	2
valid_sources[0x09]	937	1			T4	24		T8	7		T47	13
valid_sources[0x0a]	907	1			T4	31		T8	9		T11	1
valid_sources[0x0b]	1328	1			T4	33		T8	5		T47	13
valid_sources[0x0c]	1273	1			T4	19		T8	13		T47	9
valid_sources[0x0d]	1406	1			T4	19		T8	7		T47	17
valid_sources[0x0e]	1058	1			T4	21		T8	9		T11	3
valid_sources[0x0f]	1387	1			T4	31		T8	5		T9	1
valid_sources[0x10]	1031	1			T4	21		T8	7		T47	14
valid_sources[0x11]	922	1			T4	26		T8	10		T47	14
valid_sources[0x12]	990	1			T4	18		T8	13		T11	64
valid_sources[0x13]	1327	1			T4	33		T8	10		T11	1
valid_sources[0x14]	1308	1			T4	30		T8	9		T11	7
valid_sources[0x15]	911	1			T4	27		T8	6		T11	1
valid_sources[0x16]	1470	1			T4	17		T8	11		T47	7
valid_sources[0x17]	886	1			T4	28		T8	6		T11	1
valid_sources[0x18]	932	1			T4	28		T8	9		T47	13
valid_sources[0x19]	981	1			T4	37		T8	11		T11	1
valid_sources[0x1a]	1252	1			T4	32		T8	11		T11	7
valid_sources[0x1b]	1216	1			T4	22		T8	7		T11	3
valid_sources[0x1c]	1231	1			T4	28		T8	11		T11	1
valid_sources[0x1d]	1482	1			T4	32		T8	5		T47	14
valid_sources[0x1e]	863	1			T4	17		T8	10		T47	10
valid_sources[0x1f]	801	1			T4	27		T8	3		T47	21
valid_sources[0x20]	1030	1			T4	32		T8	8		T47	11
valid_sources[0x21]	1299	1			T4	35		T8	5		T47	12
valid_sources[0x22]	971	1			T4	32		T8	4		T47	10
valid_sources[0x23]	1311	1			T4	42		T8	10		T47	9
valid_sources[0x24]	1363	1			T4	27		T8	13		T47	21
valid_sources[0x25]	1081	1			T4	31		T8	12		T47	9
valid_sources[0x26]	1252	1			T4	23		T8	11		T11	4
valid_sources[0x27]	1185	1			T4	27		T8	3		T11	2
valid_sources[0x28]	1150	1			T4	25		T8	7		T11	3
valid_sources[0x29]	1109	1			T4	37		T8	6		T11	1
valid_sources[0x2a]	929	1			T4	16		T8	4		T47	16
valid_sources[0x2b]	1132	1			T4	17		T8	6		T47	19
valid_sources[0x2c]	1344	1			T4	21		T8	7		T10	2
valid_sources[0x2d]	916	1			T4	19		T8	9		T47	16
valid_sources[0x2e]	922	1			T4	22		T8	4		T11	2
valid_sources[0x2f]	1033	1			T4	28		T8	3		T47	16
valid_sources[0x30]	1032	1			T4	25		T8	8		T11	2
valid_sources[0x31]	1050	1			T4	37		T8	7		T11	38
valid_sources[0x32]	1225	1			T4	26		T8	4		T47	21
valid_sources[0x33]	1259	1			T4	26		T8	7		T11	6
valid_sources[0x34]	1451	1			T4	32		T8	9		T11	4
valid_sources[0x35]	1141	1			T4	22		T8	7		T11	121
valid_sources[0x36]	895	1			T4	26		T47	14		T14	1
valid_sources[0x37]	1216	1			T4	33		T8	7		T47	11
valid_sources[0x38]	1317	1			T4	14		T8	12		T47	12
valid_sources[0x39]	934	1			T4	39		T8	10		T47	16
valid_sources[0x3a]	1565	1			T4	20		T6	1		T8	10
valid_sources[0x3b]	888	1			T4	22		T8	10		T11	1
valid_sources[0x3c]	1319	1			T4	26		T8	5		T47	12
valid_sources[0x3d]	964	1			T4	19		T8	5		T11	1
valid_sources[0x3e]	888	1			T4	23		T8	7		T47	22
valid_sources[0x3f]	1351	1			T4	22		T8	6		T11	108
valid_sources[0x40]	924	1			T4	26		T8	6		T11	3
valid_sources[0x41]	1085	1			T4	29		T8	11		T47	11
valid_sources[0x42]	1210	1			T4	29		T8	5		T47	9
valid_sources[0x43]	1311	1			T4	19		T8	10		T9	1
valid_sources[0x44]	1441	1			T4	41		T8	5		T11	2
valid_sources[0x45]	1211	1			T4	22		T8	5		T47	19
valid_sources[0x46]	1344	1			T4	23		T8	11		T47	15
valid_sources[0x47]	1189	1			T4	26		T6	1		T8	6
valid_sources[0x48]	1124	1			T4	26		T8	11		T47	17
valid_sources[0x49]	1003	1			T4	22		T8	14		T47	14
valid_sources[0x4a]	1303	1			T4	27		T8	3		T11	1
valid_sources[0x4b]	1380	1			T4	20		T8	10		T11	2
valid_sources[0x4c]	1269	1			T4	25		T8	8		T10	3
valid_sources[0x4d]	1108	1			T4	31		T8	6		T47	13
valid_sources[0x4e]	1292	1			T4	24		T6	1		T8	12
valid_sources[0x4f]	970	1			T4	40		T7	4		T8	15
valid_sources[0x50]	1226	1			T4	27		T8	10		T47	6
valid_sources[0x51]	1064	1			T4	29		T8	9		T11	1
valid_sources[0x52]	1109	1			T4	21		T8	9		T47	20
valid_sources[0x53]	1263	1			T4	29		T8	8		T11	1
valid_sources[0x54]	984	1			T4	23		T8	12		T11	151
valid_sources[0x55]	915	1			T4	20		T8	6		T47	16
valid_sources[0x56]	895	1			T4	22		T8	10		T47	18
valid_sources[0x57]	1068	1			T4	20		T8	5		T11	1
valid_sources[0x58]	1014	1			T4	24		T8	7		T9	1
valid_sources[0x59]	1031	1			T4	36		T8	10		T58	1
valid_sources[0x5a]	843	1			T4	22		T8	4		T47	14
valid_sources[0x5b]	1234	1			T4	30		T8	10		T11	74
valid_sources[0x5c]	1062	1			T4	16		T8	17		T11	2
valid_sources[0x5d]	1108	1			T4	26		T8	3		T11	1
valid_sources[0x5e]	1916	1			T4	26		T8	15		T47	15
valid_sources[0x5f]	850	1			T4	19		T8	9		T47	17
valid_sources[0x60]	970	1			T4	23		T8	5		T11	2
valid_sources[0x61]	1131	1			T4	38		T8	6		T11	1
valid_sources[0x62]	1031	1			T4	32		T8	4		T11	40
valid_sources[0x63]	1192	1			T4	33		T8	4		T11	2
valid_sources[0x64]	1056	1			T4	24		T5	32		T8	6
valid_sources[0x65]	1044	1			T4	24		T6	1		T8	6
valid_sources[0x66]	1078	1			T4	24		T8	5		T47	8
valid_sources[0x67]	1011	1			T4	27		T8	9		T11	1
valid_sources[0x68]	813	1			T4	33		T8	16		T11	5
valid_sources[0x69]	1335	1			T4	18		T8	7		T11	2
valid_sources[0x6a]	1389	1			T4	19		T8	7		T11	1
valid_sources[0x6b]	1295	1			T4	21		T8	8		T47	6
valid_sources[0x6c]	1203	1			T4	21		T8	3		T47	15
valid_sources[0x6d]	1148	1			T4	20		T8	10		T47	13
valid_sources[0x6e]	998	1			T4	25		T8	1		T47	13
valid_sources[0x6f]	970	1			T4	34		T8	6		T9	1
valid_sources[0x70]	1175	1			T4	26		T8	15		T11	93
valid_sources[0x71]	1077	1			T4	27		T8	8		T47	21
valid_sources[0x72]	1086	1			T4	19		T8	9		T11	1
valid_sources[0x73]	1112	1			T4	26		T8	7		T11	139
valid_sources[0x74]	1377	1			T4	31		T8	6		T11	42
valid_sources[0x75]	1141	1			T4	29		T8	7		T11	1
valid_sources[0x76]	1182	1			T4	20		T8	16		T58	3
valid_sources[0x77]	996	1			T4	33		T8	6		T21	1
valid_sources[0x78]	989	1			T4	17		T8	10		T47	13
valid_sources[0x79]	1307	1			T4	21		T8	13		T47	17
valid_sources[0x7a]	1167	1			T4	25		T8	13		T11	3
valid_sources[0x7b]	1235	1			T4	30		T8	6		T47	13
valid_sources[0x7c]	1101	1			T4	28		T8	9		T47	18
valid_sources[0x7d]	908	1			T4	16		T8	5		T47	2
valid_sources[0x7e]	1472	1			T4	38		T8	9		T47	13
valid_sources[0x7f]	1295	1			T4	20		T8	12		T47	17
valid_sources[0x80]	1183	1			T4	25		T8	10		T47	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67535

1

T3

10

T4

1612

T5

17

values[0x0]

all_enables

biggest_size

96981

1

T4

2097

T8

705

T10

3

values[0x1]

all_enables

biggest_size

97437

1

T4

2216

T8

679

T10

1