Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

565813

1

T1

83

T2

362

T4

15127

full_word

352340

1

T1

8

T2

30

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	917873	1			T1	91		T2	392		T3	6
auto[TlIntgErrCmd]	79	1			T52	8		T53	5		T54	4
auto[TlIntgErrData]	99	1			T52	4		T53	7		T54	3
auto[TlIntgErrBoth]	102	1			T52	8		T53	8		T54	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166337

1

T1

91

T2

392

T3

6

auto[1]

751816

1

T4

18963

T8

4417

T11

11222

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	81215	1			T1	83		T2	362		T4	1877
auto[TlIntgErrNone]	partial	auto[1]	484338	1			T4	13250		T8	2739		T11	6630
auto[TlIntgErrNone]	full_word	auto[0]	85019	1			T1	8		T2	30		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	267301	1			T4	5713		T8	1678		T11	4592
auto[TlIntgErrCmd]	partial	auto[0]	21	1			T52	1		T53	2		T54	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T52	6		T53	3		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T106	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T52	1		T107	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T52	1		T53	2		T54	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T52	3		T53	4		T54	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T53	1		T109	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T109	1		T106	2		T111	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T52	3		T53	3		T54	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T52	4		T53	5		T54	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T52	1		T112	3		T110	1