Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

655154

1

T1

90

T2

34

T4

126

full_word

399703

1

T1

6

T2

3

T4

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1054557	1			T1	96		T2	37		T4	139
auto[TlIntgErrCmd]	101	1			T77	2		T78	2		T79	5
auto[TlIntgErrData]	98	1			T77	5		T78	4		T79	4
auto[TlIntgErrBoth]	101	1			T77	3		T78	4		T79	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187068

1

T1

96

T2

37

T4

139

auto[1]

867789

1

T16

16511

T17

5300

T18

3636

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	90849	1			T1	90		T2	34		T4	126
auto[TlIntgErrNone]	partial	auto[1]	564033	1			T16	11098		T17	3111		T18	2482
auto[TlIntgErrNone]	full_word	auto[0]	96073	1			T1	6		T2	3		T4	13
auto[TlIntgErrNone]	full_word	auto[1]	303602	1			T16	5413		T17	2189		T18	1154
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T77	1		T78	1		T122	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T78	1		T79	5		T122	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T127	1		T131	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T77	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T78	3		T79	1		T122	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T77	3		T78	1		T79	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T77	1		T122	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T77	1		T126	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T77	1		T78	2		T122	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T77	1		T78	2		T79	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T126	2		T131	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T77	1		T134	1		T125	1