Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T4
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T4
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 9 | 56.25 |
| Logical | 16 | 9 | 56.25 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T5,T13 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 24 | 19 | 79.17 |
| Logical | 24 | 19 | 79.17 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T5,T13 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95460678 |
1887204 |
0 |
0 |
| T1 |
27405 |
288 |
0 |
0 |
| T2 |
40683 |
419 |
0 |
0 |
| T3 |
38346 |
0 |
0 |
0 |
| T4 |
28617 |
417 |
0 |
0 |
| T5 |
30747 |
308 |
0 |
0 |
| T6 |
27282 |
90 |
0 |
0 |
| T7 |
295806 |
0 |
0 |
0 |
| T8 |
37314 |
0 |
0 |
0 |
| T9 |
39900 |
75 |
0 |
0 |
| T10 |
75042 |
0 |
0 |
0 |
| T11 |
0 |
282 |
0 |
0 |
| T13 |
0 |
399 |
0 |
0 |
| T14 |
0 |
1062 |
0 |
0 |
| T15 |
0 |
90 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95460678 |
94952490 |
0 |
0 |
| T1 |
27405 |
27207 |
0 |
0 |
| T2 |
40683 |
40386 |
0 |
0 |
| T3 |
38346 |
38067 |
0 |
0 |
| T4 |
28617 |
28404 |
0 |
0 |
| T5 |
30747 |
30519 |
0 |
0 |
| T6 |
27282 |
27015 |
0 |
0 |
| T7 |
295806 |
295404 |
0 |
0 |
| T8 |
37314 |
37065 |
0 |
0 |
| T9 |
39900 |
39678 |
0 |
0 |
| T10 |
75042 |
74469 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95460678 |
94952490 |
0 |
0 |
| T1 |
27405 |
27207 |
0 |
0 |
| T2 |
40683 |
40386 |
0 |
0 |
| T3 |
38346 |
38067 |
0 |
0 |
| T4 |
28617 |
28404 |
0 |
0 |
| T5 |
30747 |
30519 |
0 |
0 |
| T6 |
27282 |
27015 |
0 |
0 |
| T7 |
295806 |
295404 |
0 |
0 |
| T8 |
37314 |
37065 |
0 |
0 |
| T9 |
39900 |
39678 |
0 |
0 |
| T10 |
75042 |
74469 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95460678 |
94952490 |
0 |
0 |
| T1 |
27405 |
27207 |
0 |
0 |
| T2 |
40683 |
40386 |
0 |
0 |
| T3 |
38346 |
38067 |
0 |
0 |
| T4 |
28617 |
28404 |
0 |
0 |
| T5 |
30747 |
30519 |
0 |
0 |
| T6 |
27282 |
27015 |
0 |
0 |
| T7 |
295806 |
295404 |
0 |
0 |
| T8 |
37314 |
37065 |
0 |
0 |
| T9 |
39900 |
39678 |
0 |
0 |
| T10 |
75042 |
74469 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95460678 |
1887204 |
0 |
0 |
| T1 |
27405 |
288 |
0 |
0 |
| T2 |
40683 |
419 |
0 |
0 |
| T3 |
38346 |
0 |
0 |
0 |
| T4 |
28617 |
417 |
0 |
0 |
| T5 |
30747 |
308 |
0 |
0 |
| T6 |
27282 |
90 |
0 |
0 |
| T7 |
295806 |
0 |
0 |
0 |
| T8 |
37314 |
0 |
0 |
0 |
| T9 |
39900 |
75 |
0 |
0 |
| T10 |
75042 |
0 |
0 |
0 |
| T11 |
0 |
282 |
0 |
0 |
| T13 |
0 |
399 |
0 |
0 |
| T14 |
0 |
1062 |
0 |
0 |
| T15 |
0 |
90 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T4
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 16 | 9 | 56.25 |
| Logical | 16 | 9 | 56.25 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
32622 |
0 |
0 |
| T1 |
9135 |
96 |
0 |
0 |
| T2 |
13561 |
37 |
0 |
0 |
| T3 |
12782 |
0 |
0 |
0 |
| T4 |
9539 |
139 |
0 |
0 |
| T5 |
10249 |
24 |
0 |
0 |
| T6 |
9094 |
30 |
0 |
0 |
| T7 |
98602 |
0 |
0 |
0 |
| T8 |
12438 |
0 |
0 |
0 |
| T9 |
13300 |
25 |
0 |
0 |
| T10 |
25014 |
0 |
0 |
0 |
| T11 |
0 |
94 |
0 |
0 |
| T13 |
0 |
133 |
0 |
0 |
| T14 |
0 |
354 |
0 |
0 |
| T15 |
0 |
30 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
32622 |
0 |
0 |
| T1 |
9135 |
96 |
0 |
0 |
| T2 |
13561 |
37 |
0 |
0 |
| T3 |
12782 |
0 |
0 |
0 |
| T4 |
9539 |
139 |
0 |
0 |
| T5 |
10249 |
24 |
0 |
0 |
| T6 |
9094 |
30 |
0 |
0 |
| T7 |
98602 |
0 |
0 |
0 |
| T8 |
12438 |
0 |
0 |
0 |
| T9 |
13300 |
25 |
0 |
0 |
| T10 |
25014 |
0 |
0 |
0 |
| T11 |
0 |
94 |
0 |
0 |
| T13 |
0 |
133 |
0 |
0 |
| T14 |
0 |
354 |
0 |
0 |
| T15 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T4
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T5,T13 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
1800298 |
0 |
0 |
| T1 |
9135 |
96 |
0 |
0 |
| T2 |
13561 |
191 |
0 |
0 |
| T3 |
12782 |
0 |
0 |
0 |
| T4 |
9539 |
139 |
0 |
0 |
| T5 |
10249 |
142 |
0 |
0 |
| T6 |
9094 |
30 |
0 |
0 |
| T7 |
98602 |
0 |
0 |
0 |
| T8 |
12438 |
0 |
0 |
0 |
| T9 |
13300 |
25 |
0 |
0 |
| T10 |
25014 |
0 |
0 |
0 |
| T11 |
0 |
94 |
0 |
0 |
| T13 |
0 |
133 |
0 |
0 |
| T14 |
0 |
354 |
0 |
0 |
| T15 |
0 |
30 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
1800298 |
0 |
0 |
| T1 |
9135 |
96 |
0 |
0 |
| T2 |
13561 |
191 |
0 |
0 |
| T3 |
12782 |
0 |
0 |
0 |
| T4 |
9539 |
139 |
0 |
0 |
| T5 |
10249 |
142 |
0 |
0 |
| T6 |
9094 |
30 |
0 |
0 |
| T7 |
98602 |
0 |
0 |
0 |
| T8 |
12438 |
0 |
0 |
0 |
| T9 |
13300 |
25 |
0 |
0 |
| T10 |
25014 |
0 |
0 |
0 |
| T11 |
0 |
94 |
0 |
0 |
| T13 |
0 |
133 |
0 |
0 |
| T14 |
0 |
354 |
0 |
0 |
| T15 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T4
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 24 | 19 | 79.17 |
| Logical | 24 | 19 | 79.17 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T5,T13 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T12 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
54284 |
0 |
0 |
| T1 |
9135 |
96 |
0 |
0 |
| T2 |
13561 |
191 |
0 |
0 |
| T3 |
12782 |
0 |
0 |
0 |
| T4 |
9539 |
139 |
0 |
0 |
| T5 |
10249 |
142 |
0 |
0 |
| T6 |
9094 |
30 |
0 |
0 |
| T7 |
98602 |
0 |
0 |
0 |
| T8 |
12438 |
0 |
0 |
0 |
| T9 |
13300 |
25 |
0 |
0 |
| T10 |
25014 |
0 |
0 |
0 |
| T11 |
0 |
94 |
0 |
0 |
| T13 |
0 |
133 |
0 |
0 |
| T14 |
0 |
354 |
0 |
0 |
| T15 |
0 |
30 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
31650830 |
0 |
0 |
| T1 |
9135 |
9069 |
0 |
0 |
| T2 |
13561 |
13462 |
0 |
0 |
| T3 |
12782 |
12689 |
0 |
0 |
| T4 |
9539 |
9468 |
0 |
0 |
| T5 |
10249 |
10173 |
0 |
0 |
| T6 |
9094 |
9005 |
0 |
0 |
| T7 |
98602 |
98468 |
0 |
0 |
| T8 |
12438 |
12355 |
0 |
0 |
| T9 |
13300 |
13226 |
0 |
0 |
| T10 |
25014 |
24823 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31820226 |
54284 |
0 |
0 |
| T1 |
9135 |
96 |
0 |
0 |
| T2 |
13561 |
191 |
0 |
0 |
| T3 |
12782 |
0 |
0 |
0 |
| T4 |
9539 |
139 |
0 |
0 |
| T5 |
10249 |
142 |
0 |
0 |
| T6 |
9094 |
30 |
0 |
0 |
| T7 |
98602 |
0 |
0 |
0 |
| T8 |
12438 |
0 |
0 |
0 |
| T9 |
13300 |
25 |
0 |
0 |
| T10 |
25014 |
0 |
0 |
0 |
| T11 |
0 |
94 |
0 |
0 |
| T13 |
0 |
133 |
0 |
0 |
| T14 |
0 |
354 |
0 |
0 |
| T15 |
0 |
30 |
0 |
0 |