Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

294404

1

T2

6

T3

8

T4

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	104729	1			T2	49		T3	90		T4	47
values[0x0]	110099	1			T11	760		T12	1129		T13	624
values[0x1]	113867	1			T11	785		T12	1084		T13	698

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16046	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

312649

1

T2

25

T3

52

T4

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1237	1			T18	1		T116	2		T137	1
valid_sources[0x01]	1333	1			T6	2		T21	3		T14	3
valid_sources[0x02]	1917	1			T5	1		T11	5		T12	19
valid_sources[0x03]	1090	1			T3	1		T5	1		T6	1
valid_sources[0x04]	1107	1			T6	6		T113	3		T114	4
valid_sources[0x05]	1199	1			T5	2		T6	5		T18	3
valid_sources[0x06]	1190	1			T3	1		T113	5		T114	3
valid_sources[0x07]	1146	1			T5	4		T9	19		T21	7
valid_sources[0x08]	1171	1			T19	4		T30	18		T137	1
valid_sources[0x09]	1303	1			T5	3		T18	4		T21	1
valid_sources[0x0a]	923	1			T5	1		T6	3		T19	1
valid_sources[0x0b]	2158	1			T5	1		T20	3		T19	1
valid_sources[0x0c]	1211	1			T5	2		T137	1		T38	2
valid_sources[0x0d]	1097	1			T16	3		T37	2		T38	9
valid_sources[0x0e]	1314	1			T5	1		T116	5		T38	1
valid_sources[0x0f]	1570	1			T4	2		T5	2		T113	1
valid_sources[0x10]	1887	1			T9	3		T14	4		T38	1
valid_sources[0x11]	1057	1			T3	1		T21	2		T113	12
valid_sources[0x12]	1045	1			T5	2		T6	1		T21	5
valid_sources[0x13]	1040	1			T5	1		T6	3		T21	2
valid_sources[0x14]	1184	1			T137	1		T32	1		T11	17
valid_sources[0x15]	1094	1			T3	2		T5	2		T6	5
valid_sources[0x16]	1009	1			T114	2		T11	7		T12	16
valid_sources[0x17]	1707	1			T3	1		T18	1		T113	4
valid_sources[0x18]	1870	1			T4	1		T5	1		T113	5
valid_sources[0x19]	1159	1			T20	6		T14	3		T113	1
valid_sources[0x1a]	1161	1			T5	1		T14	2		T16	5
valid_sources[0x1b]	1760	1			T5	2		T6	3		T113	1
valid_sources[0x1c]	1098	1			T5	2		T6	2		T21	2
valid_sources[0x1d]	1719	1			T5	1		T6	10		T114	4
valid_sources[0x1e]	1297	1			T3	1		T114	1		T137	2
valid_sources[0x1f]	1530	1			T3	1		T5	1		T114	1
valid_sources[0x20]	1160	1			T5	1		T113	2		T114	3
valid_sources[0x21]	1226	1			T5	4		T19	3		T38	1
valid_sources[0x22]	1078	1			T5	1		T113	1		T137	1
valid_sources[0x23]	1493	1			T5	1		T20	8		T21	1
valid_sources[0x24]	1070	1			T3	1		T113	1		T19	1
valid_sources[0x25]	1649	1			T6	1		T19	1		T116	7
valid_sources[0x26]	1058	1			T4	3		T21	1		T16	3
valid_sources[0x27]	1040	1			T5	2		T114	3		T137	1
valid_sources[0x28]	926	1			T21	1		T19	3		T137	1
valid_sources[0x29]	1231	1			T4	1		T5	1		T6	1
valid_sources[0x2a]	1073	1			T5	1		T21	2		T19	3
valid_sources[0x2b]	987	1			T5	2		T21	1		T114	1
valid_sources[0x2c]	1067	1			T5	1		T6	5		T21	1
valid_sources[0x2d]	3158	1			T5	3		T6	2		T21	2
valid_sources[0x2e]	1006	1			T5	1		T21	2		T67	2
valid_sources[0x2f]	1172	1			T3	1		T137	2		T38	3
valid_sources[0x30]	1288	1			T3	1		T6	1		T21	1
valid_sources[0x31]	1120	1			T5	1		T6	5		T21	3
valid_sources[0x32]	1213	1			T5	1		T21	1		T113	3
valid_sources[0x33]	1522	1			T6	8		T116	1		T137	2
valid_sources[0x34]	1172	1			T5	3		T6	1		T113	1
valid_sources[0x35]	1339	1			T5	2		T114	2		T116	6
valid_sources[0x36]	1665	1			T5	2		T137	1		T37	1
valid_sources[0x37]	1099	1			T5	3		T113	1		T114	1
valid_sources[0x38]	1155	1			T21	1		T115	28		T67	1
valid_sources[0x39]	1285	1			T3	1		T137	1		T11	10
valid_sources[0x3a]	1320	1			T5	2		T6	2		T20	11
valid_sources[0x3b]	1325	1			T3	1		T6	13		T16	1
valid_sources[0x3c]	1065	1			T3	2		T5	1		T6	2
valid_sources[0x3d]	1079	1			T20	6		T19	1		T32	2
valid_sources[0x3e]	1075	1			T3	1		T5	7		T37	1
valid_sources[0x3f]	1462	1			T5	1		T137	2		T11	7
valid_sources[0x40]	1126	1			T5	2		T67	1		T38	1
valid_sources[0x41]	1141	1			T5	1		T18	2		T21	1
valid_sources[0x42]	1052	1			T21	3		T19	2		T137	2
valid_sources[0x43]	1914	1			T3	1		T116	4		T137	2
valid_sources[0x44]	1360	1			T5	3		T19	1		T137	3
valid_sources[0x45]	1142	1			T14	1		T113	1		T11	8
valid_sources[0x46]	1267	1			T4	1		T5	1		T21	1
valid_sources[0x47]	1353	1			T3	1		T5	2		T137	4
valid_sources[0x48]	1657	1			T5	1		T6	1		T20	2
valid_sources[0x49]	1504	1			T3	1		T18	3		T113	3
valid_sources[0x4a]	1312	1			T67	1		T81	23		T137	1
valid_sources[0x4b]	1211	1			T3	1		T4	1		T5	1
valid_sources[0x4c]	1290	1			T3	1		T5	3		T137	1
valid_sources[0x4d]	1312	1			T6	2		T21	2		T114	1
valid_sources[0x4e]	1135	1			T5	1		T20	1		T67	1
valid_sources[0x4f]	1049	1			T5	3		T6	3		T18	1
valid_sources[0x50]	1012	1			T4	1		T5	1		T113	1
valid_sources[0x51]	1293	1			T4	2		T5	1		T19	1
valid_sources[0x52]	1655	1			T5	1		T21	3		T11	3
valid_sources[0x53]	1266	1			T5	2		T6	3		T16	1
valid_sources[0x54]	1353	1			T3	1		T21	2		T67	1
valid_sources[0x55]	1331	1			T3	1		T5	2		T6	1
valid_sources[0x56]	1053	1			T4	8		T5	2		T21	1
valid_sources[0x57]	1152	1			T3	1		T5	1		T113	8
valid_sources[0x58]	1156	1			T38	2		T32	3		T11	12
valid_sources[0x59]	1485	1			T5	2		T21	3		T137	3
valid_sources[0x5a]	1044	1			T21	2		T137	1		T11	7
valid_sources[0x5b]	1151	1			T3	1		T4	4		T6	6
valid_sources[0x5c]	1094	1			T21	1		T137	1		T38	1
valid_sources[0x5d]	1313	1			T6	3		T21	1		T113	2
valid_sources[0x5e]	1380	1			T5	2		T6	2		T21	1
valid_sources[0x5f]	1256	1			T3	1		T9	9		T21	1
valid_sources[0x60]	1163	1			T3	1		T5	1		T21	1
valid_sources[0x61]	1156	1			T5	1		T137	1		T11	4
valid_sources[0x62]	1868	1			T5	1		T114	1		T11	8
valid_sources[0x63]	1000	1			T3	1		T5	1		T6	4
valid_sources[0x64]	1226	1			T5	1		T21	1		T113	1
valid_sources[0x65]	1061	1			T5	1		T6	1		T19	2
valid_sources[0x66]	1327	1			T5	2		T30	2		T67	1
valid_sources[0x67]	1066	1			T5	1		T6	1		T21	3
valid_sources[0x68]	1105	1			T5	2		T18	1		T19	1
valid_sources[0x69]	1272	1			T3	1		T116	2		T137	2
valid_sources[0x6a]	1254	1			T6	1		T38	3		T11	8
valid_sources[0x6b]	1151	1			T3	1		T5	2		T113	1
valid_sources[0x6c]	1256	1			T4	2		T5	3		T11	12
valid_sources[0x6d]	1015	1			T5	3		T21	1		T113	4
valid_sources[0x6e]	1264	1			T5	1		T6	1		T21	1
valid_sources[0x6f]	1226	1			T3	1		T5	2		T6	3
valid_sources[0x70]	1653	1			T3	1		T5	4		T18	1
valid_sources[0x71]	1113	1			T5	1		T114	1		T115	10
valid_sources[0x72]	1047	1			T5	2		T18	1		T38	8
valid_sources[0x73]	1340	1			T6	7		T19	1		T38	2
valid_sources[0x74]	1023	1			T5	1		T6	3		T21	2
valid_sources[0x75]	1505	1			T4	3		T5	1		T37	1
valid_sources[0x76]	1409	1			T5	2		T21	1		T113	1
valid_sources[0x77]	1084	1			T3	2		T5	1		T21	1
valid_sources[0x78]	1486	1			T21	2		T113	2		T137	1
valid_sources[0x79]	2503	1			T5	1		T6	4		T21	1
valid_sources[0x7a]	1004	1			T5	1		T67	1		T137	1
valid_sources[0x7b]	1000	1			T3	3		T5	2		T21	1
valid_sources[0x7c]	1109	1			T21	3		T19	1		T137	3
valid_sources[0x7d]	1178	1			T3	1		T21	1		T113	1
valid_sources[0x7e]	1401	1			T4	2		T137	2		T37	1
valid_sources[0x7f]	1130	1			T6	3		T21	1		T137	2
valid_sources[0x80]	1118	1			T5	3		T6	7		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76329

1

T2

6

T3

8

T4

9

values[0x0]

all_enables

biggest_size

109064

1

T11

750

T12

1120

T13

620

values[0x1]

all_enables

biggest_size

109011

1

T11

747

T12

1040

T13

676

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30394	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256630

1

T1

3

T2

8

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	77763	1			T2	16		T3	48		T4	16
values[0x0]	97687	1			T1	6		T29	4		T15	3
values[0x1]	111574	1			T1	6		T8	1		T29	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

270722

1

T1

4

T2

12

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1031	1			T32	2		T12	9		T24	21
valid_sources[0x01]	1056	1			T19	1		T32	2		T12	18
valid_sources[0x02]	1280	1			T9	1		T30	1		T117	1
valid_sources[0x03]	1477	1			T21	1		T11	21		T12	13
valid_sources[0x04]	1150	1			T37	2		T32	2		T12	11
valid_sources[0x05]	1507	1			T2	13		T117	1		T32	2
valid_sources[0x06]	861	1			T11	9		T12	13		T17	28
valid_sources[0x07]	1413	1			T12	17		T17	29		T52	4
valid_sources[0x08]	1457	1			T21	1		T11	65		T12	23
valid_sources[0x09]	1468	1			T19	1		T71	1		T32	2
valid_sources[0x0a]	1242	1			T21	1		T30	1		T12	15
valid_sources[0x0b]	1398	1			T11	14		T12	13		T59	1
valid_sources[0x0c]	1753	1			T30	1		T12	19		T17	21
valid_sources[0x0d]	918	1			T7	1		T21	1		T11	1
valid_sources[0x0e]	1184	1			T117	4		T11	7		T12	10
valid_sources[0x0f]	1037	1			T37	1		T12	9		T138	1
valid_sources[0x10]	953	1			T30	1		T11	1		T12	11
valid_sources[0x11]	927	1			T117	1		T12	11		T13	2
valid_sources[0x12]	960	1			T21	1		T19	3		T67	3
valid_sources[0x13]	899	1			T21	1		T19	1		T11	18
valid_sources[0x14]	1262	1			T21	1		T11	11		T12	8
valid_sources[0x15]	1094	1			T9	1		T11	3		T41	2
valid_sources[0x16]	1382	1			T21	1		T32	6		T11	4
valid_sources[0x17]	1382	1			T21	1		T32	6		T11	4
valid_sources[0x18]	1111	1			T18	16		T11	3		T12	16
valid_sources[0x19]	1148	1			T25	1		T11	11		T41	12
valid_sources[0x1a]	1180	1			T19	2		T12	11		T138	1
valid_sources[0x1b]	1324	1			T21	1		T12	15		T17	15
valid_sources[0x1c]	1031	1			T21	1		T115	1		T11	2
valid_sources[0x1d]	1594	1			T30	2		T11	3		T12	4
valid_sources[0x1e]	1272	1			T32	2		T11	3		T12	18
valid_sources[0x1f]	1223	1			T115	1		T30	2		T11	9
valid_sources[0x20]	1287	1			T9	1		T19	2		T117	4
valid_sources[0x21]	1335	1			T11	18		T12	11		T17	18
valid_sources[0x22]	811	1			T11	6		T58	3		T12	8
valid_sources[0x23]	777	1			T21	1		T37	1		T11	2
valid_sources[0x24]	902	1			T21	1		T19	1		T115	1
valid_sources[0x25]	987	1			T19	2		T32	1		T12	12
valid_sources[0x26]	931	1			T21	1		T11	16		T12	23
valid_sources[0x27]	829	1			T21	2		T72	1		T25	1
valid_sources[0x28]	1155	1			T9	2		T21	1		T115	1
valid_sources[0x29]	1361	1			T16	16		T30	2		T12	8
valid_sources[0x2a]	1318	1			T15	1		T81	2		T11	5
valid_sources[0x2b]	1233	1			T9	1		T21	1		T19	1
valid_sources[0x2c]	944	1			T21	2		T72	1		T11	3
valid_sources[0x2d]	1394	1			T19	1		T72	1		T12	15
valid_sources[0x2e]	1181	1			T21	2		T12	9		T13	19
valid_sources[0x2f]	712	1			T15	1		T11	7		T12	6
valid_sources[0x30]	913	1			T2	2		T9	1		T19	2
valid_sources[0x31]	1238	1			T21	1		T30	2		T37	1
valid_sources[0x32]	894	1			T30	2		T81	2		T11	24
valid_sources[0x33]	818	1			T115	1		T81	1		T117	2
valid_sources[0x34]	1387	1			T21	2		T11	9		T12	8
valid_sources[0x35]	1067	1			T11	8		T12	9		T17	15
valid_sources[0x36]	1214	1			T115	3		T37	2		T11	35
valid_sources[0x37]	895	1			T19	1		T11	12		T12	11
valid_sources[0x38]	914	1			T67	7		T11	15		T12	18
valid_sources[0x39]	1184	1			T12	14		T60	1		T17	24
valid_sources[0x3a]	976	1			T4	16		T19	1		T30	1
valid_sources[0x3b]	1300	1			T19	1		T11	9		T12	9
valid_sources[0x3c]	1041	1			T72	1		T11	7		T12	12
valid_sources[0x3d]	1021	1			T21	1		T117	1		T11	1
valid_sources[0x3e]	1199	1			T11	26		T12	16		T17	20
valid_sources[0x3f]	1383	1			T11	3		T12	12		T13	101
valid_sources[0x40]	993	1			T11	14		T12	4		T17	25
valid_sources[0x41]	1094	1			T11	1		T12	23		T13	10
valid_sources[0x42]	965	1			T30	1		T11	30		T12	4
valid_sources[0x43]	1000	1			T11	20		T12	10		T17	29
valid_sources[0x44]	905	1			T29	1		T21	1		T11	23
valid_sources[0x45]	1197	1			T21	1		T30	1		T12	16
valid_sources[0x46]	1414	1			T11	20		T12	12		T60	1
valid_sources[0x47]	1065	1			T11	17		T12	18		T13	2
valid_sources[0x48]	1318	1			T11	17		T12	14		T59	2
valid_sources[0x49]	1177	1			T37	1		T11	25		T12	13
valid_sources[0x4a]	1018	1			T12	9		T34	1		T17	25
valid_sources[0x4b]	944	1			T21	1		T19	1		T117	1
valid_sources[0x4c]	838	1			T11	31		T12	4		T60	2
valid_sources[0x4d]	849	1			T30	1		T81	1		T12	3
valid_sources[0x4e]	892	1			T21	1		T11	2		T12	9
valid_sources[0x4f]	1498	1			T11	23		T12	20		T139	1
valid_sources[0x50]	743	1			T11	1		T12	20		T27	1
valid_sources[0x51]	917	1			T21	1		T15	1		T11	10
valid_sources[0x52]	868	1			T9	1		T19	2		T11	14
valid_sources[0x53]	1382	1			T66	3		T37	1		T11	17
valid_sources[0x54]	908	1			T12	25		T140	1		T13	1
valid_sources[0x55]	1180	1			T21	3		T11	1		T12	11
valid_sources[0x56]	703	1			T12	22		T17	30		T53	23
valid_sources[0x57]	1308	1			T115	1		T11	1		T12	12
valid_sources[0x58]	1192	1			T12	5		T13	38		T34	1
valid_sources[0x59]	1532	1			T11	2		T12	19		T59	1
valid_sources[0x5a]	1042	1			T9	1		T30	1		T11	1
valid_sources[0x5b]	1139	1			T12	11		T140	1		T17	24
valid_sources[0x5c]	1222	1			T21	1		T12	18		T17	27
valid_sources[0x5d]	1415	1			T19	1		T11	6		T12	12
valid_sources[0x5e]	1183	1			T32	1		T11	5		T12	13
valid_sources[0x5f]	931	1			T19	1		T30	3		T12	16
valid_sources[0x60]	1529	1			T11	2		T12	6		T138	1
valid_sources[0x61]	767	1			T30	2		T25	1		T12	14
valid_sources[0x62]	675	1			T21	1		T12	10		T34	1
valid_sources[0x63]	1053	1			T19	1		T30	3		T11	7
valid_sources[0x64]	1438	1			T8	1		T21	1		T30	2
valid_sources[0x65]	1645	1			T21	1		T81	1		T72	1
valid_sources[0x66]	1706	1			T21	1		T117	2		T12	17
valid_sources[0x67]	1630	1			T11	16		T12	14		T138	1
valid_sources[0x68]	1170	1			T21	1		T11	37		T12	24
valid_sources[0x69]	818	1			T2	1		T21	1		T11	8
valid_sources[0x6a]	946	1			T14	2		T11	18		T12	16
valid_sources[0x6b]	1426	1			T12	27		T59	1		T17	21
valid_sources[0x6c]	928	1			T9	1		T19	3		T11	10
valid_sources[0x6d]	924	1			T19	2		T30	1		T37	1
valid_sources[0x6e]	1328	1			T11	38		T12	25		T17	22
valid_sources[0x6f]	1114	1			T11	2		T12	19		T27	1
valid_sources[0x70]	981	1			T9	1		T11	1		T12	13
valid_sources[0x71]	759	1			T21	1		T12	15		T138	1
valid_sources[0x72]	1070	1			T21	1		T12	7		T17	29
valid_sources[0x73]	901	1			T21	1		T11	15		T12	10
valid_sources[0x74]	1336	1			T29	1		T19	1		T115	1
valid_sources[0x75]	740	1			T11	17		T12	10		T17	32
valid_sources[0x76]	924	1			T30	4		T11	4		T12	15
valid_sources[0x77]	1043	1			T12	11		T61	1		T34	1
valid_sources[0x78]	1305	1			T32	2		T11	2		T12	13
valid_sources[0x79]	928	1			T21	2		T81	1		T11	5
valid_sources[0x7a]	972	1			T9	2		T117	2		T11	2
valid_sources[0x7b]	994	1			T9	1		T81	2		T11	8
valid_sources[0x7c]	754	1			T11	32		T12	15		T17	18
valid_sources[0x7d]	943	1			T21	1		T33	1		T12	12
valid_sources[0x7e]	1289	1			T21	1		T30	1		T11	4
valid_sources[0x7f]	1082	1			T9	1		T11	8		T12	2
valid_sources[0x80]	1263	1			T9	1		T30	1		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66276

1

T2

8

T3

23

T4

11

values[0x0]

all_enables

biggest_size

95170

1

T1

1

T29

3

T66

1

values[0x1]

all_enables

biggest_size

95184

1

T1

2

T15

2

T72

1