Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 96.89 91.99 97.67 100.00 98.28 98.05 99.06


Total tests in report: 457
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.61 66.61 92.34 92.34 74.72 74.72 60.30 60.30 40.00 40.00 87.93 87.93 93.85 93.85 17.10 17.10 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.59253695
83.54 16.93 96.05 3.71 84.83 10.11 82.30 22.00 53.33 13.33 93.45 5.52 95.65 1.80 79.16 62.06 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3449765190
88.77 5.24 96.05 0.00 86.94 2.11 88.97 6.67 80.00 26.67 93.79 0.34 95.80 0.15 79.86 0.70 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1352632182
91.01 2.23 96.53 0.48 87.64 0.70 93.67 4.70 86.67 6.67 95.86 2.07 96.10 0.30 80.56 0.70 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1123133914
93.10 2.09 96.65 0.12 87.78 0.14 93.67 0.00 100.00 13.33 96.21 0.34 96.10 0.00 81.26 0.70 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2426343448
94.46 1.37 96.65 0.00 87.78 0.00 95.05 1.38 100.00 0.00 96.21 0.00 96.10 0.00 89.46 8.20 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.256723586
95.48 1.02 96.89 0.24 88.48 0.70 95.05 0.00 100.00 0.00 97.24 1.03 96.10 0.00 94.61 5.15 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3246086355
96.05 0.57 96.89 0.00 89.75 1.26 96.62 1.57 100.00 0.00 97.93 0.69 96.10 0.00 95.08 0.47 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3691729739
96.33 0.28 96.89 0.00 90.31 0.56 96.78 0.15 100.00 0.00 97.93 0.00 96.40 0.30 96.02 0.94 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3398352719
96.50 0.17 96.89 0.00 90.45 0.14 96.78 0.00 100.00 0.00 97.93 0.00 97.45 1.05 96.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3346140878
96.67 0.17 96.89 0.00 90.45 0.00 96.78 0.00 100.00 0.00 97.93 0.00 97.45 0.00 97.19 1.17 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1281140052
96.80 0.13 96.89 0.00 90.45 0.00 96.78 0.00 100.00 0.00 97.93 0.00 97.45 0.00 98.13 0.94 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3456452626
96.93 0.13 96.89 0.00 91.01 0.56 97.12 0.35 100.00 0.00 97.93 0.00 97.45 0.00 98.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4103633983
97.04 0.11 96.89 0.00 91.71 0.70 97.17 0.05 100.00 0.00 97.93 0.00 97.45 0.00 98.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1759034686
97.14 0.10 96.89 0.00 91.85 0.14 97.38 0.20 100.00 0.00 98.28 0.34 97.45 0.00 98.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2922057901
97.21 0.07 96.89 0.00 91.85 0.00 97.38 0.00 100.00 0.00 98.28 0.00 97.45 0.00 98.59 0.47 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3912623180
97.26 0.06 96.89 0.00 91.99 0.14 97.47 0.10 100.00 0.00 98.28 0.00 97.60 0.15 98.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2476119215
97.30 0.04 96.89 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.28 0.00 97.90 0.30 98.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2583313318
97.34 0.03 96.89 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.28 0.00 97.90 0.00 98.83 0.23 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.788703501
97.37 0.03 96.89 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.28 0.00 97.90 0.00 99.06 0.23 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2063371556
97.39 0.02 96.89 0.00 91.99 0.00 97.62 0.15 100.00 0.00 98.28 0.00 97.90 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3700917498
97.41 0.02 96.89 0.00 91.99 0.00 97.62 0.00 100.00 0.00 98.28 0.00 98.05 0.15 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.445954391
97.42 0.01 96.89 0.00 91.99 0.00 97.67 0.05 100.00 0.00 98.28 0.00 98.05 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.4015707487

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2098006829
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2712579174
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3475323765
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.596717346
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3384609038
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1205210509
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2000721281
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.294278185
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1560988190
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.57115032
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2708127622
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3918503596
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3002149881
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2384881781
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3544873497
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.707978594
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.676658478
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2319191411
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4111145711
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2513753461
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1978211883
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2079591544
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.313738698
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4224649953
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3303483430
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1737847361
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1932429224
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2970727487
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2241699124
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2160809395
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3257880141
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3995597548
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.111817795
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1570662355
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3910344946
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.162476884
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2471447409
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.788641095
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2666190744
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1829691190
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3949691646
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3182376626
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3260238680
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1332687162
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3328439619
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3166966607
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.369982214
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1102962023
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2757603265
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2324216089
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4235165309
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4172480267
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1897732274
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.254443944
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.894690897
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.408608046
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3844906834
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1565763837
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2743156761
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3176853796
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2730477999
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2911548314
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1950124244
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2166788655
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3207203375
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.176195309
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3006655716
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3300517979
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2083627145
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1667916013
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3418036600
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2187480251
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4225875363
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4118628518
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3651660252
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3942970917
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2582376174
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2690559217
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3795714400
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1821415803
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3397574732
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3780161423
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1522350565
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2399716705
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.910712458
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3359089334
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.307325019
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/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.515528770
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/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.4039030050
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3933636451
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2817498923
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1297429123
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1491374759
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1325273639
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/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1423062214
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/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3409434624
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4153966276
/workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3033874098



Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4103633983 Aug 25 03:25:48 AM UTC 24 Aug 25 03:25:55 AM UTC 24 321610766 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3921813195 Aug 25 03:25:47 AM UTC 24 Aug 25 03:25:56 AM UTC 24 95975076 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.59253695 Aug 25 03:27:40 AM UTC 24 Aug 25 03:28:05 AM UTC 24 1813869456 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.4198259860 Aug 25 03:25:48 AM UTC 24 Aug 25 03:25:58 AM UTC 24 901094673 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1022059327 Aug 25 03:25:48 AM UTC 24 Aug 25 03:25:59 AM UTC 24 752084287 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1931772356 Aug 25 03:25:49 AM UTC 24 Aug 25 03:26:00 AM UTC 24 137217556 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2922057901 Aug 25 03:25:48 AM UTC 24 Aug 25 03:26:02 AM UTC 24 168731766 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2569530294 Aug 25 03:25:56 AM UTC 24 Aug 25 03:26:05 AM UTC 24 253804441 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3089180437 Aug 25 03:25:48 AM UTC 24 Aug 25 03:26:05 AM UTC 24 1508119111 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1123133914 Aug 25 03:25:50 AM UTC 24 Aug 25 03:26:06 AM UTC 24 695729714 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.627124818 Aug 25 03:25:56 AM UTC 24 Aug 25 03:26:07 AM UTC 24 143501437 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1376162979 Aug 25 03:25:59 AM UTC 24 Aug 25 03:26:08 AM UTC 24 342531535 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.4093971340 Aug 25 03:26:06 AM UTC 24 Aug 25 03:26:13 AM UTC 24 519022219 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2476119215 Aug 25 03:25:57 AM UTC 24 Aug 25 03:26:14 AM UTC 24 1637991736 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3879921897 Aug 25 03:26:00 AM UTC 24 Aug 25 03:26:15 AM UTC 24 176565488 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3709964174 Aug 25 03:26:06 AM UTC 24 Aug 25 03:26:16 AM UTC 24 141917451 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1122327403 Aug 25 03:26:07 AM UTC 24 Aug 25 03:26:17 AM UTC 24 270926820 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3691729739 Aug 25 03:25:47 AM UTC 24 Aug 25 03:26:19 AM UTC 24 1743564407 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2936731918 Aug 25 03:26:14 AM UTC 24 Aug 25 03:26:23 AM UTC 24 126432438 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.4015707487 Aug 25 03:26:08 AM UTC 24 Aug 25 03:26:24 AM UTC 24 348183382 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3643891984 Aug 25 03:26:15 AM UTC 24 Aug 25 03:26:26 AM UTC 24 279747837 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1389010244 Aug 25 03:26:17 AM UTC 24 Aug 25 03:26:27 AM UTC 24 489243829 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.867311355 Aug 25 03:26:16 AM UTC 24 Aug 25 03:26:29 AM UTC 24 457658561 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2819718553 Aug 25 03:26:07 AM UTC 24 Aug 25 03:26:33 AM UTC 24 329389072 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2871793331 Aug 25 03:26:20 AM UTC 24 Aug 25 03:26:36 AM UTC 24 348204760 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2202796649 Aug 25 03:26:25 AM UTC 24 Aug 25 03:26:36 AM UTC 24 5481106524 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1297429123 Aug 25 03:26:27 AM UTC 24 Aug 25 03:26:36 AM UTC 24 399519517 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.2817498923 Aug 25 03:26:30 AM UTC 24 Aug 25 03:26:40 AM UTC 24 142134996 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.4039030050 Aug 25 03:26:37 AM UTC 24 Aug 25 03:26:45 AM UTC 24 541305265 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2434361285 Aug 25 03:26:37 AM UTC 24 Aug 25 03:26:48 AM UTC 24 267425141 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1557770337 Aug 25 03:26:41 AM UTC 24 Aug 25 03:26:51 AM UTC 24 366601142 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2875048320 Aug 25 03:26:49 AM UTC 24 Aug 25 03:26:56 AM UTC 24 640836745 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1986038748 Aug 25 03:26:41 AM UTC 24 Aug 25 03:26:58 AM UTC 24 336668769 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.187873946 Aug 25 03:25:51 AM UTC 24 Aug 25 03:27:00 AM UTC 24 273046513 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3933636451 Aug 25 03:26:36 AM UTC 24 Aug 25 03:27:01 AM UTC 24 1001355635 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1729414043 Aug 25 03:26:49 AM UTC 24 Aug 25 03:27:02 AM UTC 24 1051067082 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3498937812 Aug 25 03:26:53 AM UTC 24 Aug 25 03:27:02 AM UTC 24 195776268 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1491374759 Aug 25 03:26:28 AM UTC 24 Aug 25 03:27:03 AM UTC 24 1072267026 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3673655055 Aug 25 03:26:46 AM UTC 24 Aug 25 03:27:04 AM UTC 24 251573579 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3996270538 Aug 25 03:26:59 AM UTC 24 Aug 25 03:27:06 AM UTC 24 552983153 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3449765190 Aug 25 03:26:01 AM UTC 24 Aug 25 03:27:10 AM UTC 24 6292934747 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1423062214 Aug 25 03:27:01 AM UTC 24 Aug 25 03:27:12 AM UTC 24 364378895 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3596307110 Aug 25 03:27:03 AM UTC 24 Aug 25 03:27:12 AM UTC 24 97738529 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.81576096 Aug 25 03:27:06 AM UTC 24 Aug 25 03:27:13 AM UTC 24 136093186 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.256723586 Aug 25 03:25:48 AM UTC 24 Aug 25 03:27:13 AM UTC 24 12323737343 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.612110678 Aug 25 03:26:58 AM UTC 24 Aug 25 03:27:14 AM UTC 24 580442171 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.570250472 Aug 25 03:26:52 AM UTC 24 Aug 25 03:27:19 AM UTC 24 1145145293 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2929835587 Aug 25 03:27:02 AM UTC 24 Aug 25 03:27:21 AM UTC 24 264655509 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3409434624 Aug 25 03:27:11 AM UTC 24 Aug 25 03:27:21 AM UTC 24 100297187 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2849557754 Aug 25 03:27:13 AM UTC 24 Aug 25 03:27:21 AM UTC 24 386963458 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.798301348 Aug 25 03:27:04 AM UTC 24 Aug 25 03:27:22 AM UTC 24 780506743 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.227733673 Aug 25 03:26:10 AM UTC 24 Aug 25 03:27:27 AM UTC 24 782236929 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2455331809 Aug 25 03:27:20 AM UTC 24 Aug 25 03:27:28 AM UTC 24 1385731203 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2349050067 Aug 25 03:27:15 AM UTC 24 Aug 25 03:27:28 AM UTC 24 173234856 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1488174610 Aug 25 03:26:03 AM UTC 24 Aug 25 03:27:31 AM UTC 24 621679412 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3188095648 Aug 25 03:27:22 AM UTC 24 Aug 25 03:27:31 AM UTC 24 196330512 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4153966276 Aug 25 03:27:13 AM UTC 24 Aug 25 03:27:33 AM UTC 24 263946070 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.1517404395 Aug 25 03:27:29 AM UTC 24 Aug 25 03:27:38 AM UTC 24 262065752 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3127964158 Aug 25 03:27:29 AM UTC 24 Aug 25 03:27:39 AM UTC 24 528291604 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.722532196 Aug 25 03:27:23 AM UTC 24 Aug 25 03:27:40 AM UTC 24 252535454 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.2217273715 Aug 25 03:27:29 AM UTC 24 Aug 25 03:27:46 AM UTC 24 288646893 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.4242335707 Aug 25 03:27:39 AM UTC 24 Aug 25 03:27:46 AM UTC 24 85774387 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.3397454404 Aug 25 03:27:32 AM UTC 24 Aug 25 03:27:50 AM UTC 24 302736606 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.652211109 Aug 25 03:27:22 AM UTC 24 Aug 25 03:27:51 AM UTC 24 429930139 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3911701799 Aug 25 03:27:41 AM UTC 24 Aug 25 03:27:52 AM UTC 24 143519640 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.599522865 Aug 25 03:25:48 AM UTC 24 Aug 25 03:27:53 AM UTC 24 1471056147 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1352632182 Aug 25 03:26:19 AM UTC 24 Aug 25 03:27:57 AM UTC 24 2250118277 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.4183184508 Aug 25 03:27:52 AM UTC 24 Aug 25 03:28:04 AM UTC 24 2259630347 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1864571662 Aug 25 03:27:47 AM UTC 24 Aug 25 03:28:04 AM UTC 24 1001789740 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.828515723 Aug 25 03:25:49 AM UTC 24 Aug 25 03:28:05 AM UTC 24 6380142515 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1510230729 Aug 25 03:27:54 AM UTC 24 Aug 25 03:28:05 AM UTC 24 603367296 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.862504680 Aug 25 03:28:05 AM UTC 24 Aug 25 03:28:13 AM UTC 24 89185523 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4226803567 Aug 25 03:26:00 AM UTC 24 Aug 25 03:28:14 AM UTC 24 4898157915 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1136415294 Aug 25 03:27:53 AM UTC 24 Aug 25 03:28:15 AM UTC 24 1171884919 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1374514053 Aug 25 03:28:07 AM UTC 24 Aug 25 03:28:16 AM UTC 24 924327039 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2591865438 Aug 25 03:28:04 AM UTC 24 Aug 25 03:28:22 AM UTC 24 2076258324 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.684388734 Aug 25 03:26:49 AM UTC 24 Aug 25 03:28:24 AM UTC 24 4866222908 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.748357645 Aug 25 03:28:16 AM UTC 24 Aug 25 03:28:24 AM UTC 24 497080208 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.1067924158 Aug 25 03:28:06 AM UTC 24 Aug 25 03:28:27 AM UTC 24 287101853 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1180754661 Aug 25 03:28:14 AM UTC 24 Aug 25 03:28:30 AM UTC 24 335741901 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.12782968 Aug 25 03:28:17 AM UTC 24 Aug 25 03:28:30 AM UTC 24 119266721 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.3398352719 Aug 25 03:25:48 AM UTC 24 Aug 25 03:28:30 AM UTC 24 2508477763 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.288920353 Aug 25 03:28:23 AM UTC 24 Aug 25 03:28:31 AM UTC 24 143452655 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3246958623 Aug 25 03:28:28 AM UTC 24 Aug 25 03:28:36 AM UTC 24 349711021 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1689956549 Aug 25 03:26:24 AM UTC 24 Aug 25 03:28:39 AM UTC 24 3036856382 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3895963712 Aug 25 03:28:30 AM UTC 24 Aug 25 03:28:40 AM UTC 24 96087864 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.67412830 Aug 25 03:28:25 AM UTC 24 Aug 25 03:28:42 AM UTC 24 1039974273 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1325273639 Aug 25 03:26:37 AM UTC 24 Aug 25 03:28:44 AM UTC 24 5921232778 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1252970389 Aug 25 03:28:37 AM UTC 24 Aug 25 03:28:45 AM UTC 24 127756865 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.447395140 Aug 25 03:26:07 AM UTC 24 Aug 25 03:28:47 AM UTC 24 1674668268 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1945746713 Aug 25 03:28:31 AM UTC 24 Aug 25 03:28:49 AM UTC 24 258576911 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2808789147 Aug 25 03:28:41 AM UTC 24 Aug 25 03:28:51 AM UTC 24 267538086 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1142313226 Aug 25 03:28:30 AM UTC 24 Aug 25 03:28:53 AM UTC 24 431810312 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2922772365 Aug 25 03:28:46 AM UTC 24 Aug 25 03:28:54 AM UTC 24 1038256006 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3066378985 Aug 25 03:26:09 AM UTC 24 Aug 25 03:28:57 AM UTC 24 15402645612 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3084104629 Aug 25 03:28:47 AM UTC 24 Aug 25 03:28:57 AM UTC 24 784299835 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3714134761 Aug 25 03:28:45 AM UTC 24 Aug 25 03:29:00 AM UTC 24 343515099 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.387247494 Aug 25 03:26:24 AM UTC 24 Aug 25 03:29:00 AM UTC 24 944039493 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1752413852 Aug 25 03:28:53 AM UTC 24 Aug 25 03:29:02 AM UTC 24 126331322 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2781131905 Aug 25 03:28:40 AM UTC 24 Aug 25 03:29:02 AM UTC 24 220403584 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3781302388 Aug 25 03:28:50 AM UTC 24 Aug 25 03:29:06 AM UTC 24 921777545 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2711448106 Aug 25 03:28:55 AM UTC 24 Aug 25 03:29:06 AM UTC 24 560547886 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1604454638 Aug 25 03:28:47 AM UTC 24 Aug 25 03:29:08 AM UTC 24 218466278 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.4072752016 Aug 25 03:29:01 AM UTC 24 Aug 25 03:29:09 AM UTC 24 158409134 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.902921544 Aug 25 03:27:14 AM UTC 24 Aug 25 03:29:10 AM UTC 24 6584039404 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1829946715 Aug 25 03:29:03 AM UTC 24 Aug 25 03:29:14 AM UTC 24 139225447 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3880258225 Aug 25 03:29:10 AM UTC 24 Aug 25 03:29:17 AM UTC 24 399262827 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3304503792 Aug 25 03:27:05 AM UTC 24 Aug 25 03:29:18 AM UTC 24 8577240629 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1120265238 Aug 25 03:27:03 AM UTC 24 Aug 25 03:29:19 AM UTC 24 3658937261 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.1992199217 Aug 25 03:28:55 AM UTC 24 Aug 25 03:29:19 AM UTC 24 293383133 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1064134976 Aug 25 03:28:57 AM UTC 24 Aug 25 03:29:21 AM UTC 24 2008134702 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1305233046 Aug 25 03:27:28 AM UTC 24 Aug 25 03:29:23 AM UTC 24 2307477155 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3553868353 Aug 25 03:29:07 AM UTC 24 Aug 25 03:29:23 AM UTC 24 2384144394 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.280273200 Aug 25 03:29:11 AM UTC 24 Aug 25 03:29:24 AM UTC 24 116704511 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2293111403 Aug 25 03:29:15 AM UTC 24 Aug 25 03:29:26 AM UTC 24 270223191 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3674870008 Aug 25 03:29:20 AM UTC 24 Aug 25 03:29:29 AM UTC 24 95120932 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.22367891 Aug 25 03:26:42 AM UTC 24 Aug 25 03:29:30 AM UTC 24 2288141984 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3909524637 Aug 25 03:29:25 AM UTC 24 Aug 25 03:29:32 AM UTC 24 88862228 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.376317656 Aug 25 03:29:20 AM UTC 24 Aug 25 03:29:33 AM UTC 24 525387041 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.531560019 Aug 25 03:29:03 AM UTC 24 Aug 25 03:29:35 AM UTC 24 572370590 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.4017938952 Aug 25 03:29:18 AM UTC 24 Aug 25 03:29:37 AM UTC 24 481154465 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.335097044 Aug 25 03:29:29 AM UTC 24 Aug 25 03:29:39 AM UTC 24 281201158 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4048654345 Aug 25 03:26:59 AM UTC 24 Aug 25 03:29:41 AM UTC 24 11671355809 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1618282380 Aug 25 03:29:24 AM UTC 24 Aug 25 03:29:41 AM UTC 24 250169612 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3906177816 Aug 25 03:29:33 AM UTC 24 Aug 25 03:29:41 AM UTC 24 126949624 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3033874098 Aug 25 03:27:15 AM UTC 24 Aug 25 03:29:44 AM UTC 24 6633691222 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.373077524 Aug 25 03:27:51 AM UTC 24 Aug 25 03:29:46 AM UTC 24 14266603477 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.735838545 Aug 25 03:27:31 AM UTC 24 Aug 25 03:29:46 AM UTC 24 2714719547 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.228528956 Aug 25 03:29:32 AM UTC 24 Aug 25 03:29:48 AM UTC 24 666532771 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2054632580 Aug 25 03:30:06 AM UTC 24 Aug 25 03:30:16 AM UTC 24 138352767 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3850934114 Aug 25 03:27:47 AM UTC 24 Aug 25 03:29:48 AM UTC 24 5671715613 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1563845670 Aug 25 03:30:00 AM UTC 24 Aug 25 03:30:18 AM UTC 24 521405859 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1759034686 Aug 25 03:26:34 AM UTC 24 Aug 25 03:29:48 AM UTC 24 2806573405 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.4259080734 Aug 25 03:29:20 AM UTC 24 Aug 25 03:29:49 AM UTC 24 3037260658 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3232904663 Aug 25 03:29:43 AM UTC 24 Aug 25 03:29:50 AM UTC 24 348905217 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.4031832497 Aug 25 03:29:36 AM UTC 24 Aug 25 03:29:50 AM UTC 24 523710170 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3853659745 Aug 25 03:29:08 AM UTC 24 Aug 25 03:29:55 AM UTC 24 5890303489 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.629222870 Aug 25 03:29:46 AM UTC 24 Aug 25 03:29:55 AM UTC 24 201062018 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.725891715 Aug 25 03:29:35 AM UTC 24 Aug 25 03:29:56 AM UTC 24 228115781 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3321547488 Aug 25 03:29:39 AM UTC 24 Aug 25 03:29:57 AM UTC 24 995665190 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2296610911 Aug 25 03:29:49 AM UTC 24 Aug 25 03:29:57 AM UTC 24 128403680 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1724119417 Aug 25 03:29:50 AM UTC 24 Aug 25 03:30:00 AM UTC 24 694523454 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2472989257 Aug 25 03:29:56 AM UTC 24 Aug 25 03:30:03 AM UTC 24 312277662 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2654610209 Aug 25 03:27:22 AM UTC 24 Aug 25 03:30:03 AM UTC 24 2123585169 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1015463568 Aug 25 03:29:47 AM UTC 24 Aug 25 03:30:04 AM UTC 24 709821688 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3035690266 Aug 25 03:29:43 AM UTC 24 Aug 25 03:30:05 AM UTC 24 208385866 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.170377720 Aug 25 03:28:08 AM UTC 24 Aug 25 03:30:05 AM UTC 24 4862668173 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2396629822 Aug 25 03:29:51 AM UTC 24 Aug 25 03:30:06 AM UTC 24 330818023 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2426343448 Aug 25 03:26:57 AM UTC 24 Aug 25 03:30:07 AM UTC 24 2176638143 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.1882944416 Aug 25 03:29:57 AM UTC 24 Aug 25 03:30:07 AM UTC 24 136344211 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3700917498 Aug 25 03:28:05 AM UTC 24 Aug 25 03:30:08 AM UTC 24 19764922544 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3905740578 Aug 25 03:28:31 AM UTC 24 Aug 25 03:30:09 AM UTC 24 2870173419 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3625921274 Aug 25 03:25:50 AM UTC 24 Aug 25 03:30:09 AM UTC 24 15824227856 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.192100585 Aug 25 03:29:49 AM UTC 24 Aug 25 03:30:10 AM UTC 24 2745280906 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.237353389 Aug 25 03:29:27 AM UTC 24 Aug 25 03:30:10 AM UTC 24 2735505370 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3412929480 Aug 25 03:30:05 AM UTC 24 Aug 25 03:30:12 AM UTC 24 89131667 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3404014269 Aug 25 03:30:08 AM UTC 24 Aug 25 03:30:15 AM UTC 24 90183960 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2418645094 Aug 25 03:30:09 AM UTC 24 Aug 25 03:30:19 AM UTC 24 139049060 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.4032573610 Aug 25 03:30:12 AM UTC 24 Aug 25 03:30:21 AM UTC 24 132486437 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3839975593 Aug 25 03:30:07 AM UTC 24 Aug 25 03:30:24 AM UTC 24 1460140654 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.445954391 Aug 25 03:30:16 AM UTC 24 Aug 25 03:30:26 AM UTC 24 192774024 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.750498656 Aug 25 03:30:11 AM UTC 24 Aug 25 03:30:27 AM UTC 24 174122398 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2376285347 Aug 25 03:30:22 AM UTC 24 Aug 25 03:30:29 AM UTC 24 347785862 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2915048487 Aug 25 03:28:50 AM UTC 24 Aug 25 03:30:32 AM UTC 24 4593861069 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2006996592 Aug 25 03:29:57 AM UTC 24 Aug 25 03:30:33 AM UTC 24 525771338 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3195517637 Aug 25 03:30:18 AM UTC 24 Aug 25 03:30:34 AM UTC 24 175705178 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3106186327 Aug 25 03:30:06 AM UTC 24 Aug 25 03:30:35 AM UTC 24 410118216 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.17151475 Aug 25 03:30:28 AM UTC 24 Aug 25 03:30:37 AM UTC 24 558234961 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.3307076263 Aug 25 03:30:09 AM UTC 24 Aug 25 03:30:38 AM UTC 24 827204831 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.974368158 Aug 25 03:30:16 AM UTC 24 Aug 25 03:30:38 AM UTC 24 306799081 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.4090908535 Aug 25 03:30:33 AM UTC 24 Aug 25 03:30:41 AM UTC 24 381533856 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2271465689 Aug 25 03:28:16 AM UTC 24 Aug 25 03:30:42 AM UTC 24 2517229659 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2846426331 Aug 25 03:30:34 AM UTC 24 Aug 25 03:30:43 AM UTC 24 339905162 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.727205269 Aug 25 03:30:25 AM UTC 24 Aug 25 03:30:46 AM UTC 24 192735251 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.136488123 Aug 25 03:30:39 AM UTC 24 Aug 25 03:30:47 AM UTC 24 159438136 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.1637103991 Aug 25 03:30:34 AM UTC 24 Aug 25 03:30:51 AM UTC 24 998821508 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2283540492 Aug 25 03:30:35 AM UTC 24 Aug 25 03:30:51 AM UTC 24 329151147 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.65140944 Aug 25 03:30:42 AM UTC 24 Aug 25 03:30:51 AM UTC 24 98014473 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.1412104189 Aug 25 03:30:29 AM UTC 24 Aug 25 03:30:54 AM UTC 24 1029815139 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1097123320 Aug 25 03:29:49 AM UTC 24 Aug 25 03:30:56 AM UTC 24 868827610 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3496531138 Aug 25 03:30:48 AM UTC 24 Aug 25 03:30:56 AM UTC 24 500422272 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.1956183536 Aug 25 03:30:52 AM UTC 24 Aug 25 03:31:00 AM UTC 24 183600554 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.4230257153 Aug 25 03:30:44 AM UTC 24 Aug 25 03:31:01 AM UTC 24 261757420 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.121451017 Aug 25 03:30:57 AM UTC 24 Aug 25 03:31:05 AM UTC 24 182455692 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3745568580 Aug 25 03:30:39 AM UTC 24 Aug 25 03:31:06 AM UTC 24 296407707 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.660054427 Aug 25 03:27:58 AM UTC 24 Aug 25 03:31:08 AM UTC 24 4679600973 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.3565406233 Aug 25 03:30:52 AM UTC 24 Aug 25 03:31:10 AM UTC 24 921507676 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3081798136 Aug 25 03:31:01 AM UTC 24 Aug 25 03:31:10 AM UTC 24 99763106 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2083823635 Aug 25 03:30:49 AM UTC 24 Aug 25 03:31:14 AM UTC 24 218364529 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.947962038 Aug 25 03:29:07 AM UTC 24 Aug 25 03:31:17 AM UTC 24 1449443127 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3426445215 Aug 25 03:31:10 AM UTC 24 Aug 25 03:31:18 AM UTC 24 1770884440 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.467685500 Aug 25 03:28:23 AM UTC 24 Aug 25 03:31:19 AM UTC 24 9631884677 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1691090322 Aug 25 03:31:11 AM UTC 24 Aug 25 03:31:19 AM UTC 24 345921848 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1065425602 Aug 25 03:30:57 AM UTC 24 Aug 25 03:31:19 AM UTC 24 203532852 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.158856725 Aug 25 03:30:08 AM UTC 24 Aug 25 03:31:20 AM UTC 24 1364878926 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2821542433 Aug 25 03:31:05 AM UTC 24 Aug 25 03:31:22 AM UTC 24 255219113 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.721548586 Aug 25 03:28:34 AM UTC 24 Aug 25 03:31:26 AM UTC 24 1721154603 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3870024885 Aug 25 03:31:19 AM UTC 24 Aug 25 03:31:26 AM UTC 24 336524629 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3577141527 Aug 25 03:31:15 AM UTC 24 Aug 25 03:31:27 AM UTC 24 364139597 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.1829241841 Aug 25 03:31:20 AM UTC 24 Aug 25 03:31:30 AM UTC 24 430314170 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2623171017 Aug 25 03:29:01 AM UTC 24 Aug 25 03:31:30 AM UTC 24 9258087958 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3317496199 Aug 25 03:31:20 AM UTC 24 Aug 25 03:31:31 AM UTC 24 557758843 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2417859106 Aug 25 03:31:11 AM UTC 24 Aug 25 03:31:31 AM UTC 24 1204040109 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.4111526483 Aug 25 03:31:23 AM UTC 24 Aug 25 03:31:32 AM UTC 24 521793665 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2513882217 Aug 25 03:28:45 AM UTC 24 Aug 25 03:31:34 AM UTC 24 7283694092 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2341638503 Aug 25 03:31:26 AM UTC 24 Aug 25 03:31:37 AM UTC 24 462338813 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3000829437 Aug 25 03:31:21 AM UTC 24 Aug 25 03:31:38 AM UTC 24 2763670219 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3741429003 Aug 25 03:31:17 AM UTC 24 Aug 25 03:31:39 AM UTC 24 1638174669 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1164831685 Aug 25 03:31:32 AM UTC 24 Aug 25 03:31:40 AM UTC 24 131212682 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2355287679 Aug 25 03:31:26 AM UTC 24 Aug 25 03:31:42 AM UTC 24 308058913 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1145383244 Aug 25 03:31:32 AM UTC 24 Aug 25 03:31:42 AM UTC 24 541235254 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.189909637 Aug 25 03:31:29 AM UTC 24 Aug 25 03:31:44 AM UTC 24 348753585 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1881502408 Aug 25 03:29:23 AM UTC 24 Aug 25 03:31:45 AM UTC 24 6463799036 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.391138060 Aug 25 03:31:38 AM UTC 24 Aug 25 03:31:46 AM UTC 24 498663931 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3757418914 Aug 25 03:27:34 AM UTC 24 Aug 25 03:31:48 AM UTC 24 5589366759 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3689792769 Aug 25 03:31:32 AM UTC 24 Aug 25 03:31:48 AM UTC 24 131480482 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2521204267 Aug 25 03:31:35 AM UTC 24 Aug 25 03:31:50 AM UTC 24 350802373 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3123870898 Aug 25 03:31:40 AM UTC 24 Aug 25 03:31:53 AM UTC 24 797307916 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2136696984 Aug 25 03:31:41 AM UTC 24 Aug 25 03:31:56 AM UTC 24 2107744649 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.2099324798 Aug 25 03:31:44 AM UTC 24 Aug 25 03:31:56 AM UTC 24 2129511213 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.353839963 Aug 25 03:28:57 AM UTC 24 Aug 25 03:31:57 AM UTC 24 5324017658 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.3693079845 Aug 25 03:31:48 AM UTC 24 Aug 25 03:31:58 AM UTC 24 135236993 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2335047732 Aug 25 03:29:33 AM UTC 24 Aug 25 03:31:59 AM UTC 24 26246526014 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.3860450574 Aug 25 03:31:43 AM UTC 24 Aug 25 03:31:59 AM UTC 24 171860686 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.711965486 Aug 25 03:29:58 AM UTC 24 Aug 25 03:32:00 AM UTC 24 8727478232 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.279631038 Aug 25 03:29:41 AM UTC 24 Aug 25 03:32:01 AM UTC 24 3843778136 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3083534159 Aug 25 03:31:54 AM UTC 24 Aug 25 03:32:02 AM UTC 24 127386011 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2362101816 Aug 25 03:31:47 AM UTC 24 Aug 25 03:32:03 AM UTC 24 161271586 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.994701171 Aug 25 03:31:49 AM UTC 24 Aug 25 03:32:04 AM UTC 24 348064704 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.218138128 Aug 25 03:31:57 AM UTC 24 Aug 25 03:32:07 AM UTC 24 552128910 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3813917339 Aug 25 03:29:51 AM UTC 24 Aug 25 03:32:08 AM UTC 24 1966435201 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.475593607 Aug 25 03:32:00 AM UTC 24 Aug 25 03:32:08 AM UTC 24 241333308 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2066477907 Aug 25 03:29:37 AM UTC 24 Aug 25 03:32:11 AM UTC 24 7031224964 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.4176347942 Aug 25 03:32:02 AM UTC 24 Aug 25 03:32:12 AM UTC 24 189233233 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.4001095273 Aug 25 03:32:08 AM UTC 24 Aug 25 03:32:16 AM UTC 24 516285311 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.2331434102 Aug 25 03:31:59 AM UTC 24 Aug 25 03:32:18 AM UTC 24 1033989062 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3675301994 Aug 25 03:32:09 AM UTC 24 Aug 25 03:32:19 AM UTC 24 102749127 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.242738251 Aug 25 03:30:16 AM UTC 24 Aug 25 03:32:20 AM UTC 24 3334794819 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1957881034 Aug 25 03:32:04 AM UTC 24 Aug 25 03:32:21 AM UTC 24 498698988 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4050658699 Aug 25 03:29:15 AM UTC 24 Aug 25 03:32:22 AM UTC 24 9444512089 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.255180906 Aug 25 03:30:21 AM UTC 24 Aug 25 03:32:23 AM UTC 24 7425145759 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2938939242 Aug 25 03:29:24 AM UTC 24 Aug 25 03:32:26 AM UTC 24 14555401895 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2007742590 Aug 25 03:32:18 AM UTC 24 Aug 25 03:32:26 AM UTC 24 255621389 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.3870917982 Aug 25 03:31:57 AM UTC 24 Aug 25 03:32:27 AM UTC 24 777253570 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.106149555 Aug 25 03:32:09 AM UTC 24 Aug 25 03:32:30 AM UTC 24 811891038 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.4220088792 Aug 25 03:32:13 AM UTC 24 Aug 25 03:32:30 AM UTC 24 997670324 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3173795601 Aug 25 03:32:20 AM UTC 24 Aug 25 03:32:31 AM UTC 24 140551441 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2649769635 Aug 25 03:32:26 AM UTC 24 Aug 25 03:32:35 AM UTC 24 133422953 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2760806845 Aug 25 03:32:28 AM UTC 24 Aug 25 03:32:37 AM UTC 24 359900265 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2969126647 Aug 25 03:29:47 AM UTC 24 Aug 25 03:32:38 AM UTC 24 12408345373 ps
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