| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.43 | 96.89 | 91.99 | 97.67 | 100.00 | 98.28 | 97.90 | 99.30 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 67.08 | 67.08 | 92.58 | 92.58 | 71.49 | 71.49 | 66.22 | 66.22 | 40.00 | 40.00 | 88.62 | 88.62 | 94.00 | 94.00 | 16.63 | 16.63 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2129627068 |
| 82.19 | 15.11 | 95.93 | 3.35 | 83.29 | 11.80 | 83.12 | 16.90 | 40.00 | 0.00 | 91.72 | 3.10 | 95.80 | 1.80 | 85.48 | 68.85 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4089840784 |
| 92.58 | 10.39 | 96.53 | 0.60 | 86.52 | 3.23 | 95.03 | 11.90 | 93.33 | 53.33 | 94.48 | 2.76 | 96.25 | 0.45 | 85.95 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.643002922 |
| 93.93 | 1.34 | 96.65 | 0.12 | 87.64 | 1.12 | 95.03 | 0.00 | 100.00 | 6.67 | 95.52 | 1.03 | 96.25 | 0.00 | 86.42 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3459382770 |
| 94.95 | 1.02 | 96.89 | 0.24 | 88.34 | 0.70 | 95.03 | 0.00 | 100.00 | 0.00 | 96.55 | 1.03 | 96.25 | 0.00 | 91.57 | 5.15 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2014634391 |
| 95.60 | 0.66 | 96.89 | 0.00 | 89.19 | 0.84 | 96.55 | 1.52 | 100.00 | 0.00 | 96.90 | 0.34 | 96.25 | 0.00 | 93.44 | 1.87 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4155484821 |
| 96.11 | 0.51 | 96.89 | 0.00 | 90.45 | 1.26 | 97.00 | 0.45 | 100.00 | 0.00 | 97.59 | 0.69 | 96.25 | 0.00 | 94.61 | 1.17 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3360725163 |
| 96.40 | 0.28 | 96.89 | 0.00 | 91.15 | 0.70 | 97.05 | 0.05 | 100.00 | 0.00 | 97.59 | 0.00 | 96.55 | 0.30 | 95.55 | 0.94 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.340654600 |
| 96.60 | 0.20 | 96.89 | 0.00 | 91.15 | 0.00 | 97.05 | 0.00 | 100.00 | 0.00 | 97.59 | 0.00 | 96.55 | 0.00 | 96.96 | 1.41 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.83792367 |
| 96.76 | 0.16 | 96.89 | 0.00 | 91.15 | 0.00 | 97.05 | 0.00 | 100.00 | 0.00 | 97.59 | 0.00 | 97.45 | 0.90 | 97.19 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3709236123 |
| 96.91 | 0.15 | 96.89 | 0.00 | 91.29 | 0.14 | 97.40 | 0.35 | 100.00 | 0.00 | 97.93 | 0.34 | 97.45 | 0.00 | 97.42 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1820499107 |
| 97.02 | 0.11 | 96.89 | 0.00 | 91.71 | 0.42 | 97.53 | 0.12 | 100.00 | 0.00 | 97.93 | 0.00 | 97.45 | 0.00 | 97.66 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3113782718 |
| 97.12 | 0.10 | 96.89 | 0.00 | 91.71 | 0.00 | 97.53 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 97.45 | 0.00 | 98.36 | 0.70 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1839986851 |
| 97.20 | 0.08 | 96.89 | 0.00 | 91.85 | 0.14 | 97.60 | 0.07 | 100.00 | 0.00 | 98.28 | 0.34 | 97.45 | 0.00 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1144178681 |
| 97.27 | 0.07 | 96.89 | 0.00 | 91.85 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.45 | 0.00 | 98.83 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2578506956 |
| 97.33 | 0.06 | 96.89 | 0.00 | 91.99 | 0.14 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.30 | 98.83 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.39611001 |
| 97.37 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3375904104 |
| 97.40 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 99.30 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1391419932 |
| 97.42 | 0.02 | 96.89 | 0.00 | 91.99 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.15 | 99.30 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1835196635 |
| 97.43 | 0.01 | 96.89 | 0.00 | 91.99 | 0.00 | 97.67 | 0.07 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.00 | 99.30 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3913382047 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1431830095 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1006611846 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.40331867 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.120367697 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.372937796 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4035935930 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2339210186 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3381863771 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1761627958 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2667809164 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1000006492 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1249420853 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3896868421 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2643277774 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2546805558 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3237957258 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2964803614 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.46796227 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3215156858 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2213117236 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3711205014 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1340871917 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4275732156 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2085797633 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1393991594 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2778599091 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1204211743 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1511749331 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.93413159 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.557465800 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1546373716 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1614175239 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.201819352 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1856296122 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.595289125 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2074407690 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.160869884 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2561204554 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3441062297 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3737099469 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2650077838 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2687735322 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1628629800 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.205000696 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3644364454 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1573227550 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.130907922 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2678017421 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3770057957 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1620507803 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1025109665 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3657233574 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3537180122 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1827857172 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.499776853 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3962986872 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3109394410 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2182127209 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3743576777 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.566077812 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3942210667 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4206479355 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3710555338 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2528380622 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.710430312 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3888612281 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3408764228 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1716086703 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2522841309 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3703205036 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1849860128 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.701483849 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1620742708 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3867869377 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3799386644 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3417032864 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2325238376 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.720144583 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2795091780 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.988246366 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.964457134 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1403735192 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3581458846 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.414612733 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.357008761 |
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| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3149585397 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.4003658689 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.56252833 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3808751994 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1804136246 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2867619090 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3920846855 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.37074154 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.4107143039 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1885283186 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1677351216 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3908920306 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1705665836 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.125450657 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3702130093 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1695079098 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.652241504 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1496255697 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2244280479 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1941093285 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.556380781 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3157395109 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1447768024 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.574291122 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3241959904 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3145657760 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.19872415 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.3532538148 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4278870805 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3974198202 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.849354903 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.377301359 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4087308303 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1304271674 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1248439108 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3223748300 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2607402736 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.434826603 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3009585520 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3580041749 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2855009897 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1550478019 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3508765068 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.808623668 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.909202726 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3162641517 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.825753185 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3392700810 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1648088468 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2481171004 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1896349772 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3394018001 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.35626695 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1376760045 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.238572887 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2849730480 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1978691095 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1014840767 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3600538785 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1977125205 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.54294475 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.220895378 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.369352510 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1287045176 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3421959109 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2971744464 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3502944508 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.466120337 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3686131215 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3124396841 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.4025124066 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3572551467 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.384346379 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1585326220 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1597059479 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1025036691 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1065309548 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1116118923 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3460125849 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1745994698 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1448381403 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2452939954 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.151893457 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2275606307 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.542460115 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.4288624837 | Aug 27 06:42:55 AM UTC 24 | Aug 27 06:43:05 AM UTC 24 | 277637567 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1863634407 | Aug 27 06:42:57 AM UTC 24 | Aug 27 06:43:15 AM UTC 24 | 504396787 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3913382047 | Aug 27 06:43:06 AM UTC 24 | Aug 27 06:43:15 AM UTC 24 | 190358428 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1144178681 | Aug 27 06:43:16 AM UTC 24 | Aug 27 06:43:26 AM UTC 24 | 175626106 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4155484821 | Aug 27 06:43:26 AM UTC 24 | Aug 27 06:43:34 AM UTC 24 | 126806029 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2589557280 | Aug 27 06:43:26 AM UTC 24 | Aug 27 06:43:35 AM UTC 24 | 183384453 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2007096362 | Aug 27 06:43:29 AM UTC 24 | Aug 27 06:43:40 AM UTC 24 | 498776444 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2129627068 | Aug 27 06:43:27 AM UTC 24 | Aug 27 06:43:47 AM UTC 24 | 613502803 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3963819587 | Aug 27 06:43:36 AM UTC 24 | Aug 27 06:43:54 AM UTC 24 | 1040982918 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.737224951 | Aug 27 06:43:49 AM UTC 24 | Aug 27 06:43:54 AM UTC 24 | 499105776 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.832319674 | Aug 27 06:43:55 AM UTC 24 | Aug 27 06:44:05 AM UTC 24 | 423354548 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3113782718 | Aug 27 06:43:55 AM UTC 24 | Aug 27 06:44:09 AM UTC 24 | 533637999 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3537345662 | Aug 27 06:43:55 AM UTC 24 | Aug 27 06:44:13 AM UTC 24 | 558263417 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1611327507 | Aug 27 06:44:08 AM UTC 24 | Aug 27 06:44:15 AM UTC 24 | 100610510 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.143277517 | Aug 27 06:44:09 AM UTC 24 | Aug 27 06:44:19 AM UTC 24 | 302360398 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1820499107 | Aug 27 06:43:57 AM UTC 24 | Aug 27 06:44:22 AM UTC 24 | 4455404088 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.789245848 | Aug 27 06:44:13 AM UTC 24 | Aug 27 06:44:26 AM UTC 24 | 128838943 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3740738420 | Aug 27 06:44:16 AM UTC 24 | Aug 27 06:44:26 AM UTC 24 | 373378896 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1640814828 | Aug 27 06:44:27 AM UTC 24 | Aug 27 06:44:35 AM UTC 24 | 131430218 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1849528135 | Aug 27 06:44:27 AM UTC 24 | Aug 27 06:44:36 AM UTC 24 | 1023527237 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.3288582616 | Aug 27 06:44:19 AM UTC 24 | Aug 27 06:44:37 AM UTC 24 | 263263974 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3391779761 | Aug 27 06:43:40 AM UTC 24 | Aug 27 06:44:44 AM UTC 24 | 5929783898 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1702042737 | Aug 27 06:44:30 AM UTC 24 | Aug 27 06:44:46 AM UTC 24 | 644034886 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1542639393 | Aug 27 06:44:36 AM UTC 24 | Aug 27 06:44:46 AM UTC 24 | 1876381924 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.3697600783 | Aug 27 06:44:46 AM UTC 24 | Aug 27 06:44:53 AM UTC 24 | 320879562 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.119483133 | Aug 27 06:44:38 AM UTC 24 | Aug 27 06:44:54 AM UTC 24 | 174327980 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2849730480 | Aug 27 06:44:47 AM UTC 24 | Aug 27 06:44:58 AM UTC 24 | 280975222 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.238572887 | Aug 27 06:44:54 AM UTC 24 | Aug 27 06:45:04 AM UTC 24 | 187956509 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1978691095 | Aug 27 06:44:54 AM UTC 24 | Aug 27 06:45:14 AM UTC 24 | 1225488520 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.340654600 | Aug 27 06:44:24 AM UTC 24 | Aug 27 06:45:17 AM UTC 24 | 247450353 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.643002922 | Aug 27 06:43:16 AM UTC 24 | Aug 27 06:45:18 AM UTC 24 | 9241698357 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1376760045 | Aug 27 06:45:05 AM UTC 24 | Aug 27 06:45:20 AM UTC 24 | 169909750 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3394018001 | Aug 27 06:45:18 AM UTC 24 | Aug 27 06:45:26 AM UTC 24 | 464478134 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.369352510 | Aug 27 06:45:19 AM UTC 24 | Aug 27 06:45:27 AM UTC 24 | 136000289 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.220895378 | Aug 27 06:45:21 AM UTC 24 | Aug 27 06:45:30 AM UTC 24 | 95031968 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4089840784 | Aug 27 06:44:03 AM UTC 24 | Aug 27 06:45:31 AM UTC 24 | 2618516508 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1685829335 | Aug 27 06:43:47 AM UTC 24 | Aug 27 06:45:32 AM UTC 24 | 289097462 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3600538785 | Aug 27 06:45:30 AM UTC 24 | Aug 27 06:45:39 AM UTC 24 | 143563773 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3124396841 | Aug 27 06:45:32 AM UTC 24 | Aug 27 06:45:42 AM UTC 24 | 137374840 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1287045176 | Aug 27 06:45:21 AM UTC 24 | Aug 27 06:45:43 AM UTC 24 | 300888432 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1151179804 | Aug 27 06:43:56 AM UTC 24 | Aug 27 06:45:44 AM UTC 24 | 3435983596 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.54294475 | Aug 27 06:45:28 AM UTC 24 | Aug 27 06:45:44 AM UTC 24 | 355218318 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2764393878 | Aug 27 06:43:26 AM UTC 24 | Aug 27 06:45:47 AM UTC 24 | 2760757879 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3686131215 | Aug 27 06:45:38 AM UTC 24 | Aug 27 06:45:47 AM UTC 24 | 400363809 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2184276574 | Aug 27 06:44:44 AM UTC 24 | Aug 27 06:45:52 AM UTC 24 | 190632368 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2971744464 | Aug 27 06:45:45 AM UTC 24 | Aug 27 06:45:53 AM UTC 24 | 126521914 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1025036691 | Aug 27 06:45:45 AM UTC 24 | Aug 27 06:45:53 AM UTC 24 | 219373869 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.4025124066 | Aug 27 06:45:33 AM UTC 24 | Aug 27 06:45:54 AM UTC 24 | 212052386 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.466120337 | Aug 27 06:45:44 AM UTC 24 | Aug 27 06:45:55 AM UTC 24 | 176289664 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1065309548 | Aug 27 06:45:48 AM UTC 24 | Aug 27 06:45:56 AM UTC 24 | 162786595 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1597059479 | Aug 27 06:45:48 AM UTC 24 | Aug 27 06:45:58 AM UTC 24 | 577995466 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1014840767 | Aug 27 06:45:16 AM UTC 24 | Aug 27 06:46:00 AM UTC 24 | 3776231966 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3572551467 | Aug 27 06:45:55 AM UTC 24 | Aug 27 06:46:00 AM UTC 24 | 91369114 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1585326220 | Aug 27 06:45:54 AM UTC 24 | Aug 27 06:46:05 AM UTC 24 | 252969736 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.151893457 | Aug 27 06:45:56 AM UTC 24 | Aug 27 06:46:06 AM UTC 24 | 279686891 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3421959109 | Aug 27 06:45:30 AM UTC 24 | Aug 27 06:46:06 AM UTC 24 | 1213556160 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2452939954 | Aug 27 06:45:58 AM UTC 24 | Aug 27 06:46:08 AM UTC 24 | 1683414507 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2275606307 | Aug 27 06:45:57 AM UTC 24 | Aug 27 06:46:14 AM UTC 24 | 1068995545 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3460125849 | Aug 27 06:46:07 AM UTC 24 | Aug 27 06:46:15 AM UTC 24 | 263051677 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3459382770 | Aug 27 06:44:19 AM UTC 24 | Aug 27 06:46:17 AM UTC 24 | 7772124081 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2833589428 | Aug 27 06:46:07 AM UTC 24 | Aug 27 06:46:17 AM UTC 24 | 792623288 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2417634790 | Aug 27 06:43:35 AM UTC 24 | Aug 27 06:46:18 AM UTC 24 | 32350881308 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1448381403 | Aug 27 06:46:01 AM UTC 24 | Aug 27 06:46:18 AM UTC 24 | 251970802 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3767244818 | Aug 27 06:46:09 AM UTC 24 | Aug 27 06:46:19 AM UTC 24 | 135766786 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.63998634 | Aug 27 06:46:16 AM UTC 24 | Aug 27 06:46:23 AM UTC 24 | 546536674 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.556559448 | Aug 27 06:46:12 AM UTC 24 | Aug 27 06:46:25 AM UTC 24 | 1559822490 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1181243405 | Aug 27 06:44:06 AM UTC 24 | Aug 27 06:46:27 AM UTC 24 | 1161638497 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2776193037 | Aug 27 06:46:18 AM UTC 24 | Aug 27 06:46:29 AM UTC 24 | 2242354474 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3360725163 | Aug 27 06:44:23 AM UTC 24 | Aug 27 06:46:29 AM UTC 24 | 7489389517 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1461332948 | Aug 27 06:46:21 AM UTC 24 | Aug 27 06:46:31 AM UTC 24 | 521768038 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.3239664881 | Aug 27 06:46:19 AM UTC 24 | Aug 27 06:46:33 AM UTC 24 | 669722602 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1540157545 | Aug 27 06:46:25 AM UTC 24 | Aug 27 06:46:33 AM UTC 24 | 375315167 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1611446406 | Aug 27 06:43:19 AM UTC 24 | Aug 27 06:46:38 AM UTC 24 | 4397609802 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3440678809 | Aug 27 06:46:31 AM UTC 24 | Aug 27 06:46:38 AM UTC 24 | 348457502 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2398901145 | Aug 27 06:46:34 AM UTC 24 | Aug 27 06:46:43 AM UTC 24 | 381995915 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2270586321 | Aug 27 06:46:24 AM UTC 24 | Aug 27 06:46:44 AM UTC 24 | 297231672 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.854203458 | Aug 27 06:46:18 AM UTC 24 | Aug 27 06:46:44 AM UTC 24 | 4080143832 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1776356937 | Aug 27 06:46:30 AM UTC 24 | Aug 27 06:46:47 AM UTC 24 | 782980258 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.2729147092 | Aug 27 06:46:41 AM UTC 24 | Aug 27 06:46:49 AM UTC 24 | 251174150 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.516871649 | Aug 27 06:44:43 AM UTC 24 | Aug 27 06:46:54 AM UTC 24 | 16728770821 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2969192014 | Aug 27 06:46:32 AM UTC 24 | Aug 27 06:46:54 AM UTC 24 | 216529979 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2195901397 | Aug 27 06:46:39 AM UTC 24 | Aug 27 06:46:55 AM UTC 24 | 665792444 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.4254631836 | Aug 27 06:46:45 AM UTC 24 | Aug 27 06:46:56 AM UTC 24 | 141902051 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2937349230 | Aug 27 06:46:44 AM UTC 24 | Aug 27 06:46:58 AM UTC 24 | 701464685 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3967591413 | Aug 27 06:46:48 AM UTC 24 | Aug 27 06:47:01 AM UTC 24 | 182089214 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1977125205 | Aug 27 06:45:27 AM UTC 24 | Aug 27 06:47:01 AM UTC 24 | 3071110934 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.602046794 | Aug 27 06:46:55 AM UTC 24 | Aug 27 06:47:02 AM UTC 24 | 348295504 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.525096637 | Aug 27 06:46:56 AM UTC 24 | Aug 27 06:47:03 AM UTC 24 | 141294502 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3365438798 | Aug 27 06:46:50 AM UTC 24 | Aug 27 06:47:10 AM UTC 24 | 1453198281 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3399675086 | Aug 27 06:47:02 AM UTC 24 | Aug 27 06:47:10 AM UTC 24 | 1244174353 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.35626695 | Aug 27 06:44:58 AM UTC 24 | Aug 27 06:47:11 AM UTC 24 | 11744143667 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2028816372 | Aug 27 06:44:37 AM UTC 24 | Aug 27 06:47:11 AM UTC 24 | 23512953698 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1114364823 | Aug 27 06:46:59 AM UTC 24 | Aug 27 06:47:11 AM UTC 24 | 1107114896 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.4046252408 | Aug 27 06:47:03 AM UTC 24 | Aug 27 06:47:12 AM UTC 24 | 441626813 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2076639476 | Aug 27 06:46:56 AM UTC 24 | Aug 27 06:47:18 AM UTC 24 | 212436876 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1373473337 | Aug 27 06:47:11 AM UTC 24 | Aug 27 06:47:19 AM UTC 24 | 760296307 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.165439860 | Aug 27 06:47:12 AM UTC 24 | Aug 27 06:47:23 AM UTC 24 | 478247839 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.895654710 | Aug 27 06:47:12 AM UTC 24 | Aug 27 06:47:23 AM UTC 24 | 145143150 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3508635124 | Aug 27 06:46:20 AM UTC 24 | Aug 27 06:47:24 AM UTC 24 | 1583786863 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1449723619 | Aug 27 06:46:11 AM UTC 24 | Aug 27 06:47:25 AM UTC 24 | 2063434579 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.527456036 | Aug 27 06:47:11 AM UTC 24 | Aug 27 06:47:27 AM UTC 24 | 257109981 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.2475599591 | Aug 27 06:47:03 AM UTC 24 | Aug 27 06:47:27 AM UTC 24 | 303032793 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2791580761 | Aug 27 06:47:20 AM UTC 24 | Aug 27 06:47:27 AM UTC 24 | 298931243 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3883961767 | Aug 27 06:47:15 AM UTC 24 | Aug 27 06:47:29 AM UTC 24 | 450684013 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2647385587 | Aug 27 06:47:24 AM UTC 24 | Aug 27 06:47:34 AM UTC 24 | 139354671 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.781672223 | Aug 27 06:47:28 AM UTC 24 | Aug 27 06:47:37 AM UTC 24 | 517250572 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.660484136 | Aug 27 06:47:28 AM UTC 24 | Aug 27 06:47:38 AM UTC 24 | 664486145 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.384346379 | Aug 27 06:45:53 AM UTC 24 | Aug 27 06:47:40 AM UTC 24 | 5962200011 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.717324580 | Aug 27 06:47:21 AM UTC 24 | Aug 27 06:47:41 AM UTC 24 | 842097528 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.4256564815 | Aug 27 06:47:25 AM UTC 24 | Aug 27 06:47:43 AM UTC 24 | 1002247379 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2548227995 | Aug 27 06:46:34 AM UTC 24 | Aug 27 06:47:46 AM UTC 24 | 6270561523 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3744679430 | Aug 27 06:47:39 AM UTC 24 | Aug 27 06:47:46 AM UTC 24 | 126978490 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3774485662 | Aug 27 06:47:41 AM UTC 24 | Aug 27 06:47:48 AM UTC 24 | 98120165 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.600660249 | Aug 27 06:47:44 AM UTC 24 | Aug 27 06:47:49 AM UTC 24 | 291685671 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3502944508 | Aug 27 06:45:39 AM UTC 24 | Aug 27 06:47:53 AM UTC 24 | 1516856429 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3237336309 | Aug 27 06:47:47 AM UTC 24 | Aug 27 06:47:57 AM UTC 24 | 312736975 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.420601620 | Aug 27 06:47:28 AM UTC 24 | Aug 27 06:47:58 AM UTC 24 | 1243779746 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.55889824 | Aug 27 06:47:35 AM UTC 24 | Aug 27 06:47:59 AM UTC 24 | 1278772499 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2889692666 | Aug 27 06:47:39 AM UTC 24 | Aug 27 06:48:00 AM UTC 24 | 194053683 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1856878647 | Aug 27 06:47:43 AM UTC 24 | Aug 27 06:48:01 AM UTC 24 | 1001131447 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.2316281220 | Aug 27 06:47:55 AM UTC 24 | Aug 27 06:48:02 AM UTC 24 | 308364900 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.757958228 | Aug 27 06:47:46 AM UTC 24 | Aug 27 06:48:07 AM UTC 24 | 331171897 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3184707756 | Aug 27 06:47:50 AM UTC 24 | Aug 27 06:48:08 AM UTC 24 | 251205109 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1668892138 | Aug 27 06:46:18 AM UTC 24 | Aug 27 06:48:10 AM UTC 24 | 2095187633 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3896444032 | Aug 27 06:48:03 AM UTC 24 | Aug 27 06:48:11 AM UTC 24 | 198039008 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2198259561 | Aug 27 06:47:59 AM UTC 24 | Aug 27 06:48:12 AM UTC 24 | 2383695660 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3664002501 | Aug 27 06:48:01 AM UTC 24 | Aug 27 06:48:17 AM UTC 24 | 1036450030 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3141958131 | Aug 27 06:48:09 AM UTC 24 | Aug 27 06:48:18 AM UTC 24 | 821294262 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3918671120 | Aug 27 06:47:58 AM UTC 24 | Aug 27 06:48:19 AM UTC 24 | 1183534818 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4167488202 | Aug 27 06:46:15 AM UTC 24 | Aug 27 06:48:20 AM UTC 24 | 3143498464 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.1306105363 | Aug 27 06:48:13 AM UTC 24 | Aug 27 06:48:21 AM UTC 24 | 497449501 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2531569184 | Aug 27 06:48:12 AM UTC 24 | Aug 27 06:48:23 AM UTC 24 | 178333032 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.4137592754 | Aug 27 06:48:57 AM UTC 24 | Aug 27 06:49:05 AM UTC 24 | 420948110 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.222076850 | Aug 27 06:48:19 AM UTC 24 | Aug 27 06:48:28 AM UTC 24 | 2249163990 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3005988180 | Aug 27 06:48:24 AM UTC 24 | Aug 27 06:48:32 AM UTC 24 | 131417730 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3797971189 | Aug 27 06:48:08 AM UTC 24 | Aug 27 06:48:33 AM UTC 24 | 1212690853 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3501744749 | Aug 27 06:48:17 AM UTC 24 | Aug 27 06:48:34 AM UTC 24 | 3873221404 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2821712697 | Aug 27 06:46:28 AM UTC 24 | Aug 27 06:48:35 AM UTC 24 | 1950892169 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1003979912 | Aug 27 06:48:29 AM UTC 24 | Aug 27 06:48:35 AM UTC 24 | 100055972 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1599059514 | Aug 27 06:48:21 AM UTC 24 | Aug 27 06:48:37 AM UTC 24 | 177397090 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2230347659 | Aug 27 06:46:45 AM UTC 24 | Aug 27 06:48:38 AM UTC 24 | 1215729757 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3196602745 | Aug 27 06:48:26 AM UTC 24 | Aug 27 06:48:39 AM UTC 24 | 2161318010 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2632041893 | Aug 27 06:47:24 AM UTC 24 | Aug 27 06:48:39 AM UTC 24 | 5983740550 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1899428077 | Aug 27 06:47:20 AM UTC 24 | Aug 27 06:48:43 AM UTC 24 | 14835522438 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.4037233722 | Aug 27 06:48:35 AM UTC 24 | Aug 27 06:48:43 AM UTC 24 | 250062834 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3007131519 | Aug 27 06:48:33 AM UTC 24 | Aug 27 06:48:44 AM UTC 24 | 169238665 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1153850730 | Aug 27 06:48:36 AM UTC 24 | Aug 27 06:48:46 AM UTC 24 | 182747694 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3361459449 | Aug 27 06:48:39 AM UTC 24 | Aug 27 06:48:47 AM UTC 24 | 112250795 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.950601814 | Aug 27 06:48:39 AM UTC 24 | Aug 27 06:48:51 AM UTC 24 | 305936935 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.612955567 | Aug 27 06:48:43 AM UTC 24 | Aug 27 06:48:52 AM UTC 24 | 527168648 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.551221146 | Aug 27 06:48:38 AM UTC 24 | Aug 27 06:48:55 AM UTC 24 | 5780003654 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.502241184 | Aug 27 06:48:48 AM UTC 24 | Aug 27 06:48:55 AM UTC 24 | 221316361 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.542460115 | Aug 27 06:46:07 AM UTC 24 | Aug 27 06:48:56 AM UTC 24 | 10589383700 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.3161283206 | Aug 27 06:48:35 AM UTC 24 | Aug 27 06:48:56 AM UTC 24 | 571780430 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2456660656 | Aug 27 06:46:57 AM UTC 24 | Aug 27 06:48:59 AM UTC 24 | 15863404691 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2181945245 | Aug 27 06:48:45 AM UTC 24 | Aug 27 06:49:00 AM UTC 24 | 508374076 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1111171617 | Aug 27 06:48:53 AM UTC 24 | Aug 27 06:49:03 AM UTC 24 | 95427050 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1631223365 | Aug 27 06:48:52 AM UTC 24 | Aug 27 06:49:07 AM UTC 24 | 179662824 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1745994698 | Aug 27 06:46:00 AM UTC 24 | Aug 27 06:49:10 AM UTC 24 | 3927111214 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2297231050 | Aug 27 06:49:01 AM UTC 24 | Aug 27 06:49:11 AM UTC 24 | 632582364 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2014223555 | Aug 27 06:48:56 AM UTC 24 | Aug 27 06:49:12 AM UTC 24 | 170410436 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1318445865 | Aug 27 06:47:26 AM UTC 24 | Aug 27 06:49:18 AM UTC 24 | 2278991646 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2066605813 | Aug 27 06:49:11 AM UTC 24 | Aug 27 06:49:18 AM UTC 24 | 254817636 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1607982516 | Aug 27 06:47:42 AM UTC 24 | Aug 27 06:49:19 AM UTC 24 | 2678474969 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.4188671437 | Aug 27 06:49:05 AM UTC 24 | Aug 27 06:49:20 AM UTC 24 | 177407436 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.793189449 | Aug 27 06:49:00 AM UTC 24 | Aug 27 06:49:21 AM UTC 24 | 405160391 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3605688668 | Aug 27 06:49:13 AM UTC 24 | Aug 27 06:49:22 AM UTC 24 | 94578014 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1025723498 | Aug 27 06:47:48 AM UTC 24 | Aug 27 06:49:23 AM UTC 24 | 7705860072 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1358813739 | Aug 27 06:49:12 AM UTC 24 | Aug 27 06:49:24 AM UTC 24 | 575702484 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.406842196 | Aug 27 06:47:07 AM UTC 24 | Aug 27 06:49:27 AM UTC 24 | 8504177747 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2052942775 | Aug 27 06:49:21 AM UTC 24 | Aug 27 06:49:28 AM UTC 24 | 98107812 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.4171637596 | Aug 27 06:49:23 AM UTC 24 | Aug 27 06:49:31 AM UTC 24 | 135928696 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2151836212 | Aug 27 06:49:19 AM UTC 24 | Aug 27 06:49:35 AM UTC 24 | 1116255825 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1103199611 | Aug 27 06:49:28 AM UTC 24 | Aug 27 06:49:37 AM UTC 24 | 131793481 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2711176647 | Aug 27 06:46:30 AM UTC 24 | Aug 27 06:49:37 AM UTC 24 | 6774040489 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3527965564 | Aug 27 06:48:02 AM UTC 24 | Aug 27 06:49:39 AM UTC 24 | 1791211274 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.545724666 | Aug 27 06:47:02 AM UTC 24 | Aug 27 06:49:41 AM UTC 24 | 4524591987 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.201562763 | Aug 27 06:49:32 AM UTC 24 | Aug 27 06:49:42 AM UTC 24 | 277458385 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3596057986 | Aug 27 06:49:24 AM UTC 24 | Aug 27 06:49:42 AM UTC 24 | 999219071 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1036992618 | Aug 27 06:47:37 AM UTC 24 | Aug 27 06:49:42 AM UTC 24 | 22730426003 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.1108166769 | Aug 27 06:49:29 AM UTC 24 | Aug 27 06:49:43 AM UTC 24 | 593041141 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1349582963 | Aug 27 06:47:13 AM UTC 24 | Aug 27 06:49:51 AM UTC 24 | 12415426031 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1616680464 | Aug 27 06:49:22 AM UTC 24 | Aug 27 06:49:51 AM UTC 24 | 399112229 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2247405544 | Aug 27 06:49:44 AM UTC 24 | Aug 27 06:49:52 AM UTC 24 | 88198996 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1663039044 | Aug 27 06:49:40 AM UTC 24 | Aug 27 06:49:52 AM UTC 24 | 503703495 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.4113170762 | Aug 27 06:49:42 AM UTC 24 | Aug 27 06:49:52 AM UTC 24 | 271049231 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.3696124466 | Aug 27 06:49:38 AM UTC 24 | Aug 27 06:49:54 AM UTC 24 | 169898047 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.663251801 | Aug 27 06:49:43 AM UTC 24 | Aug 27 06:49:59 AM UTC 24 | 997384597 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.677874046 | Aug 27 06:49:54 AM UTC 24 | Aug 27 06:50:00 AM UTC 24 | 168073397 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.947804614 | Aug 27 06:48:19 AM UTC 24 | Aug 27 06:50:02 AM UTC 24 | 3058599918 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2703028322 | Aug 27 06:49:52 AM UTC 24 | Aug 27 06:50:02 AM UTC 24 | 98306317 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1854465227 | Aug 27 06:49:48 AM UTC 24 | Aug 27 06:50:07 AM UTC 24 | 1242101736 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.1036131157 | Aug 27 06:49:52 AM UTC 24 | Aug 27 06:50:07 AM UTC 24 | 2384778431 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2012624310 | Aug 27 06:50:00 AM UTC 24 | Aug 27 06:50:08 AM UTC 24 | 97138539 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1899400865 | Aug 27 06:49:55 AM UTC 24 | Aug 27 06:50:09 AM UTC 24 | 162144385 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1944534810 | Aug 27 06:49:41 AM UTC 24 | Aug 27 06:50:09 AM UTC 24 | 310633941 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2181141368 | Aug 27 06:49:08 AM UTC 24 | Aug 27 06:50:16 AM UTC 24 | 5150239003 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2567458190 | Aug 27 06:50:08 AM UTC 24 | Aug 27 06:50:16 AM UTC 24 | 951749292 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.562983215 | Aug 27 06:50:09 AM UTC 24 | Aug 27 06:50:18 AM UTC 24 | 389657038 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3534035738 | Aug 27 06:50:03 AM UTC 24 | Aug 27 06:50:21 AM UTC 24 | 508536769 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1846086723 | Aug 27 06:50:10 AM UTC 24 | Aug 27 06:50:22 AM UTC 24 | 168884895 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2751063414 | Aug 27 06:50:17 AM UTC 24 | Aug 27 06:50:25 AM UTC 24 | 172239555 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.250751193 | Aug 27 06:48:00 AM UTC 24 | Aug 27 06:50:28 AM UTC 24 | 2982125230 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.4104752197 | Aug 27 06:50:19 AM UTC 24 | Aug 27 06:50:31 AM UTC 24 | 1349570033 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.493721289 | Aug 27 06:50:21 AM UTC 24 | Aug 27 06:50:31 AM UTC 24 | 556649133 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3545614042 | Aug 27 06:48:11 AM UTC 24 | Aug 27 06:50:33 AM UTC 24 | 5718239155 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2369672187 | Aug 27 06:50:08 AM UTC 24 | Aug 27 06:50:33 AM UTC 24 | 664569657 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2147421470 | Aug 27 06:49:43 AM UTC 24 | Aug 27 06:50:33 AM UTC 24 | 2415878387 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.699743075 | Aug 27 06:50:23 AM UTC 24 | Aug 27 06:50:36 AM UTC 24 | 343335639 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1420603748 | Aug 27 06:50:29 AM UTC 24 | Aug 27 06:50:37 AM UTC 24 | 148038476 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2601163194 | Aug 27 06:48:47 AM UTC 24 | Aug 27 06:50:37 AM UTC 24 | 5730227799 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.563654255 | Aug 27 06:47:30 AM UTC 24 | Aug 27 06:50:40 AM UTC 24 | 7425009322 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3518801274 | Aug 27 06:50:32 AM UTC 24 | Aug 27 06:50:40 AM UTC 24 | 548579018 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.2676980795 | Aug 27 06:50:37 AM UTC 24 | Aug 27 06:50:43 AM UTC 24 | 153949706 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1318082226 | Aug 27 06:50:38 AM UTC 24 | Aug 27 06:50:45 AM UTC 24 | 404272512 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4091790034 | Aug 27 06:47:53 AM UTC 24 | Aug 27 06:50:46 AM UTC 24 | 12618527555 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2122380162 | Aug 27 06:50:34 AM UTC 24 | Aug 27 06:50:46 AM UTC 24 | 667368631 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3674156119 | Aug 27 06:50:32 AM UTC 24 | Aug 27 06:50:49 AM UTC 24 | 1404049570 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.114052455 | Aug 27 06:50:46 AM UTC 24 | Aug 27 06:50:53 AM UTC 24 | 597348402 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1350423981 | Aug 27 06:50:40 AM UTC 24 | Aug 27 06:50:56 AM UTC 24 | 697134708 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2300326998 | Aug 27 06:50:47 AM UTC 24 | Aug 27 06:50:57 AM UTC 24 | 563218885 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.2119402294 | Aug 27 06:50:38 AM UTC 24 | Aug 27 06:50:57 AM UTC 24 | 369262707 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3991836155 | Aug 27 06:48:32 AM UTC 24 | Aug 27 06:51:03 AM UTC 24 | 2592040130 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1629538686 | Aug 27 06:50:58 AM UTC 24 | Aug 27 06:51:05 AM UTC 24 | 1034586272 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1952309874 | Aug 27 06:49:36 AM UTC 24 | Aug 27 06:51:07 AM UTC 24 | 2797863241 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.56252833 | Aug 27 06:50:58 AM UTC 24 | Aug 27 06:51:10 AM UTC 24 | 175069720 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3077601102 | Aug 27 06:49:19 AM UTC 24 | Aug 27 06:51:11 AM UTC 24 | 9080498827 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.487621996 | Aug 27 06:50:54 AM UTC 24 | Aug 27 06:51:11 AM UTC 24 | 521369700 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.4003658689 | Aug 27 06:51:04 AM UTC 24 | Aug 27 06:51:14 AM UTC 24 | 269925102 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.649525647 | Aug 27 06:51:07 AM UTC 24 | Aug 27 06:51:15 AM UTC 24 | 693231638 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2849750616 | Aug 27 06:50:47 AM UTC 24 | Aug 27 06:51:17 AM UTC 24 | 446822743 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1494017976 | Aug 27 06:48:45 AM UTC 24 | Aug 27 06:51:19 AM UTC 24 | 7087424027 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.529894309 | Aug 27 06:49:20 AM UTC 24 | Aug 27 06:51:20 AM UTC 24 | 6284915027 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.37074154 | Aug 27 06:51:12 AM UTC 24 | Aug 27 06:51:21 AM UTC 24 | 192337524 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3149585397 | Aug 27 06:51:05 AM UTC 24 | Aug 27 06:51:21 AM UTC 24 | 666146671 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2822543979 | Aug 27 06:48:12 AM UTC 24 | Aug 27 06:51:22 AM UTC 24 | 2405236098 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1804136246 | Aug 27 06:51:16 AM UTC 24 | Aug 27 06:51:23 AM UTC 24 | 85469193 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.125450657 | Aug 27 06:51:20 AM UTC 24 | Aug 27 06:51:29 AM UTC 24 | 144352054 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2420140172 | Aug 27 06:47:44 AM UTC 24 | Aug 27 06:51:29 AM UTC 24 | 4538326132 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1677351216 | Aug 27 06:51:23 AM UTC 24 | Aug 27 06:51:31 AM UTC 24 | 133710030 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3702130093 | Aug 27 06:51:18 AM UTC 24 | Aug 27 06:51:31 AM UTC 24 | 136773667 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3920846855 | Aug 27 06:51:14 AM UTC 24 | Aug 27 06:51:31 AM UTC 24 | 260492156 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1116118923 | Aug 27 06:45:54 AM UTC 24 | Aug 27 06:51:33 AM UTC 24 | 9339760987 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.4107143039 | Aug 27 06:51:11 AM UTC 24 | Aug 27 06:51:34 AM UTC 24 | 1288435722 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1941093285 | Aug 27 06:51:26 AM UTC 24 | Aug 27 06:51:34 AM UTC 24 | 137921099 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1705665836 | Aug 27 06:51:22 AM UTC 24 | Aug 27 06:51:36 AM UTC 24 | 258455530 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4103538127 | Aug 27 06:48:36 AM UTC 24 | Aug 27 06:51:38 AM UTC 24 | 16602567517 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.745807143 | Aug 27 06:50:57 AM UTC 24 | Aug 27 06:51:39 AM UTC 24 | 10979699518 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.652241504 | Aug 27 06:51:33 AM UTC 24 | Aug 27 06:51:40 AM UTC 24 | 88832053 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3145657760 | Aug 27 06:51:34 AM UTC 24 | Aug 27 06:51:43 AM UTC 24 | 97488969 ps |
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