Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
424 427 99.30 424 427 99.30 1


Total groups in report: 15
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 13 15 86.67 92.86 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg 22 24 91.67 91.67 1 100 1 1 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 14 14 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
push_pull_agent_pkg::valid_ready_cg 4 4 100.00 100.00 1 100 1 1 64 64
tb.dut.u_rom_ctrl_cov_if::rom_ctrl_check_cg 2 2 100.00 100.00 1 100 1 1 64 64
tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg 7 7 100.00 100.00 1 100 1 1 64 64
tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg 6 6 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=2} 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%