Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

583815

1

T2

24

T3

205

T4

56

full_word

351081

1

T2

3

T3

22

T4

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	934586	1			T2	27		T3	227		T4	63
auto[TlIntgErrCmd]	113	1			T63	6		T64	5		T65	4
auto[TlIntgErrData]	97	1			T63	2		T64	3		T65	4
auto[TlIntgErrBoth]	100	1			T63	2		T64	2		T65	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167982

1

T2

27

T3

227

T4

63

auto[1]

766914

1

T15

10335

T16

11155

T17

5198

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	83284	1			T2	24		T3	205		T4	56
auto[TlIntgErrNone]	partial	auto[1]	500244	1			T15	6471		T16	7395		T17	3048
auto[TlIntgErrNone]	full_word	auto[0]	84564	1			T2	3		T3	22		T4	7
auto[TlIntgErrNone]	full_word	auto[1]	266494	1			T15	3864		T16	3760		T17	2150
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T63	1		T64	2		T128	3
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T63	5		T64	3		T65	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T126	1		T124	2		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T65	1		T129	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T64	1		T65	1		T128	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T63	2		T64	1		T65	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T128	2		T126	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T64	1		T131	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T63	1		T126	2		T124	5
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T64	2		T65	2		T128	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T124	1		T133	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T63	1		T123	1		T134	1