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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.60 96.89 92.56 97.67 100.00 98.97 98.05 99.06


Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T297 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2486695630 Sep 01 09:00:33 AM UTC 24 Sep 01 09:00:53 AM UTC 24 191173526 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3956382573 Sep 01 08:59:41 AM UTC 24 Sep 01 09:00:53 AM UTC 24 3590536713 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3792066639 Sep 01 09:00:25 AM UTC 24 Sep 01 09:00:54 AM UTC 24 1676573519 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.712082036 Sep 01 09:00:37 AM UTC 24 Sep 01 09:00:55 AM UTC 24 531954210 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2306982313 Sep 01 09:00:49 AM UTC 24 Sep 01 09:00:57 AM UTC 24 127824804 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3848170176 Sep 01 08:57:55 AM UTC 24 Sep 01 09:00:58 AM UTC 24 8360310142 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2196155939 Sep 01 09:00:40 AM UTC 24 Sep 01 09:00:59 AM UTC 24 688871361 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2523289711 Sep 01 08:58:31 AM UTC 24 Sep 01 09:01:01 AM UTC 24 10578217306 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1106416675 Sep 01 09:00:44 AM UTC 24 Sep 01 09:01:02 AM UTC 24 3117952149 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.617440420 Sep 01 09:00:53 AM UTC 24 Sep 01 09:01:04 AM UTC 24 141730717 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1585843243 Sep 01 09:00:55 AM UTC 24 Sep 01 09:01:04 AM UTC 24 427115771 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3244903018 Sep 01 08:59:33 AM UTC 24 Sep 01 09:01:04 AM UTC 24 15607858806 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.168634052 Sep 01 09:00:59 AM UTC 24 Sep 01 09:01:07 AM UTC 24 96306865 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1011325670 Sep 01 09:00:52 AM UTC 24 Sep 01 09:01:08 AM UTC 24 282414744 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1076944577 Sep 01 08:59:35 AM UTC 24 Sep 01 09:01:08 AM UTC 24 1659039712 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.865106149 Sep 01 09:01:03 AM UTC 24 Sep 01 09:01:09 AM UTC 24 86222623 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3988297937 Sep 01 08:58:56 AM UTC 24 Sep 01 09:01:10 AM UTC 24 1792347324 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2147197928 Sep 01 09:01:05 AM UTC 24 Sep 01 09:01:13 AM UTC 24 515791808 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.970116053 Sep 01 08:58:51 AM UTC 24 Sep 01 09:01:15 AM UTC 24 2702841906 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.2436319132 Sep 01 09:01:07 AM UTC 24 Sep 01 09:01:15 AM UTC 24 542692445 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1883440057 Sep 01 09:01:05 AM UTC 24 Sep 01 09:01:17 AM UTC 24 257456340 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1563309535 Sep 01 09:01:00 AM UTC 24 Sep 01 09:01:17 AM UTC 24 1038364100 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.715964556 Sep 01 09:00:54 AM UTC 24 Sep 01 09:01:19 AM UTC 24 988109925 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2266266844 Sep 01 08:59:56 AM UTC 24 Sep 01 09:01:23 AM UTC 24 3320961368 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2982824506 Sep 01 09:01:05 AM UTC 24 Sep 01 09:01:25 AM UTC 24 1132329581 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1938262172 Sep 01 09:00:57 AM UTC 24 Sep 01 09:01:26 AM UTC 24 1662812681 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3290197189 Sep 01 08:57:40 AM UTC 24 Sep 01 09:01:27 AM UTC 24 11125387599 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.397678553 Sep 01 08:58:07 AM UTC 24 Sep 01 09:01:28 AM UTC 24 10554678909 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1990646650 Sep 01 09:00:15 AM UTC 24 Sep 01 09:01:30 AM UTC 24 7418209174 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1671904657 Sep 01 08:59:03 AM UTC 24 Sep 01 09:01:33 AM UTC 24 6001538920 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.993448626 Sep 01 08:59:23 AM UTC 24 Sep 01 09:01:34 AM UTC 24 1904133342 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2607360919 Sep 01 09:00:38 AM UTC 24 Sep 01 09:01:36 AM UTC 24 3902847150 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3497480113 Sep 01 08:59:40 AM UTC 24 Sep 01 09:01:40 AM UTC 24 4085327805 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2288197237 Sep 01 09:00:06 AM UTC 24 Sep 01 09:01:42 AM UTC 24 4792024139 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2720440295 Sep 01 08:58:49 AM UTC 24 Sep 01 09:01:43 AM UTC 24 18211866339 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2342823087 Sep 01 08:58:16 AM UTC 24 Sep 01 09:01:44 AM UTC 24 15321796285 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2891512444 Sep 01 08:59:59 AM UTC 24 Sep 01 09:01:50 AM UTC 24 1953848474 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2345183528 Sep 01 08:57:13 AM UTC 24 Sep 01 09:01:50 AM UTC 24 19218385650 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.430220959 Sep 01 08:58:26 AM UTC 24 Sep 01 09:01:52 AM UTC 24 2650222905 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1870992277 Sep 01 09:01:02 AM UTC 24 Sep 01 09:01:57 AM UTC 24 21909822441 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4284990347 Sep 01 08:59:45 AM UTC 24 Sep 01 09:01:58 AM UTC 24 17210148020 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2737988881 Sep 01 08:57:22 AM UTC 24 Sep 01 09:02:00 AM UTC 24 14278788780 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2147012833 Sep 01 08:59:09 AM UTC 24 Sep 01 09:02:00 AM UTC 24 5109051317 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3056660090 Sep 01 09:00:13 AM UTC 24 Sep 01 09:02:04 AM UTC 24 1582562781 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2545007474 Sep 01 09:00:32 AM UTC 24 Sep 01 09:02:05 AM UTC 24 5276450381 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3866197827 Sep 01 09:01:00 AM UTC 24 Sep 01 09:02:24 AM UTC 24 1924159726 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1876040383 Sep 01 09:00:06 AM UTC 24 Sep 01 09:02:25 AM UTC 24 16173015059 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1844061093 Sep 01 09:00:33 AM UTC 24 Sep 01 09:02:31 AM UTC 24 8801424819 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3812008332 Sep 01 09:00:54 AM UTC 24 Sep 01 09:02:39 AM UTC 24 7950286486 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1417213483 Sep 01 09:00:20 AM UTC 24 Sep 01 09:02:50 AM UTC 24 18847878421 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1965671446 Sep 01 08:59:59 AM UTC 24 Sep 01 09:02:57 AM UTC 24 3800434999 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1382463047 Sep 01 08:58:37 AM UTC 24 Sep 01 09:03:08 AM UTC 24 7265569807 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2998480139 Sep 01 09:00:45 AM UTC 24 Sep 01 09:03:08 AM UTC 24 3335768579 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4002340972 Sep 01 09:00:55 AM UTC 24 Sep 01 09:03:21 AM UTC 24 3753861353 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2824929032 Sep 01 09:00:29 AM UTC 24 Sep 01 09:03:30 AM UTC 24 5664885816 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3248842506 Sep 01 09:00:42 AM UTC 24 Sep 01 09:03:40 AM UTC 24 34136190649 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2448860234 Sep 01 08:59:55 AM UTC 24 Sep 01 09:03:58 AM UTC 24 46879089966 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4196517069 Sep 01 08:57:40 AM UTC 24 Sep 01 09:04:01 AM UTC 24 4314095593 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3458096712 Sep 01 08:59:49 AM UTC 24 Sep 01 09:04:09 AM UTC 24 13988746051 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2644776601 Sep 01 09:01:05 AM UTC 24 Sep 01 09:04:10 AM UTC 24 5506325624 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2789446833 Sep 01 09:00:23 AM UTC 24 Sep 01 09:05:16 AM UTC 24 3844573747 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3662651959 Sep 01 08:59:27 AM UTC 24 Sep 01 09:07:31 AM UTC 24 23637055954 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.614225687 Sep 01 09:01:11 AM UTC 24 Sep 01 09:01:18 AM UTC 24 270258126 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3476100707 Sep 01 09:01:11 AM UTC 24 Sep 01 09:01:18 AM UTC 24 175309059 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.480745668 Sep 01 09:01:16 AM UTC 24 Sep 01 09:01:23 AM UTC 24 690257976 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1813716945 Sep 01 09:01:18 AM UTC 24 Sep 01 09:01:24 AM UTC 24 175140390 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1003986368 Sep 01 09:01:16 AM UTC 24 Sep 01 09:01:24 AM UTC 24 521353149 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.153447577 Sep 01 09:01:18 AM UTC 24 Sep 01 09:01:24 AM UTC 24 333876384 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2367620566 Sep 01 09:01:09 AM UTC 24 Sep 01 09:01:26 AM UTC 24 378763257 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3505394089 Sep 01 09:01:56 AM UTC 24 Sep 01 09:02:06 AM UTC 24 516816258 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3092739889 Sep 01 09:01:14 AM UTC 24 Sep 01 09:01:26 AM UTC 24 511542783 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1115505719 Sep 01 09:01:23 AM UTC 24 Sep 01 09:02:06 AM UTC 24 244357921 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1364319151 Sep 01 09:01:19 AM UTC 24 Sep 01 09:01:28 AM UTC 24 143458669 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1313533196 Sep 01 09:01:23 AM UTC 24 Sep 01 09:01:31 AM UTC 24 89188724 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1619498850 Sep 01 09:01:20 AM UTC 24 Sep 01 09:01:32 AM UTC 24 130938060 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.364831729 Sep 01 09:01:24 AM UTC 24 Sep 01 09:01:32 AM UTC 24 178055478 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1984265203 Sep 01 09:01:27 AM UTC 24 Sep 01 09:01:33 AM UTC 24 517698810 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1096155215 Sep 01 09:01:27 AM UTC 24 Sep 01 09:01:34 AM UTC 24 354290328 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2866498956 Sep 01 09:01:25 AM UTC 24 Sep 01 09:01:34 AM UTC 24 132119217 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2284437355 Sep 01 09:01:26 AM UTC 24 Sep 01 09:01:34 AM UTC 24 498182084 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1418986249 Sep 01 09:01:29 AM UTC 24 Sep 01 09:01:37 AM UTC 24 171950860 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1184132639 Sep 01 09:01:27 AM UTC 24 Sep 01 09:01:37 AM UTC 24 384334073 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1717517288 Sep 01 09:01:31 AM UTC 24 Sep 01 09:01:38 AM UTC 24 497674068 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1268602400 Sep 01 09:01:08 AM UTC 24 Sep 01 09:01:38 AM UTC 24 1309162022 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1591719625 Sep 01 09:01:24 AM UTC 24 Sep 01 09:01:40 AM UTC 24 949322779 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3157379465 Sep 01 09:01:33 AM UTC 24 Sep 01 09:01:41 AM UTC 24 85971779 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.785471280 Sep 01 09:01:33 AM UTC 24 Sep 01 09:01:41 AM UTC 24 638362271 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1488527795 Sep 01 09:01:31 AM UTC 24 Sep 01 09:01:41 AM UTC 24 315896201 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1119978220 Sep 01 09:01:28 AM UTC 24 Sep 01 09:01:41 AM UTC 24 88881220 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3047452155 Sep 01 09:01:34 AM UTC 24 Sep 01 09:01:42 AM UTC 24 519815257 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3516320040 Sep 01 09:01:33 AM UTC 24 Sep 01 09:01:42 AM UTC 24 567130640 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3344145028 Sep 01 09:01:34 AM UTC 24 Sep 01 09:01:44 AM UTC 24 277730969 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2362259547 Sep 01 09:01:38 AM UTC 24 Sep 01 09:01:46 AM UTC 24 148780055 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4158387925 Sep 01 09:01:38 AM UTC 24 Sep 01 09:01:46 AM UTC 24 176940199 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3650159060 Sep 01 09:01:39 AM UTC 24 Sep 01 09:01:46 AM UTC 24 567113912 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1521200323 Sep 01 09:01:39 AM UTC 24 Sep 01 09:01:47 AM UTC 24 2348565294 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1510489162 Sep 01 09:01:41 AM UTC 24 Sep 01 09:01:48 AM UTC 24 142719098 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3449849916 Sep 01 09:01:41 AM UTC 24 Sep 01 09:01:48 AM UTC 24 542419386 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3391706690 Sep 01 09:01:37 AM UTC 24 Sep 01 09:01:48 AM UTC 24 974205344 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3647908484 Sep 01 09:01:35 AM UTC 24 Sep 01 09:01:49 AM UTC 24 309952125 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1684516428 Sep 01 09:01:41 AM UTC 24 Sep 01 09:01:49 AM UTC 24 132106586 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2426784434 Sep 01 09:01:45 AM UTC 24 Sep 01 09:01:51 AM UTC 24 250939824 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.312932672 Sep 01 09:01:42 AM UTC 24 Sep 01 09:01:51 AM UTC 24 214064569 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2521072916 Sep 01 09:01:45 AM UTC 24 Sep 01 09:01:51 AM UTC 24 127192257 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3552964614 Sep 01 09:01:44 AM UTC 24 Sep 01 09:01:51 AM UTC 24 260397226 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1687654920 Sep 01 09:01:44 AM UTC 24 Sep 01 09:01:52 AM UTC 24 344348023 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1201046804 Sep 01 09:01:45 AM UTC 24 Sep 01 09:01:52 AM UTC 24 1046557985 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1487776883 Sep 01 09:01:42 AM UTC 24 Sep 01 09:01:53 AM UTC 24 351316749 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1089476995 Sep 01 09:01:47 AM UTC 24 Sep 01 09:01:56 AM UTC 24 544343605 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3853873280 Sep 01 09:01:47 AM UTC 24 Sep 01 09:01:56 AM UTC 24 550571841 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.445125631 Sep 01 09:01:49 AM UTC 24 Sep 01 09:01:57 AM UTC 24 544855301 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.316278082 Sep 01 09:01:48 AM UTC 24 Sep 01 09:01:57 AM UTC 24 461083162 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1179426163 Sep 01 09:01:49 AM UTC 24 Sep 01 09:01:58 AM UTC 24 521728462 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1545665049 Sep 01 09:01:52 AM UTC 24 Sep 01 09:01:59 AM UTC 24 483919038 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2041833244 Sep 01 09:01:49 AM UTC 24 Sep 01 09:01:59 AM UTC 24 269786544 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3831770401 Sep 01 09:01:52 AM UTC 24 Sep 01 09:02:00 AM UTC 24 518921666 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2956021406 Sep 01 09:01:53 AM UTC 24 Sep 01 09:02:00 AM UTC 24 361483199 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3933171709 Sep 01 09:01:19 AM UTC 24 Sep 01 09:02:01 AM UTC 24 566721070 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.217602218 Sep 01 09:01:53 AM UTC 24 Sep 01 09:02:01 AM UTC 24 131811141 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2960641005 Sep 01 09:01:53 AM UTC 24 Sep 01 09:02:02 AM UTC 24 322371288 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1910403958 Sep 01 09:01:52 AM UTC 24 Sep 01 09:02:02 AM UTC 24 104228475 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2952927812 Sep 01 09:01:50 AM UTC 24 Sep 01 09:02:02 AM UTC 24 521026808 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4137714491 Sep 01 09:01:27 AM UTC 24 Sep 01 09:02:02 AM UTC 24 782459593 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3748801501 Sep 01 09:01:53 AM UTC 24 Sep 01 09:02:02 AM UTC 24 260198239 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1399209736 Sep 01 09:01:42 AM UTC 24 Sep 01 09:02:03 AM UTC 24 1494439925 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2403715518 Sep 01 09:01:57 AM UTC 24 Sep 01 09:02:06 AM UTC 24 245103534 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1848792141 Sep 01 09:01:09 AM UTC 24 Sep 01 09:02:06 AM UTC 24 655871536 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1404538780 Sep 01 09:01:58 AM UTC 24 Sep 01 09:02:06 AM UTC 24 958952240 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.333974518 Sep 01 09:02:00 AM UTC 24 Sep 01 09:02:07 AM UTC 24 362991282 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1003715131 Sep 01 09:01:59 AM UTC 24 Sep 01 09:02:07 AM UTC 24 95255992 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1809287145 Sep 01 09:01:35 AM UTC 24 Sep 01 09:02:07 AM UTC 24 1038276243 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.477134296 Sep 01 09:02:01 AM UTC 24 Sep 01 09:02:08 AM UTC 24 350231603 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1779649000 Sep 01 09:02:01 AM UTC 24 Sep 01 09:02:09 AM UTC 24 1125368184 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.925969689 Sep 01 09:01:59 AM UTC 24 Sep 01 09:02:09 AM UTC 24 87322995 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3911139972 Sep 01 09:02:02 AM UTC 24 Sep 01 09:02:10 AM UTC 24 347973506 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.880491925 Sep 01 09:02:02 AM UTC 24 Sep 01 09:02:11 AM UTC 24 518955104 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.408560767 Sep 01 09:02:02 AM UTC 24 Sep 01 09:02:11 AM UTC 24 410651936 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.573617928 Sep 01 09:02:03 AM UTC 24 Sep 01 09:02:11 AM UTC 24 86791837 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2413472315 Sep 01 09:02:01 AM UTC 24 Sep 01 09:02:12 AM UTC 24 145792072 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.61480211 Sep 01 09:02:05 AM UTC 24 Sep 01 09:02:11 AM UTC 24 128709783 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1150380207 Sep 01 09:01:50 AM UTC 24 Sep 01 09:02:12 AM UTC 24 1283101749 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3994365948 Sep 01 09:02:05 AM UTC 24 Sep 01 09:02:13 AM UTC 24 504353248 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4034272805 Sep 01 09:02:07 AM UTC 24 Sep 01 09:02:13 AM UTC 24 1186174347 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2389109509 Sep 01 09:02:03 AM UTC 24 Sep 01 09:02:15 AM UTC 24 367606061 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3556991568 Sep 01 09:02:09 AM UTC 24 Sep 01 09:02:15 AM UTC 24 251607523 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2744549015 Sep 01 09:02:07 AM UTC 24 Sep 01 09:02:15 AM UTC 24 534255567 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2116006540 Sep 01 09:02:08 AM UTC 24 Sep 01 09:02:16 AM UTC 24 541452731 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.571215124 Sep 01 09:02:07 AM UTC 24 Sep 01 09:02:16 AM UTC 24 97078127 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2234497989 Sep 01 09:02:07 AM UTC 24 Sep 01 09:02:18 AM UTC 24 127441471 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1118938194 Sep 01 09:02:12 AM UTC 24 Sep 01 09:02:19 AM UTC 24 558689014 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1462188280 Sep 01 09:02:12 AM UTC 24 Sep 01 09:02:20 AM UTC 24 89048976 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4239210934 Sep 01 09:02:12 AM UTC 24 Sep 01 09:02:20 AM UTC 24 190891894 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3022657794 Sep 01 09:02:14 AM UTC 24 Sep 01 09:02:20 AM UTC 24 593265159 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2894780942 Sep 01 09:02:08 AM UTC 24 Sep 01 09:02:20 AM UTC 24 1241420374 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3834927012 Sep 01 09:02:10 AM UTC 24 Sep 01 09:02:21 AM UTC 24 511592899 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2398668721 Sep 01 09:02:11 AM UTC 24 Sep 01 09:02:21 AM UTC 24 163686738 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.204809303 Sep 01 09:01:59 AM UTC 24 Sep 01 09:02:22 AM UTC 24 2367362444 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4246158437 Sep 01 09:02:13 AM UTC 24 Sep 01 09:02:22 AM UTC 24 256210098 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.325012747 Sep 01 09:02:16 AM UTC 24 Sep 01 09:02:23 AM UTC 24 351008435 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1829097046 Sep 01 09:02:13 AM UTC 24 Sep 01 09:02:24 AM UTC 24 520517526 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1410127116 Sep 01 09:01:47 AM UTC 24 Sep 01 09:02:25 AM UTC 24 3167300631 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.222111557 Sep 01 09:02:18 AM UTC 24 Sep 01 09:02:26 AM UTC 24 266934475 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4016406917 Sep 01 09:02:02 AM UTC 24 Sep 01 09:02:27 AM UTC 24 1073142601 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1332388528 Sep 01 09:02:19 AM UTC 24 Sep 01 09:02:27 AM UTC 24 128699146 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1958824436 Sep 01 09:02:23 AM UTC 24 Sep 01 09:02:29 AM UTC 24 132216986 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.975752243 Sep 01 09:02:21 AM UTC 24 Sep 01 09:02:29 AM UTC 24 498769967 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3039580936 Sep 01 09:01:54 AM UTC 24 Sep 01 09:02:30 AM UTC 24 824987071 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.376815997 Sep 01 09:02:21 AM UTC 24 Sep 01 09:02:30 AM UTC 24 2069622759 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.99349812 Sep 01 09:02:25 AM UTC 24 Sep 01 09:02:30 AM UTC 24 301161953 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2316834269 Sep 01 09:02:20 AM UTC 24 Sep 01 09:02:31 AM UTC 24 5511311266 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3361969958 Sep 01 09:02:24 AM UTC 24 Sep 01 09:02:31 AM UTC 24 347577110 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3156639825 Sep 01 09:02:17 AM UTC 24 Sep 01 09:02:31 AM UTC 24 127635550 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2148735274 Sep 01 09:02:01 AM UTC 24 Sep 01 09:02:31 AM UTC 24 1095977325 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3504082024 Sep 01 09:02:25 AM UTC 24 Sep 01 09:02:32 AM UTC 24 139518188 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2863080696 Sep 01 09:02:20 AM UTC 24 Sep 01 09:02:33 AM UTC 24 256879229 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4234235586 Sep 01 09:02:27 AM UTC 24 Sep 01 09:02:34 AM UTC 24 538966533 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3107451606 Sep 01 09:01:52 AM UTC 24 Sep 01 09:02:35 AM UTC 24 819880769 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.719160593 Sep 01 09:02:23 AM UTC 24 Sep 01 09:02:36 AM UTC 24 617732696 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1536329168 Sep 01 09:02:27 AM UTC 24 Sep 01 09:02:36 AM UTC 24 96536485 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4285135713 Sep 01 09:02:29 AM UTC 24 Sep 01 09:02:36 AM UTC 24 2215498938 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.651213827 Sep 01 09:02:26 AM UTC 24 Sep 01 09:02:37 AM UTC 24 146375029 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.472245558 Sep 01 09:01:49 AM UTC 24 Sep 01 09:02:37 AM UTC 24 238531065 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.727697796 Sep 01 09:02:17 AM UTC 24 Sep 01 09:02:37 AM UTC 24 1453591389 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.129474277 Sep 01 09:01:56 AM UTC 24 Sep 01 09:02:39 AM UTC 24 727784174 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2280854815 Sep 01 09:02:06 AM UTC 24 Sep 01 09:02:39 AM UTC 24 550000277 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1588168626 Sep 01 09:02:07 AM UTC 24 Sep 01 09:02:40 AM UTC 24 561909737 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.804694644 Sep 01 09:02:12 AM UTC 24 Sep 01 09:02:40 AM UTC 24 1815911932 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2208207323 Sep 01 09:02:11 AM UTC 24 Sep 01 09:02:41 AM UTC 24 1003588779 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.916815310 Sep 01 09:01:53 AM UTC 24 Sep 01 09:02:42 AM UTC 24 206057895 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.831560843 Sep 01 09:02:07 AM UTC 24 Sep 01 09:02:44 AM UTC 24 206335480 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2575875963 Sep 01 09:02:00 AM UTC 24 Sep 01 09:02:49 AM UTC 24 670520267 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.237219915 Sep 01 09:02:01 AM UTC 24 Sep 01 09:02:51 AM UTC 24 800977906 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1272983722 Sep 01 09:01:36 AM UTC 24 Sep 01 09:02:52 AM UTC 24 845502549 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1496802996 Sep 01 09:02:20 AM UTC 24 Sep 01 09:02:53 AM UTC 24 828331402 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.313094060 Sep 01 09:02:23 AM UTC 24 Sep 01 09:02:58 AM UTC 24 2230652420 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2140597436 Sep 01 09:01:29 AM UTC 24 Sep 01 09:02:59 AM UTC 24 897213193 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1840950851 Sep 01 09:01:42 AM UTC 24 Sep 01 09:03:05 AM UTC 24 1055840646 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.836977026 Sep 01 09:02:20 AM UTC 24 Sep 01 09:03:07 AM UTC 24 666140058 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3051024235 Sep 01 09:02:26 AM UTC 24 Sep 01 09:03:09 AM UTC 24 15620496608 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.235444940 Sep 01 09:02:13 AM UTC 24 Sep 01 09:03:11 AM UTC 24 249169579 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4106002876 Sep 01 09:02:27 AM UTC 24 Sep 01 09:03:18 AM UTC 24 591625284 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.881995152 Sep 01 09:02:03 AM UTC 24 Sep 01 09:03:24 AM UTC 24 223067074 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2645861573 Sep 01 09:02:08 AM UTC 24 Sep 01 09:03:24 AM UTC 24 258210481 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1366876917 Sep 01 09:01:51 AM UTC 24 Sep 01 09:03:25 AM UTC 24 2429441505 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1729648832 Sep 01 09:02:12 AM UTC 24 Sep 01 09:03:28 AM UTC 24 658135452 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2974802584 Sep 01 09:02:17 AM UTC 24 Sep 01 09:03:38 AM UTC 24 1082600471 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3936410677 Sep 01 09:02:24 AM UTC 24 Sep 01 09:03:59 AM UTC 24 220804082 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1544365444
Short name T3
Test name
Test status
Simulation time 1072231869 ps
CPU time 22.86 seconds
Started Sep 01 08:52:35 AM UTC 24
Finished Sep 01 08:53:00 AM UTC 24
Peak memory 225520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154436544
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.1544365444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2944248643
Short name T15
Test name
Test status
Simulation time 3574931631 ps
CPU time 93.74 seconds
Started Sep 01 08:53:00 AM UTC 24
Finished Sep 01 08:54:36 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2944248643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2944248643
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3966141372
Short name T40
Test name
Test status
Simulation time 9170198296 ps
CPU time 131.37 seconds
Started Sep 01 08:53:54 AM UTC 24
Finished Sep 01 08:56:07 AM UTC 24
Peak memory 257544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966141372 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.3966141372
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2450191904
Short name T26
Test name
Test status
Simulation time 253997610 ps
CPU time 16.77 seconds
Started Sep 01 08:53:55 AM UTC 24
Finished Sep 01 08:54:13 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450191904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2450191904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.640173837
Short name T21
Test name
Test status
Simulation time 3450742737 ps
CPU time 127.04 seconds
Started Sep 01 08:52:44 AM UTC 24
Finished Sep 01 08:54:54 AM UTC 24
Peak memory 258412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640173837 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.640173837
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1848792141
Short name T59
Test name
Test status
Simulation time 655871536 ps
CPU time 54.78 seconds
Started Sep 01 09:01:09 AM UTC 24
Finished Sep 01 09:02:06 AM UTC 24
Peak memory 222292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848792141 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.1848792141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3876948601
Short name T225
Test name
Test status
Simulation time 3913627960 ps
CPU time 166.09 seconds
Started Sep 01 08:56:23 AM UTC 24
Finished Sep 01 08:59:12 AM UTC 24
Peak memory 242092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876948601 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.3876948601
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1386033295
Short name T25
Test name
Test status
Simulation time 1959995667 ps
CPU time 123.4 seconds
Started Sep 01 08:53:30 AM UTC 24
Finished Sep 01 08:55:36 AM UTC 24
Peak memory 257660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386033295 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1386033295
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1840950851
Short name T119
Test name
Test status
Simulation time 1055840646 ps
CPU time 80.39 seconds
Started Sep 01 09:01:42 AM UTC 24
Finished Sep 01 09:03:05 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840950851 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.1840950851
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2866498956
Short name T71
Test name
Test status
Simulation time 132119217 ps
CPU time 7.08 seconds
Started Sep 01 09:01:25 AM UTC 24
Finished Sep 01 09:01:34 AM UTC 24
Peak memory 222288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866498956 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2866498956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.416310990
Short name T10
Test name
Test status
Simulation time 87860940 ps
CPU time 6.13 seconds
Started Sep 01 08:53:40 AM UTC 24
Finished Sep 01 08:53:48 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416310990 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.416310990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.917124237
Short name T54
Test name
Test status
Simulation time 13277240997 ps
CPU time 157.18 seconds
Started Sep 01 08:54:54 AM UTC 24
Finished Sep 01 08:57:34 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=917124237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.rom_ctrl_stress_all_with_rand_reset.917124237
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3458096712
Short name T20
Test name
Test status
Simulation time 13988746051 ps
CPU time 256.33 seconds
Started Sep 01 08:59:49 AM UTC 24
Finished Sep 01 09:04:09 AM UTC 24
Peak memory 233112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3458096712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3458096712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2304030035
Short name T44
Test name
Test status
Simulation time 666854003 ps
CPU time 14.27 seconds
Started Sep 01 08:54:06 AM UTC 24
Finished Sep 01 08:54:22 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304030035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2304030035
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3655767630
Short name T6
Test name
Test status
Simulation time 535459990 ps
CPU time 9.43 seconds
Started Sep 01 08:53:13 AM UTC 24
Finished Sep 01 08:53:23 AM UTC 24
Peak memory 221288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655767630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3655767630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.427375148
Short name T48
Test name
Test status
Simulation time 262283212 ps
CPU time 16.6 seconds
Started Sep 01 08:58:09 AM UTC 24
Finished Sep 01 08:58:26 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427375148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.427375148
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2974802584
Short name T116
Test name
Test status
Simulation time 1082600471 ps
CPU time 78.81 seconds
Started Sep 01 09:02:17 AM UTC 24
Finished Sep 01 09:03:38 AM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974802584 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.2974802584
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1268602400
Short name T72
Test name
Test status
Simulation time 1309162022 ps
CPU time 28.9 seconds
Started Sep 01 09:01:08 AM UTC 24
Finished Sep 01 09:01:38 AM UTC 24
Peak memory 222452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268602400 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.1268602400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.881995152
Short name T113
Test name
Test status
Simulation time 223067074 ps
CPU time 78.23 seconds
Started Sep 01 09:02:03 AM UTC 24
Finished Sep 01 09:03:24 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881995152 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.881995152
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.480745668
Short name T62
Test name
Test status
Simulation time 690257976 ps
CPU time 6.14 seconds
Started Sep 01 09:01:16 AM UTC 24
Finished Sep 01 09:01:23 AM UTC 24
Peak memory 222356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480745668 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.480745668
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.635381103
Short name T2
Test name
Test status
Simulation time 187424933 ps
CPU time 8.24 seconds
Started Sep 01 08:52:43 AM UTC 24
Finished Sep 01 08:52:52 AM UTC 24
Peak memory 221344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635381103 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.635381103
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1451801440
Short name T89
Test name
Test status
Simulation time 138663663 ps
CPU time 9.6 seconds
Started Sep 01 08:57:39 AM UTC 24
Finished Sep 01 08:57:50 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451801440 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1451801440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1813716945
Short name T63
Test name
Test status
Simulation time 175140390 ps
CPU time 5.09 seconds
Started Sep 01 09:01:18 AM UTC 24
Finished Sep 01 09:01:24 AM UTC 24
Peak memory 222412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813716945 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.1813716945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1003986368
Short name T64
Test name
Test status
Simulation time 521353149 ps
CPU time 7.41 seconds
Started Sep 01 09:01:16 AM UTC 24
Finished Sep 01 09:01:24 AM UTC 24
Peak memory 229768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003986368 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.1003986368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3092739889
Short name T69
Test name
Test status
Simulation time 511542783 ps
CPU time 11.3 seconds
Started Sep 01 09:01:14 AM UTC 24
Finished Sep 01 09:01:26 AM UTC 24
Peak memory 229768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092739889 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.3092739889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1364319151
Short name T361
Test name
Test status
Simulation time 143458669 ps
CPU time 8.32 seconds
Started Sep 01 09:01:19 AM UTC 24
Finished Sep 01 09:01:28 AM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1364319151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
om_ctrl_csr_mem_rw_with_rand_reset.1364319151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3476100707
Short name T358
Test name
Test status
Simulation time 175309059 ps
CPU time 6.3 seconds
Started Sep 01 09:01:11 AM UTC 24
Finished Sep 01 09:01:18 AM UTC 24
Peak memory 222104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476100707 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.3476100707
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.614225687
Short name T357
Test name
Test status
Simulation time 270258126 ps
CPU time 6.16 seconds
Started Sep 01 09:01:11 AM UTC 24
Finished Sep 01 09:01:18 AM UTC 24
Peak memory 222284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614225687 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.614225687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.153447577
Short name T68
Test name
Test status
Simulation time 333876384 ps
CPU time 5.41 seconds
Started Sep 01 09:01:18 AM UTC 24
Finished Sep 01 09:01:24 AM UTC 24
Peak memory 222364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153447577 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.153447577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2367620566
Short name T359
Test name
Test status
Simulation time 378763257 ps
CPU time 14.91 seconds
Started Sep 01 09:01:09 AM UTC 24
Finished Sep 01 09:01:26 AM UTC 24
Peak memory 228532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367620566 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2367620566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1984265203
Short name T70
Test name
Test status
Simulation time 517698810 ps
CPU time 5.37 seconds
Started Sep 01 09:01:27 AM UTC 24
Finished Sep 01 09:01:33 AM UTC 24
Peak memory 222348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984265203 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.1984265203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2284437355
Short name T366
Test name
Test status
Simulation time 498182084 ps
CPU time 7.2 seconds
Started Sep 01 09:01:26 AM UTC 24
Finished Sep 01 09:01:34 AM UTC 24
Peak memory 222412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284437355 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.2284437355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1591719625
Short name T73
Test name
Test status
Simulation time 949322779 ps
CPU time 14.81 seconds
Started Sep 01 09:01:24 AM UTC 24
Finished Sep 01 09:01:40 AM UTC 24
Peak memory 222284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591719625 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.1591719625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1096155215
Short name T365
Test name
Test status
Simulation time 354290328 ps
CPU time 5.68 seconds
Started Sep 01 09:01:27 AM UTC 24
Finished Sep 01 09:01:34 AM UTC 24
Peak memory 224464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1096155215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
om_ctrl_csr_mem_rw_with_rand_reset.1096155215
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.364831729
Short name T364
Test name
Test status
Simulation time 178055478 ps
CPU time 7.09 seconds
Started Sep 01 09:01:24 AM UTC 24
Finished Sep 01 09:01:32 AM UTC 24
Peak memory 222232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364831729 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.364831729
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1313533196
Short name T362
Test name
Test status
Simulation time 89188724 ps
CPU time 6.33 seconds
Started Sep 01 09:01:23 AM UTC 24
Finished Sep 01 09:01:31 AM UTC 24
Peak memory 222224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313533196 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.1313533196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3933171709
Short name T81
Test name
Test status
Simulation time 566721070 ps
CPU time 40.36 seconds
Started Sep 01 09:01:19 AM UTC 24
Finished Sep 01 09:02:01 AM UTC 24
Peak memory 222384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933171709 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.3933171709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1184132639
Short name T99
Test name
Test status
Simulation time 384334073 ps
CPU time 9.21 seconds
Started Sep 01 09:01:27 AM UTC 24
Finished Sep 01 09:01:37 AM UTC 24
Peak memory 222348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184132639 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.1184132639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1619498850
Short name T363
Test name
Test status
Simulation time 130938060 ps
CPU time 10.76 seconds
Started Sep 01 09:01:20 AM UTC 24
Finished Sep 01 09:01:32 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619498850 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1619498850
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1115505719
Short name T58
Test name
Test status
Simulation time 244357921 ps
CPU time 41.53 seconds
Started Sep 01 09:01:23 AM UTC 24
Finished Sep 01 09:02:06 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115505719 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.1115505719
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.408560767
Short name T406
Test name
Test status
Simulation time 410651936 ps
CPU time 7.07 seconds
Started Sep 01 09:02:02 AM UTC 24
Finished Sep 01 09:02:11 AM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=408560767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.r
om_ctrl_csr_mem_rw_with_rand_reset.408560767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.880491925
Short name T405
Test name
Test status
Simulation time 518955104 ps
CPU time 7.18 seconds
Started Sep 01 09:02:02 AM UTC 24
Finished Sep 01 09:02:11 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880491925 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.880491925
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2148735274
Short name T440
Test name
Test status
Simulation time 1095977325 ps
CPU time 28.51 seconds
Started Sep 01 09:02:01 AM UTC 24
Finished Sep 01 09:02:31 AM UTC 24
Peak memory 222316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148735274 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.2148735274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3911139972
Short name T404
Test name
Test status
Simulation time 347973506 ps
CPU time 6.33 seconds
Started Sep 01 09:02:02 AM UTC 24
Finished Sep 01 09:02:10 AM UTC 24
Peak memory 229372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911139972 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.3911139972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2413472315
Short name T408
Test name
Test status
Simulation time 145792072 ps
CPU time 9.27 seconds
Started Sep 01 09:02:01 AM UTC 24
Finished Sep 01 09:02:12 AM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413472315 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2413472315
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.237219915
Short name T115
Test name
Test status
Simulation time 800977906 ps
CPU time 48.32 seconds
Started Sep 01 09:02:01 AM UTC 24
Finished Sep 01 09:02:51 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237219915 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.237219915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3994365948
Short name T411
Test name
Test status
Simulation time 504353248 ps
CPU time 6.8 seconds
Started Sep 01 09:02:05 AM UTC 24
Finished Sep 01 09:02:13 AM UTC 24
Peak memory 224400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3994365948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rom_ctrl_csr_mem_rw_with_rand_reset.3994365948
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.573617928
Short name T407
Test name
Test status
Simulation time 86791837 ps
CPU time 6.12 seconds
Started Sep 01 09:02:03 AM UTC 24
Finished Sep 01 09:02:11 AM UTC 24
Peak memory 222280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573617928 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.573617928
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4016406917
Short name T88
Test name
Test status
Simulation time 1073142601 ps
CPU time 22.88 seconds
Started Sep 01 09:02:02 AM UTC 24
Finished Sep 01 09:02:27 AM UTC 24
Peak memory 222316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016406917 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.4016406917
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.61480211
Short name T409
Test name
Test status
Simulation time 128709783 ps
CPU time 5.55 seconds
Started Sep 01 09:02:05 AM UTC 24
Finished Sep 01 09:02:11 AM UTC 24
Peak memory 222420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61480211 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.61480211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2389109509
Short name T413
Test name
Test status
Simulation time 367606061 ps
CPU time 10.39 seconds
Started Sep 01 09:02:03 AM UTC 24
Finished Sep 01 09:02:15 AM UTC 24
Peak memory 228456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389109509 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2389109509
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2744549015
Short name T415
Test name
Test status
Simulation time 534255567 ps
CPU time 6.9 seconds
Started Sep 01 09:02:07 AM UTC 24
Finished Sep 01 09:02:15 AM UTC 24
Peak memory 229900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2744549015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rom_ctrl_csr_mem_rw_with_rand_reset.2744549015
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4034272805
Short name T412
Test name
Test status
Simulation time 1186174347 ps
CPU time 5.04 seconds
Started Sep 01 09:02:07 AM UTC 24
Finished Sep 01 09:02:13 AM UTC 24
Peak memory 222416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034272805 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4034272805
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2280854815
Short name T449
Test name
Test status
Simulation time 550000277 ps
CPU time 31.7 seconds
Started Sep 01 09:02:06 AM UTC 24
Finished Sep 01 09:02:39 AM UTC 24
Peak memory 222456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280854815 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.2280854815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.571215124
Short name T416
Test name
Test status
Simulation time 97078127 ps
CPU time 8.07 seconds
Started Sep 01 09:02:07 AM UTC 24
Finished Sep 01 09:02:16 AM UTC 24
Peak memory 222296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571215124 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.571215124
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2234497989
Short name T417
Test name
Test status
Simulation time 127441471 ps
CPU time 10 seconds
Started Sep 01 09:02:07 AM UTC 24
Finished Sep 01 09:02:18 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234497989 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2234497989
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.831560843
Short name T110
Test name
Test status
Simulation time 206335480 ps
CPU time 35.58 seconds
Started Sep 01 09:02:07 AM UTC 24
Finished Sep 01 09:02:44 AM UTC 24
Peak memory 224408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831560843 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.831560843
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3834927012
Short name T423
Test name
Test status
Simulation time 511592899 ps
CPU time 10.03 seconds
Started Sep 01 09:02:10 AM UTC 24
Finished Sep 01 09:02:21 AM UTC 24
Peak memory 226576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3834927012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rom_ctrl_csr_mem_rw_with_rand_reset.3834927012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2116006540
Short name T87
Test name
Test status
Simulation time 541452731 ps
CPU time 6.76 seconds
Started Sep 01 09:02:08 AM UTC 24
Finished Sep 01 09:02:16 AM UTC 24
Peak memory 222288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116006540 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2116006540
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1588168626
Short name T450
Test name
Test status
Simulation time 561909737 ps
CPU time 31.16 seconds
Started Sep 01 09:02:07 AM UTC 24
Finished Sep 01 09:02:40 AM UTC 24
Peak memory 222392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588168626 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.1588168626
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3556991568
Short name T414
Test name
Test status
Simulation time 251607523 ps
CPU time 5.58 seconds
Started Sep 01 09:02:09 AM UTC 24
Finished Sep 01 09:02:15 AM UTC 24
Peak memory 229108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556991568 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.3556991568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2894780942
Short name T422
Test name
Test status
Simulation time 1241420374 ps
CPU time 10.63 seconds
Started Sep 01 09:02:08 AM UTC 24
Finished Sep 01 09:02:20 AM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894780942 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2894780942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2645861573
Short name T456
Test name
Test status
Simulation time 258210481 ps
CPU time 73.99 seconds
Started Sep 01 09:02:08 AM UTC 24
Finished Sep 01 09:03:24 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645861573 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.2645861573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1118938194
Short name T418
Test name
Test status
Simulation time 558689014 ps
CPU time 5.31 seconds
Started Sep 01 09:02:12 AM UTC 24
Finished Sep 01 09:02:19 AM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1118938194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rom_ctrl_csr_mem_rw_with_rand_reset.1118938194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1462188280
Short name T419
Test name
Test status
Simulation time 89048976 ps
CPU time 6.14 seconds
Started Sep 01 09:02:12 AM UTC 24
Finished Sep 01 09:02:20 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462188280 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1462188280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2208207323
Short name T451
Test name
Test status
Simulation time 1003588779 ps
CPU time 28.61 seconds
Started Sep 01 09:02:11 AM UTC 24
Finished Sep 01 09:02:41 AM UTC 24
Peak memory 222388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208207323 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.2208207323
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4239210934
Short name T420
Test name
Test status
Simulation time 190891894 ps
CPU time 6.26 seconds
Started Sep 01 09:02:12 AM UTC 24
Finished Sep 01 09:02:20 AM UTC 24
Peak memory 229748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239210934 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.4239210934
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2398668721
Short name T424
Test name
Test status
Simulation time 163686738 ps
CPU time 9.25 seconds
Started Sep 01 09:02:11 AM UTC 24
Finished Sep 01 09:02:21 AM UTC 24
Peak memory 228532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398668721 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2398668721
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1729648832
Short name T457
Test name
Test status
Simulation time 658135452 ps
CPU time 74.51 seconds
Started Sep 01 09:02:12 AM UTC 24
Finished Sep 01 09:03:28 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729648832 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.1729648832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.325012747
Short name T427
Test name
Test status
Simulation time 351008435 ps
CPU time 5.7 seconds
Started Sep 01 09:02:16 AM UTC 24
Finished Sep 01 09:02:23 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=325012747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.r
om_ctrl_csr_mem_rw_with_rand_reset.325012747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4246158437
Short name T426
Test name
Test status
Simulation time 256210098 ps
CPU time 7.1 seconds
Started Sep 01 09:02:13 AM UTC 24
Finished Sep 01 09:02:22 AM UTC 24
Peak memory 229900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246158437 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4246158437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.804694644
Short name T85
Test name
Test status
Simulation time 1815911932 ps
CPU time 26.5 seconds
Started Sep 01 09:02:12 AM UTC 24
Finished Sep 01 09:02:40 AM UTC 24
Peak memory 222248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804694644 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.804694644
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3022657794
Short name T421
Test name
Test status
Simulation time 593265159 ps
CPU time 3.96 seconds
Started Sep 01 09:02:14 AM UTC 24
Finished Sep 01 09:02:20 AM UTC 24
Peak memory 222352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022657794 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.3022657794
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1829097046
Short name T428
Test name
Test status
Simulation time 520517526 ps
CPU time 9 seconds
Started Sep 01 09:02:13 AM UTC 24
Finished Sep 01 09:02:24 AM UTC 24
Peak memory 229804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829097046 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1829097046
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.235444940
Short name T454
Test name
Test status
Simulation time 249169579 ps
CPU time 55.67 seconds
Started Sep 01 09:02:13 AM UTC 24
Finished Sep 01 09:03:11 AM UTC 24
Peak memory 222420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235444940 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.235444940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2316834269
Short name T437
Test name
Test status
Simulation time 5511311266 ps
CPU time 9.16 seconds
Started Sep 01 09:02:20 AM UTC 24
Finished Sep 01 09:02:31 AM UTC 24
Peak memory 229904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2316834269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rom_ctrl_csr_mem_rw_with_rand_reset.2316834269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.222111557
Short name T430
Test name
Test status
Simulation time 266934475 ps
CPU time 7.22 seconds
Started Sep 01 09:02:18 AM UTC 24
Finished Sep 01 09:02:26 AM UTC 24
Peak memory 222288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222111557 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.222111557
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.727697796
Short name T448
Test name
Test status
Simulation time 1453591389 ps
CPU time 19.38 seconds
Started Sep 01 09:02:17 AM UTC 24
Finished Sep 01 09:02:37 AM UTC 24
Peak memory 222384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727697796 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.727697796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1332388528
Short name T431
Test name
Test status
Simulation time 128699146 ps
CPU time 6.58 seconds
Started Sep 01 09:02:19 AM UTC 24
Finished Sep 01 09:02:27 AM UTC 24
Peak memory 222480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332388528 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.1332388528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3156639825
Short name T439
Test name
Test status
Simulation time 127635550 ps
CPU time 12.8 seconds
Started Sep 01 09:02:17 AM UTC 24
Finished Sep 01 09:02:31 AM UTC 24
Peak memory 228528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156639825 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3156639825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1958824436
Short name T432
Test name
Test status
Simulation time 132216986 ps
CPU time 5.18 seconds
Started Sep 01 09:02:23 AM UTC 24
Finished Sep 01 09:02:29 AM UTC 24
Peak memory 226640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1958824436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rom_ctrl_csr_mem_rw_with_rand_reset.1958824436
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.975752243
Short name T433
Test name
Test status
Simulation time 498769967 ps
CPU time 6.4 seconds
Started Sep 01 09:02:21 AM UTC 24
Finished Sep 01 09:02:29 AM UTC 24
Peak memory 222352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975752243 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.975752243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1496802996
Short name T452
Test name
Test status
Simulation time 828331402 ps
CPU time 31.08 seconds
Started Sep 01 09:02:20 AM UTC 24
Finished Sep 01 09:02:53 AM UTC 24
Peak memory 222520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496802996 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.1496802996
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.376815997
Short name T435
Test name
Test status
Simulation time 2069622759 ps
CPU time 7.84 seconds
Started Sep 01 09:02:21 AM UTC 24
Finished Sep 01 09:02:30 AM UTC 24
Peak memory 222360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376815997 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.376815997
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2863080696
Short name T442
Test name
Test status
Simulation time 256879229 ps
CPU time 11.4 seconds
Started Sep 01 09:02:20 AM UTC 24
Finished Sep 01 09:02:33 AM UTC 24
Peak memory 228740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863080696 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2863080696
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.836977026
Short name T112
Test name
Test status
Simulation time 666140058 ps
CPU time 44.72 seconds
Started Sep 01 09:02:20 AM UTC 24
Finished Sep 01 09:03:07 AM UTC 24
Peak memory 222288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836977026 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.836977026
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3504082024
Short name T441
Test name
Test status
Simulation time 139518188 ps
CPU time 5.66 seconds
Started Sep 01 09:02:25 AM UTC 24
Finished Sep 01 09:02:32 AM UTC 24
Peak memory 229604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3504082024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rom_ctrl_csr_mem_rw_with_rand_reset.3504082024
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3361969958
Short name T438
Test name
Test status
Simulation time 347577110 ps
CPU time 5.84 seconds
Started Sep 01 09:02:24 AM UTC 24
Finished Sep 01 09:02:31 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361969958 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3361969958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.313094060
Short name T86
Test name
Test status
Simulation time 2230652420 ps
CPU time 34.43 seconds
Started Sep 01 09:02:23 AM UTC 24
Finished Sep 01 09:02:58 AM UTC 24
Peak memory 222448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313094060 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.313094060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.99349812
Short name T436
Test name
Test status
Simulation time 301161953 ps
CPU time 4.47 seconds
Started Sep 01 09:02:25 AM UTC 24
Finished Sep 01 09:02:30 AM UTC 24
Peak memory 228224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99349812 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.99349812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.719160593
Short name T444
Test name
Test status
Simulation time 617732696 ps
CPU time 11.81 seconds
Started Sep 01 09:02:23 AM UTC 24
Finished Sep 01 09:02:36 AM UTC 24
Peak memory 228532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719160593 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.719160593
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3936410677
Short name T117
Test name
Test status
Simulation time 220804082 ps
CPU time 93.58 seconds
Started Sep 01 09:02:24 AM UTC 24
Finished Sep 01 09:03:59 AM UTC 24
Peak memory 224408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936410677 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.3936410677
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4285135713
Short name T446
Test name
Test status
Simulation time 2215498938 ps
CPU time 5.56 seconds
Started Sep 01 09:02:29 AM UTC 24
Finished Sep 01 09:02:36 AM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4285135713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rom_ctrl_csr_mem_rw_with_rand_reset.4285135713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4234235586
Short name T84
Test name
Test status
Simulation time 538966533 ps
CPU time 5.58 seconds
Started Sep 01 09:02:27 AM UTC 24
Finished Sep 01 09:02:34 AM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234235586 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4234235586
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3051024235
Short name T453
Test name
Test status
Simulation time 15620496608 ps
CPU time 41.57 seconds
Started Sep 01 09:02:26 AM UTC 24
Finished Sep 01 09:03:09 AM UTC 24
Peak memory 222452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051024235 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.3051024235
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1536329168
Short name T445
Test name
Test status
Simulation time 96536485 ps
CPU time 7.53 seconds
Started Sep 01 09:02:27 AM UTC 24
Finished Sep 01 09:02:36 AM UTC 24
Peak memory 222280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536329168 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.1536329168
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.651213827
Short name T447
Test name
Test status
Simulation time 146375029 ps
CPU time 9.48 seconds
Started Sep 01 09:02:26 AM UTC 24
Finished Sep 01 09:02:37 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651213827 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.651213827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4106002876
Short name T455
Test name
Test status
Simulation time 591625284 ps
CPU time 48.85 seconds
Started Sep 01 09:02:27 AM UTC 24
Finished Sep 01 09:03:18 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106002876 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.4106002876
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.785471280
Short name T369
Test name
Test status
Simulation time 638362271 ps
CPU time 6.52 seconds
Started Sep 01 09:01:33 AM UTC 24
Finished Sep 01 09:01:41 AM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785471280 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.785471280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3516320040
Short name T371
Test name
Test status
Simulation time 567130640 ps
CPU time 7.84 seconds
Started Sep 01 09:01:33 AM UTC 24
Finished Sep 01 09:01:42 AM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516320040 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.3516320040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1488527795
Short name T74
Test name
Test status
Simulation time 315896201 ps
CPU time 8.92 seconds
Started Sep 01 09:01:31 AM UTC 24
Finished Sep 01 09:01:41 AM UTC 24
Peak memory 222376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488527795 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.1488527795
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3344145028
Short name T372
Test name
Test status
Simulation time 277730969 ps
CPU time 7.95 seconds
Started Sep 01 09:01:34 AM UTC 24
Finished Sep 01 09:01:44 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3344145028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
om_ctrl_csr_mem_rw_with_rand_reset.3344145028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3157379465
Short name T105
Test name
Test status
Simulation time 85971779 ps
CPU time 6.18 seconds
Started Sep 01 09:01:33 AM UTC 24
Finished Sep 01 09:01:41 AM UTC 24
Peak memory 222352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157379465 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3157379465
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1717517288
Short name T368
Test name
Test status
Simulation time 497674068 ps
CPU time 5.85 seconds
Started Sep 01 09:01:31 AM UTC 24
Finished Sep 01 09:01:38 AM UTC 24
Peak memory 222204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717517288 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.1717517288
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1418986249
Short name T367
Test name
Test status
Simulation time 171950860 ps
CPU time 6.45 seconds
Started Sep 01 09:01:29 AM UTC 24
Finished Sep 01 09:01:37 AM UTC 24
Peak memory 222224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418986249 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.1418986249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4137714491
Short name T82
Test name
Test status
Simulation time 782459593 ps
CPU time 33.94 seconds
Started Sep 01 09:01:27 AM UTC 24
Finished Sep 01 09:02:02 AM UTC 24
Peak memory 222384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137714491 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.4137714491
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3047452155
Short name T75
Test name
Test status
Simulation time 519815257 ps
CPU time 6.37 seconds
Started Sep 01 09:01:34 AM UTC 24
Finished Sep 01 09:01:42 AM UTC 24
Peak memory 228880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047452155 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.3047452155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1119978220
Short name T370
Test name
Test status
Simulation time 88881220 ps
CPU time 12.24 seconds
Started Sep 01 09:01:28 AM UTC 24
Finished Sep 01 09:01:41 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119978220 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1119978220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2140597436
Short name T121
Test name
Test status
Simulation time 897213193 ps
CPU time 87.67 seconds
Started Sep 01 09:01:29 AM UTC 24
Finished Sep 01 09:02:59 AM UTC 24
Peak memory 224400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140597436 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.2140597436
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3449849916
Short name T376
Test name
Test status
Simulation time 542419386 ps
CPU time 6.34 seconds
Started Sep 01 09:01:41 AM UTC 24
Finished Sep 01 09:01:48 AM UTC 24
Peak memory 222284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449849916 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.3449849916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1521200323
Short name T375
Test name
Test status
Simulation time 2348565294 ps
CPU time 7.31 seconds
Started Sep 01 09:01:39 AM UTC 24
Finished Sep 01 09:01:47 AM UTC 24
Peak memory 229760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521200323 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.1521200323
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4158387925
Short name T374
Test name
Test status
Simulation time 176940199 ps
CPU time 7.08 seconds
Started Sep 01 09:01:38 AM UTC 24
Finished Sep 01 09:01:46 AM UTC 24
Peak memory 222348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158387925 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.4158387925
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1684516428
Short name T379
Test name
Test status
Simulation time 132106586 ps
CPU time 7.07 seconds
Started Sep 01 09:01:41 AM UTC 24
Finished Sep 01 09:01:49 AM UTC 24
Peak memory 226640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1684516428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
om_ctrl_csr_mem_rw_with_rand_reset.1684516428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3650159060
Short name T79
Test name
Test status
Simulation time 567113912 ps
CPU time 6.02 seconds
Started Sep 01 09:01:39 AM UTC 24
Finished Sep 01 09:01:46 AM UTC 24
Peak memory 222352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650159060 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3650159060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2362259547
Short name T373
Test name
Test status
Simulation time 148780055 ps
CPU time 6.96 seconds
Started Sep 01 09:01:38 AM UTC 24
Finished Sep 01 09:01:46 AM UTC 24
Peak memory 222100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362259547 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.2362259547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3391706690
Short name T377
Test name
Test status
Simulation time 974205344 ps
CPU time 10.64 seconds
Started Sep 01 09:01:37 AM UTC 24
Finished Sep 01 09:01:48 AM UTC 24
Peak memory 222224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391706690 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.3391706690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1809287145
Short name T83
Test name
Test status
Simulation time 1038276243 ps
CPU time 31.27 seconds
Started Sep 01 09:01:35 AM UTC 24
Finished Sep 01 09:02:07 AM UTC 24
Peak memory 222312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809287145 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.1809287145
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1510489162
Short name T100
Test name
Test status
Simulation time 142719098 ps
CPU time 5.69 seconds
Started Sep 01 09:01:41 AM UTC 24
Finished Sep 01 09:01:48 AM UTC 24
Peak memory 229304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510489162 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.1510489162
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3647908484
Short name T378
Test name
Test status
Simulation time 309952125 ps
CPU time 13.09 seconds
Started Sep 01 09:01:35 AM UTC 24
Finished Sep 01 09:01:49 AM UTC 24
Peak memory 228532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647908484 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3647908484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1272983722
Short name T111
Test name
Test status
Simulation time 845502549 ps
CPU time 74.44 seconds
Started Sep 01 09:01:36 AM UTC 24
Finished Sep 01 09:02:52 AM UTC 24
Peak memory 224464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272983722 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.1272983722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2426784434
Short name T380
Test name
Test status
Simulation time 250939824 ps
CPU time 4.83 seconds
Started Sep 01 09:01:45 AM UTC 24
Finished Sep 01 09:01:51 AM UTC 24
Peak memory 222284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426784434 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.2426784434
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2521072916
Short name T382
Test name
Test status
Simulation time 127192257 ps
CPU time 5.43 seconds
Started Sep 01 09:01:45 AM UTC 24
Finished Sep 01 09:01:51 AM UTC 24
Peak memory 222348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521072916 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.2521072916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1687654920
Short name T384
Test name
Test status
Simulation time 344348023 ps
CPU time 7.01 seconds
Started Sep 01 09:01:44 AM UTC 24
Finished Sep 01 09:01:52 AM UTC 24
Peak memory 222348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687654920 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.1687654920
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1089476995
Short name T387
Test name
Test status
Simulation time 544343605 ps
CPU time 7.65 seconds
Started Sep 01 09:01:47 AM UTC 24
Finished Sep 01 09:01:56 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1089476995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
om_ctrl_csr_mem_rw_with_rand_reset.1089476995
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1201046804
Short name T385
Test name
Test status
Simulation time 1046557985 ps
CPU time 5.86 seconds
Started Sep 01 09:01:45 AM UTC 24
Finished Sep 01 09:01:52 AM UTC 24
Peak memory 222352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201046804 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1201046804
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3552964614
Short name T383
Test name
Test status
Simulation time 260397226 ps
CPU time 6.86 seconds
Started Sep 01 09:01:44 AM UTC 24
Finished Sep 01 09:01:51 AM UTC 24
Peak memory 222172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552964614 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.3552964614
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.312932672
Short name T381
Test name
Test status
Simulation time 214064569 ps
CPU time 7.32 seconds
Started Sep 01 09:01:42 AM UTC 24
Finished Sep 01 09:01:51 AM UTC 24
Peak memory 222220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312932672 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.312932672
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1399209736
Short name T396
Test name
Test status
Simulation time 1494439925 ps
CPU time 19.87 seconds
Started Sep 01 09:01:42 AM UTC 24
Finished Sep 01 09:02:03 AM UTC 24
Peak memory 222448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399209736 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1399209736
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3853873280
Short name T101
Test name
Test status
Simulation time 550571841 ps
CPU time 7.65 seconds
Started Sep 01 09:01:47 AM UTC 24
Finished Sep 01 09:01:56 AM UTC 24
Peak memory 222348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853873280 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.3853873280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1487776883
Short name T386
Test name
Test status
Simulation time 351316749 ps
CPU time 9.22 seconds
Started Sep 01 09:01:42 AM UTC 24
Finished Sep 01 09:01:53 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487776883 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1487776883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2041833244
Short name T390
Test name
Test status
Simulation time 269786544 ps
CPU time 9.12 seconds
Started Sep 01 09:01:49 AM UTC 24
Finished Sep 01 09:01:59 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2041833244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
om_ctrl_csr_mem_rw_with_rand_reset.2041833244
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1179426163
Short name T389
Test name
Test status
Simulation time 521728462 ps
CPU time 7.65 seconds
Started Sep 01 09:01:49 AM UTC 24
Finished Sep 01 09:01:58 AM UTC 24
Peak memory 222288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179426163 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1179426163
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1410127116
Short name T429
Test name
Test status
Simulation time 3167300631 ps
CPU time 36.52 seconds
Started Sep 01 09:01:47 AM UTC 24
Finished Sep 01 09:02:25 AM UTC 24
Peak memory 222448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410127116 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.1410127116
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.445125631
Short name T102
Test name
Test status
Simulation time 544855301 ps
CPU time 6.55 seconds
Started Sep 01 09:01:49 AM UTC 24
Finished Sep 01 09:01:57 AM UTC 24
Peak memory 222288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445125631 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.445125631
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.316278082
Short name T388
Test name
Test status
Simulation time 461083162 ps
CPU time 8.32 seconds
Started Sep 01 09:01:48 AM UTC 24
Finished Sep 01 09:01:57 AM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316278082 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.316278082
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.472245558
Short name T60
Test name
Test status
Simulation time 238531065 ps
CPU time 46.78 seconds
Started Sep 01 09:01:49 AM UTC 24
Finished Sep 01 09:02:37 AM UTC 24
Peak memory 224404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472245558 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.472245558
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1910403958
Short name T393
Test name
Test status
Simulation time 104228475 ps
CPU time 9 seconds
Started Sep 01 09:01:52 AM UTC 24
Finished Sep 01 09:02:02 AM UTC 24
Peak memory 228496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1910403958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
om_ctrl_csr_mem_rw_with_rand_reset.1910403958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1545665049
Short name T80
Test name
Test status
Simulation time 483919038 ps
CPU time 6.41 seconds
Started Sep 01 09:01:52 AM UTC 24
Finished Sep 01 09:01:59 AM UTC 24
Peak memory 222352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545665049 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1545665049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1150380207
Short name T410
Test name
Test status
Simulation time 1283101749 ps
CPU time 20.72 seconds
Started Sep 01 09:01:50 AM UTC 24
Finished Sep 01 09:02:12 AM UTC 24
Peak memory 222384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150380207 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.1150380207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3831770401
Short name T103
Test name
Test status
Simulation time 518921666 ps
CPU time 7.18 seconds
Started Sep 01 09:01:52 AM UTC 24
Finished Sep 01 09:02:00 AM UTC 24
Peak memory 229192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831770401 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.3831770401
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2952927812
Short name T394
Test name
Test status
Simulation time 521026808 ps
CPU time 10.34 seconds
Started Sep 01 09:01:50 AM UTC 24
Finished Sep 01 09:02:02 AM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952927812 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2952927812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1366876917
Short name T122
Test name
Test status
Simulation time 2429441505 ps
CPU time 92.94 seconds
Started Sep 01 09:01:51 AM UTC 24
Finished Sep 01 09:03:25 AM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366876917 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.1366876917
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2960641005
Short name T392
Test name
Test status
Simulation time 322371288 ps
CPU time 7.32 seconds
Started Sep 01 09:01:53 AM UTC 24
Finished Sep 01 09:02:02 AM UTC 24
Peak memory 226640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2960641005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
om_ctrl_csr_mem_rw_with_rand_reset.2960641005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2956021406
Short name T391
Test name
Test status
Simulation time 361483199 ps
CPU time 6.11 seconds
Started Sep 01 09:01:53 AM UTC 24
Finished Sep 01 09:02:00 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956021406 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2956021406
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3107451606
Short name T443
Test name
Test status
Simulation time 819880769 ps
CPU time 41.62 seconds
Started Sep 01 09:01:52 AM UTC 24
Finished Sep 01 09:02:35 AM UTC 24
Peak memory 222448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107451606 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.3107451606
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.217602218
Short name T104
Test name
Test status
Simulation time 131811141 ps
CPU time 7.01 seconds
Started Sep 01 09:01:53 AM UTC 24
Finished Sep 01 09:02:01 AM UTC 24
Peak memory 222428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217602218 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.217602218
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3748801501
Short name T395
Test name
Test status
Simulation time 260198239 ps
CPU time 8.27 seconds
Started Sep 01 09:01:53 AM UTC 24
Finished Sep 01 09:02:02 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748801501 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3748801501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.916815310
Short name T118
Test name
Test status
Simulation time 206057895 ps
CPU time 47.54 seconds
Started Sep 01 09:01:53 AM UTC 24
Finished Sep 01 09:02:42 AM UTC 24
Peak memory 229776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916815310 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.916815310
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1003715131
Short name T400
Test name
Test status
Simulation time 95255992 ps
CPU time 6.93 seconds
Started Sep 01 09:01:59 AM UTC 24
Finished Sep 01 09:02:07 AM UTC 24
Peak memory 229812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1003715131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
om_ctrl_csr_mem_rw_with_rand_reset.1003715131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2403715518
Short name T397
Test name
Test status
Simulation time 245103534 ps
CPU time 6.85 seconds
Started Sep 01 09:01:57 AM UTC 24
Finished Sep 01 09:02:06 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403715518 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2403715518
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3039580936
Short name T434
Test name
Test status
Simulation time 824987071 ps
CPU time 33.79 seconds
Started Sep 01 09:01:54 AM UTC 24
Finished Sep 01 09:02:30 AM UTC 24
Peak memory 222384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039580936 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.3039580936
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1404538780
Short name T398
Test name
Test status
Simulation time 958952240 ps
CPU time 6.24 seconds
Started Sep 01 09:01:58 AM UTC 24
Finished Sep 01 09:02:06 AM UTC 24
Peak memory 229424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404538780 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.1404538780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3505394089
Short name T360
Test name
Test status
Simulation time 516816258 ps
CPU time 8.96 seconds
Started Sep 01 09:01:56 AM UTC 24
Finished Sep 01 09:02:06 AM UTC 24
Peak memory 228340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505394089 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3505394089
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.129474277
Short name T120
Test name
Test status
Simulation time 727784174 ps
CPU time 41.08 seconds
Started Sep 01 09:01:56 AM UTC 24
Finished Sep 01 09:02:39 AM UTC 24
Peak memory 224324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129474277 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.129474277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.477134296
Short name T401
Test name
Test status
Simulation time 350231603 ps
CPU time 5.48 seconds
Started Sep 01 09:02:01 AM UTC 24
Finished Sep 01 09:02:08 AM UTC 24
Peak memory 224408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=477134296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ro
m_ctrl_csr_mem_rw_with_rand_reset.477134296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.333974518
Short name T399
Test name
Test status
Simulation time 362991282 ps
CPU time 5.19 seconds
Started Sep 01 09:02:00 AM UTC 24
Finished Sep 01 09:02:07 AM UTC 24
Peak memory 221984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333974518 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.333974518
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.204809303
Short name T425
Test name
Test status
Simulation time 2367362444 ps
CPU time 21.72 seconds
Started Sep 01 09:01:59 AM UTC 24
Finished Sep 01 09:02:22 AM UTC 24
Peak memory 222452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204809303 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.204809303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1779649000
Short name T402
Test name
Test status
Simulation time 1125368184 ps
CPU time 6.7 seconds
Started Sep 01 09:02:01 AM UTC 24
Finished Sep 01 09:02:09 AM UTC 24
Peak memory 222476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779649000 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.1779649000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.925969689
Short name T403
Test name
Test status
Simulation time 87322995 ps
CPU time 9.38 seconds
Started Sep 01 09:01:59 AM UTC 24
Finished Sep 01 09:02:09 AM UTC 24
Peak memory 226552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925969689 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.925969689
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2575875963
Short name T114
Test name
Test status
Simulation time 670520267 ps
CPU time 46.98 seconds
Started Sep 01 09:02:00 AM UTC 24
Finished Sep 01 09:02:49 AM UTC 24
Peak memory 229432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575875963 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.2575875963
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.546625030
Short name T5
Test name
Test status
Simulation time 168227614 ps
CPU time 6.26 seconds
Started Sep 01 08:53:10 AM UTC 24
Finished Sep 01 08:53:17 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546625030 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.546625030
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.752999061
Short name T4
Test name
Test status
Simulation time 693181552 ps
CPU time 14.47 seconds
Started Sep 01 08:52:53 AM UTC 24
Finished Sep 01 08:53:09 AM UTC 24
Peak memory 221356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752999061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.752999061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2622306654
Short name T18
Test name
Test status
Simulation time 2295698316 ps
CPU time 83.36 seconds
Started Sep 01 08:53:04 AM UTC 24
Finished Sep 01 08:54:29 AM UTC 24
Peak memory 257620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622306654 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2622306654
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.343708969
Short name T1
Test name
Test status
Simulation time 368244473 ps
CPU time 8.26 seconds
Started Sep 01 08:52:34 AM UTC 24
Finished Sep 01 08:52:43 AM UTC 24
Peak memory 221484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343708969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.343708969
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.661156700
Short name T22
Test name
Test status
Simulation time 13029375757 ps
CPU time 111.27 seconds
Started Sep 01 08:53:19 AM UTC 24
Finished Sep 01 08:55:12 AM UTC 24
Peak memory 257420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661156700 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.661156700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1281772852
Short name T8
Test name
Test status
Simulation time 699506930 ps
CPU time 14.75 seconds
Started Sep 01 08:53:24 AM UTC 24
Finished Sep 01 08:53:40 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281772852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1281772852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.569010302
Short name T7
Test name
Test status
Simulation time 1637719311 ps
CPU time 9.28 seconds
Started Sep 01 08:53:18 AM UTC 24
Finished Sep 01 08:53:28 AM UTC 24
Peak memory 221344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569010302 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.569010302
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3465721706
Short name T9
Test name
Test status
Simulation time 296590484 ps
CPU time 21.03 seconds
Started Sep 01 08:53:18 AM UTC 24
Finished Sep 01 08:53:40 AM UTC 24
Peak memory 225520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346572170
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.3465721706
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1789351053
Short name T16
Test name
Test status
Simulation time 36690828242 ps
CPU time 133.48 seconds
Started Sep 01 08:53:29 AM UTC 24
Finished Sep 01 08:55:45 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1789351053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1789351053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3979251685
Short name T143
Test name
Test status
Simulation time 195282606 ps
CPU time 5.99 seconds
Started Sep 01 08:55:45 AM UTC 24
Finished Sep 01 08:55:52 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979251685 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3979251685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1485776420
Short name T170
Test name
Test status
Simulation time 16625285907 ps
CPU time 93.85 seconds
Started Sep 01 08:55:37 AM UTC 24
Finished Sep 01 08:57:13 AM UTC 24
Peak memory 257488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485776420 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.1485776420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.4162669532
Short name T144
Test name
Test status
Simulation time 171988702 ps
CPU time 14.51 seconds
Started Sep 01 08:55:38 AM UTC 24
Finished Sep 01 08:55:54 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162669532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4162669532
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.441561273
Short name T127
Test name
Test status
Simulation time 577627743 ps
CPU time 9.14 seconds
Started Sep 01 08:55:33 AM UTC 24
Finished Sep 01 08:55:43 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441561273 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.441561273
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.82132044
Short name T142
Test name
Test status
Simulation time 252193325 ps
CPU time 16.58 seconds
Started Sep 01 08:55:33 AM UTC 24
Finished Sep 01 08:55:51 AM UTC 24
Peak memory 221344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82132044
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.82132044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.420715061
Short name T212
Test name
Test status
Simulation time 18393072368 ps
CPU time 188.13 seconds
Started Sep 01 08:55:44 AM UTC 24
Finished Sep 01 08:58:55 AM UTC 24
Peak memory 246536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=420715061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.rom_ctrl_stress_all_with_rand_reset.420715061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3385120360
Short name T130
Test name
Test status
Simulation time 334758533 ps
CPU time 5.97 seconds
Started Sep 01 08:55:55 AM UTC 24
Finished Sep 01 08:56:02 AM UTC 24
Peak memory 221392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385120360 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3385120360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1419703954
Short name T206
Test name
Test status
Simulation time 1812264466 ps
CPU time 171.74 seconds
Started Sep 01 08:55:51 AM UTC 24
Finished Sep 01 08:58:46 AM UTC 24
Peak memory 257120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419703954 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.1419703954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2728145585
Short name T147
Test name
Test status
Simulation time 509281774 ps
CPU time 16.62 seconds
Started Sep 01 08:55:53 AM UTC 24
Finished Sep 01 08:56:10 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728145585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2728145585
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2008915735
Short name T145
Test name
Test status
Simulation time 187222075 ps
CPU time 8.34 seconds
Started Sep 01 08:55:46 AM UTC 24
Finished Sep 01 08:55:56 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008915735 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2008915735
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.2367598289
Short name T136
Test name
Test status
Simulation time 224565850 ps
CPU time 14.03 seconds
Started Sep 01 08:55:46 AM UTC 24
Finished Sep 01 08:56:02 AM UTC 24
Peak memory 221688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236759828
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.2367598289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1739007660
Short name T17
Test name
Test status
Simulation time 1760371310 ps
CPU time 27.79 seconds
Started Sep 01 08:55:54 AM UTC 24
Finished Sep 01 08:56:23 AM UTC 24
Peak memory 228736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1739007660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1739007660
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.987201130
Short name T148
Test name
Test status
Simulation time 250790265 ps
CPU time 7.2 seconds
Started Sep 01 08:56:03 AM UTC 24
Finished Sep 01 08:56:11 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987201130 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.987201130
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1257231194
Short name T90
Test name
Test status
Simulation time 1963856536 ps
CPU time 109.78 seconds
Started Sep 01 08:55:59 AM UTC 24
Finished Sep 01 08:57:51 AM UTC 24
Peak memory 241996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257231194 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.1257231194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3298889073
Short name T47
Test name
Test status
Simulation time 754873595 ps
CPU time 14.6 seconds
Started Sep 01 08:56:02 AM UTC 24
Finished Sep 01 08:56:18 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298889073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3298889073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2944180071
Short name T146
Test name
Test status
Simulation time 139699520 ps
CPU time 9.47 seconds
Started Sep 01 08:55:59 AM UTC 24
Finished Sep 01 08:56:09 AM UTC 24
Peak memory 221464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944180071 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2944180071
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1711586153
Short name T128
Test name
Test status
Simulation time 272701065 ps
CPU time 14.31 seconds
Started Sep 01 08:55:57 AM UTC 24
Finished Sep 01 08:56:12 AM UTC 24
Peak memory 223480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171158615
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.1711586153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3057948264
Short name T53
Test name
Test status
Simulation time 15639519416 ps
CPU time 86.04 seconds
Started Sep 01 08:56:03 AM UTC 24
Finished Sep 01 08:57:31 AM UTC 24
Peak memory 232920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3057948264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3057948264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1621305726
Short name T149
Test name
Test status
Simulation time 89246862 ps
CPU time 6.28 seconds
Started Sep 01 08:56:12 AM UTC 24
Finished Sep 01 08:56:19 AM UTC 24
Peak memory 221456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621305726 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1621305726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1222817397
Short name T219
Test name
Test status
Simulation time 6243548570 ps
CPU time 178.37 seconds
Started Sep 01 08:56:05 AM UTC 24
Finished Sep 01 08:59:06 AM UTC 24
Peak memory 223716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222817397 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.1222817397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.669125093
Short name T151
Test name
Test status
Simulation time 498486092 ps
CPU time 12.53 seconds
Started Sep 01 08:56:08 AM UTC 24
Finished Sep 01 08:56:22 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669125093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.669125093
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.413147579
Short name T129
Test name
Test status
Simulation time 1325931122 ps
CPU time 7.25 seconds
Started Sep 01 08:56:03 AM UTC 24
Finished Sep 01 08:56:11 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413147579 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.413147579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3724416570
Short name T153
Test name
Test status
Simulation time 1054685700 ps
CPU time 22.07 seconds
Started Sep 01 08:56:03 AM UTC 24
Finished Sep 01 08:56:27 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372441657
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.3724416570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4075674577
Short name T52
Test name
Test status
Simulation time 17011622377 ps
CPU time 71.04 seconds
Started Sep 01 08:56:10 AM UTC 24
Finished Sep 01 08:57:23 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4075674577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.4075674577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1275090264
Short name T152
Test name
Test status
Simulation time 349514258 ps
CPU time 4.29 seconds
Started Sep 01 08:56:19 AM UTC 24
Finished Sep 01 08:56:24 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275090264 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1275090264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1223435269
Short name T49
Test name
Test status
Simulation time 1584517256 ps
CPU time 83.3 seconds
Started Sep 01 08:56:13 AM UTC 24
Finished Sep 01 08:57:38 AM UTC 24
Peak memory 221472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223435269 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.1223435269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.217775599
Short name T158
Test name
Test status
Simulation time 1008160164 ps
CPU time 21.26 seconds
Started Sep 01 08:56:15 AM UTC 24
Finished Sep 01 08:56:37 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217775599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.217775599
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.352715010
Short name T150
Test name
Test status
Simulation time 553921244 ps
CPU time 7.21 seconds
Started Sep 01 08:56:13 AM UTC 24
Finished Sep 01 08:56:21 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352715010 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.352715010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3343214346
Short name T134
Test name
Test status
Simulation time 4827676066 ps
CPU time 15.87 seconds
Started Sep 01 08:56:13 AM UTC 24
Finished Sep 01 08:56:30 AM UTC 24
Peak memory 223464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334321434
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.3343214346
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1379666524
Short name T281
Test name
Test status
Simulation time 6473593404 ps
CPU time 243.32 seconds
Started Sep 01 08:56:18 AM UTC 24
Finished Sep 01 09:00:25 AM UTC 24
Peak memory 245400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1379666524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1379666524
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2238754437
Short name T155
Test name
Test status
Simulation time 338114823 ps
CPU time 7.2 seconds
Started Sep 01 08:56:26 AM UTC 24
Finished Sep 01 08:56:35 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238754437 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2238754437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3714468086
Short name T156
Test name
Test status
Simulation time 498354237 ps
CPU time 10.94 seconds
Started Sep 01 08:56:23 AM UTC 24
Finished Sep 01 08:56:35 AM UTC 24
Peak memory 221416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714468086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3714468086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1956115506
Short name T154
Test name
Test status
Simulation time 145644503 ps
CPU time 9.7 seconds
Started Sep 01 08:56:22 AM UTC 24
Finished Sep 01 08:56:33 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956115506 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1956115506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.1862639658
Short name T157
Test name
Test status
Simulation time 278049604 ps
CPU time 14.22 seconds
Started Sep 01 08:56:20 AM UTC 24
Finished Sep 01 08:56:36 AM UTC 24
Peak memory 221284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186263965
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.1862639658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1373790334
Short name T242
Test name
Test status
Simulation time 22682789133 ps
CPU time 190.08 seconds
Started Sep 01 08:56:25 AM UTC 24
Finished Sep 01 08:59:38 AM UTC 24
Peak memory 245400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1373790334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1373790334
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2109820716
Short name T140
Test name
Test status
Simulation time 88951420 ps
CPU time 6.19 seconds
Started Sep 01 08:56:37 AM UTC 24
Finished Sep 01 08:56:44 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109820716 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2109820716
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.26401617
Short name T208
Test name
Test status
Simulation time 13836962142 ps
CPU time 134.11 seconds
Started Sep 01 08:56:34 AM UTC 24
Finished Sep 01 08:58:50 AM UTC 24
Peak memory 258468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26401617 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.26401617
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1703902371
Short name T161
Test name
Test status
Simulation time 876999813 ps
CPU time 11.81 seconds
Started Sep 01 08:56:36 AM UTC 24
Finished Sep 01 08:56:49 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703902371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1703902371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.4211407358
Short name T159
Test name
Test status
Simulation time 391295935 ps
CPU time 8.57 seconds
Started Sep 01 08:56:31 AM UTC 24
Finished Sep 01 08:56:40 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211407358 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4211407358
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.104504297
Short name T160
Test name
Test status
Simulation time 423154834 ps
CPU time 16.07 seconds
Started Sep 01 08:56:27 AM UTC 24
Finished Sep 01 08:56:45 AM UTC 24
Peak memory 223392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104504297
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.104504297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1862133692
Short name T222
Test name
Test status
Simulation time 3152862331 ps
CPU time 151.82 seconds
Started Sep 01 08:56:36 AM UTC 24
Finished Sep 01 08:59:10 AM UTC 24
Peak memory 232980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1862133692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1862133692
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1791744147
Short name T163
Test name
Test status
Simulation time 262658211 ps
CPU time 7.3 seconds
Started Sep 01 08:56:45 AM UTC 24
Finished Sep 01 08:56:54 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791744147 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1791744147
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1946743190
Short name T243
Test name
Test status
Simulation time 9961835535 ps
CPU time 175.96 seconds
Started Sep 01 08:56:40 AM UTC 24
Finished Sep 01 08:59:39 AM UTC 24
Peak memory 223652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946743190 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.1946743190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.553778873
Short name T46
Test name
Test status
Simulation time 1034955592 ps
CPU time 14.87 seconds
Started Sep 01 08:56:41 AM UTC 24
Finished Sep 01 08:56:57 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553778873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.553778873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2517897884
Short name T162
Test name
Test status
Simulation time 560635262 ps
CPU time 9.83 seconds
Started Sep 01 08:56:39 AM UTC 24
Finished Sep 01 08:56:50 AM UTC 24
Peak memory 221400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517897884 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2517897884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1534465086
Short name T133
Test name
Test status
Simulation time 1235371038 ps
CPU time 20.07 seconds
Started Sep 01 08:56:38 AM UTC 24
Finished Sep 01 08:56:59 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153446508
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.1534465086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1311336763
Short name T167
Test name
Test status
Simulation time 990912061 ps
CPU time 10.35 seconds
Started Sep 01 08:56:58 AM UTC 24
Finished Sep 01 08:57:09 AM UTC 24
Peak memory 221392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311336763 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1311336763
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3747820290
Short name T209
Test name
Test status
Simulation time 9997238132 ps
CPU time 116.49 seconds
Started Sep 01 08:56:52 AM UTC 24
Finished Sep 01 08:58:50 AM UTC 24
Peak memory 255076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747820290 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.3747820290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.945412841
Short name T165
Test name
Test status
Simulation time 334358186 ps
CPU time 14.36 seconds
Started Sep 01 08:56:53 AM UTC 24
Finished Sep 01 08:57:08 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945412841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.945412841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2603047371
Short name T164
Test name
Test status
Simulation time 275046197 ps
CPU time 9.79 seconds
Started Sep 01 08:56:50 AM UTC 24
Finished Sep 01 08:57:01 AM UTC 24
Peak memory 221400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603047371 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2603047371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2338891648
Short name T168
Test name
Test status
Simulation time 1978246735 ps
CPU time 18.96 seconds
Started Sep 01 08:56:49 AM UTC 24
Finished Sep 01 08:57:09 AM UTC 24
Peak memory 225720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233889164
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.2338891648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2294735183
Short name T249
Test name
Test status
Simulation time 34964165103 ps
CPU time 167.52 seconds
Started Sep 01 08:56:55 AM UTC 24
Finished Sep 01 08:59:45 AM UTC 24
Peak memory 246344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2294735183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2294735183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.645083203
Short name T171
Test name
Test status
Simulation time 176143342 ps
CPU time 6.21 seconds
Started Sep 01 08:57:09 AM UTC 24
Finished Sep 01 08:57:16 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645083203 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.645083203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.933349865
Short name T205
Test name
Test status
Simulation time 1318826390 ps
CPU time 97.74 seconds
Started Sep 01 08:57:02 AM UTC 24
Finished Sep 01 08:58:42 AM UTC 24
Peak memory 244372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933349865 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.933349865
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.4137614090
Short name T172
Test name
Test status
Simulation time 264131101 ps
CPU time 11.87 seconds
Started Sep 01 08:57:04 AM UTC 24
Finished Sep 01 08:57:17 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137614090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4137614090
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3088603528
Short name T166
Test name
Test status
Simulation time 141297108 ps
CPU time 7.44 seconds
Started Sep 01 08:57:00 AM UTC 24
Finished Sep 01 08:57:08 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088603528 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3088603528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2135182639
Short name T173
Test name
Test status
Simulation time 1135014613 ps
CPU time 17.77 seconds
Started Sep 01 08:56:59 AM UTC 24
Finished Sep 01 08:57:18 AM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213518263
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.2135182639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2341234638
Short name T199
Test name
Test status
Simulation time 7138231717 ps
CPU time 75.08 seconds
Started Sep 01 08:57:09 AM UTC 24
Finished Sep 01 08:58:26 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2341234638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2341234638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.2809537873
Short name T28
Test name
Test status
Simulation time 763431269 ps
CPU time 6.1 seconds
Started Sep 01 08:54:00 AM UTC 24
Finished Sep 01 08:54:07 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809537873 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2809537873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.958116159
Short name T13
Test name
Test status
Simulation time 137022993 ps
CPU time 9.33 seconds
Started Sep 01 08:53:51 AM UTC 24
Finished Sep 01 08:54:01 AM UTC 24
Peak memory 221344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958116159 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.958116159
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.755223011
Short name T24
Test name
Test status
Simulation time 552908222 ps
CPU time 64.18 seconds
Started Sep 01 08:53:57 AM UTC 24
Finished Sep 01 08:55:03 AM UTC 24
Peak memory 257516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755223011 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.755223011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3539505619
Short name T12
Test name
Test status
Simulation time 238923557 ps
CPU time 6.74 seconds
Started Sep 01 08:53:41 AM UTC 24
Finished Sep 01 08:53:50 AM UTC 24
Peak memory 221420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539505619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3539505619
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.390077541
Short name T14
Test name
Test status
Simulation time 593038654 ps
CPU time 13.9 seconds
Started Sep 01 08:53:48 AM UTC 24
Finished Sep 01 08:54:04 AM UTC 24
Peak memory 223520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390077541
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.390077541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.659002387
Short name T55
Test name
Test status
Simulation time 3299020165 ps
CPU time 218.9 seconds
Started Sep 01 08:53:55 AM UTC 24
Finished Sep 01 08:57:37 AM UTC 24
Peak memory 243416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=659002387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_stress_all_with_rand_reset.659002387
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2289008576
Short name T175
Test name
Test status
Simulation time 132000146 ps
CPU time 7.25 seconds
Started Sep 01 08:57:14 AM UTC 24
Finished Sep 01 08:57:22 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289008576 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2289008576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1648228160
Short name T233
Test name
Test status
Simulation time 3916177591 ps
CPU time 129.67 seconds
Started Sep 01 08:57:10 AM UTC 24
Finished Sep 01 08:59:22 AM UTC 24
Peak memory 257488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648228160 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.1648228160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.4283286725
Short name T178
Test name
Test status
Simulation time 626463682 ps
CPU time 16.51 seconds
Started Sep 01 08:57:12 AM UTC 24
Finished Sep 01 08:57:29 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283286725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4283286725
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3616046700
Short name T174
Test name
Test status
Simulation time 637422266 ps
CPU time 9.73 seconds
Started Sep 01 08:57:10 AM UTC 24
Finished Sep 01 08:57:21 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616046700 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3616046700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2525590335
Short name T177
Test name
Test status
Simulation time 413117339 ps
CPU time 17.85 seconds
Started Sep 01 08:57:09 AM UTC 24
Finished Sep 01 08:57:28 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252559033
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.2525590335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2345183528
Short name T334
Test name
Test status
Simulation time 19218385650 ps
CPU time 273.8 seconds
Started Sep 01 08:57:13 AM UTC 24
Finished Sep 01 09:01:50 AM UTC 24
Peak memory 232908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2345183528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2345183528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1655824103
Short name T180
Test name
Test status
Simulation time 155723917 ps
CPU time 6.17 seconds
Started Sep 01 08:57:23 AM UTC 24
Finished Sep 01 08:57:30 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655824103 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1655824103
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.891684853
Short name T239
Test name
Test status
Simulation time 8923737989 ps
CPU time 131.5 seconds
Started Sep 01 08:57:19 AM UTC 24
Finished Sep 01 08:59:33 AM UTC 24
Peak memory 257016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891684853 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.891684853
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.265034608
Short name T182
Test name
Test status
Simulation time 482987297 ps
CPU time 15.96 seconds
Started Sep 01 08:57:19 AM UTC 24
Finished Sep 01 08:57:36 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265034608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.265034608
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1440767714
Short name T179
Test name
Test status
Simulation time 505752768 ps
CPU time 10.52 seconds
Started Sep 01 08:57:18 AM UTC 24
Finished Sep 01 08:57:29 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440767714 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1440767714
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3526056381
Short name T181
Test name
Test status
Simulation time 567981920 ps
CPU time 14.88 seconds
Started Sep 01 08:57:17 AM UTC 24
Finished Sep 01 08:57:33 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352605638
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.3526056381
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2737988881
Short name T338
Test name
Test status
Simulation time 14278788780 ps
CPU time 273.71 seconds
Started Sep 01 08:57:22 AM UTC 24
Finished Sep 01 09:02:00 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2737988881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2737988881
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3522579177
Short name T184
Test name
Test status
Simulation time 502319158 ps
CPU time 7.03 seconds
Started Sep 01 08:57:31 AM UTC 24
Finished Sep 01 08:57:39 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522579177 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3522579177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.722167143
Short name T269
Test name
Test status
Simulation time 6442954586 ps
CPU time 154.69 seconds
Started Sep 01 08:57:27 AM UTC 24
Finished Sep 01 09:00:05 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722167143 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.722167143
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4201726169
Short name T190
Test name
Test status
Simulation time 1132510438 ps
CPU time 16.71 seconds
Started Sep 01 08:57:29 AM UTC 24
Finished Sep 01 08:57:47 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201726169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4201726169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2311071401
Short name T183
Test name
Test status
Simulation time 531747735 ps
CPU time 7.79 seconds
Started Sep 01 08:57:27 AM UTC 24
Finished Sep 01 08:57:37 AM UTC 24
Peak memory 221528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311071401 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2311071401
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3885794946
Short name T186
Test name
Test status
Simulation time 576898212 ps
CPU time 14.37 seconds
Started Sep 01 08:57:24 AM UTC 24
Finished Sep 01 08:57:40 AM UTC 24
Peak memory 221284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388579494
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.3885794946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3747336516
Short name T251
Test name
Test status
Simulation time 13909472519 ps
CPU time 132.84 seconds
Started Sep 01 08:57:30 AM UTC 24
Finished Sep 01 08:59:46 AM UTC 24
Peak memory 233112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3747336516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3747336516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3000766959
Short name T189
Test name
Test status
Simulation time 88157413 ps
CPU time 6.33 seconds
Started Sep 01 08:57:38 AM UTC 24
Finished Sep 01 08:57:46 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000766959 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3000766959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4286370906
Short name T257
Test name
Test status
Simulation time 3548140524 ps
CPU time 139.39 seconds
Started Sep 01 08:57:34 AM UTC 24
Finished Sep 01 08:59:56 AM UTC 24
Peak memory 223780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286370906 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.4286370906
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3946338573
Short name T91
Test name
Test status
Simulation time 168767914 ps
CPU time 14.53 seconds
Started Sep 01 08:57:35 AM UTC 24
Finished Sep 01 08:57:51 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946338573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3946338573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.4223216759
Short name T187
Test name
Test status
Simulation time 187337762 ps
CPU time 8.12 seconds
Started Sep 01 08:57:32 AM UTC 24
Finished Sep 01 08:57:41 AM UTC 24
Peak memory 221528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223216759 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4223216759
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.4038382063
Short name T188
Test name
Test status
Simulation time 161979901 ps
CPU time 10.56 seconds
Started Sep 01 08:57:32 AM UTC 24
Finished Sep 01 08:57:44 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403838206
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.4038382063
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3339836051
Short name T201
Test name
Test status
Simulation time 1106545324 ps
CPU time 51.75 seconds
Started Sep 01 08:57:37 AM UTC 24
Finished Sep 01 08:58:30 AM UTC 24
Peak memory 230808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3339836051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3339836051
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.2140463748
Short name T191
Test name
Test status
Simulation time 89973209 ps
CPU time 6.22 seconds
Started Sep 01 08:57:41 AM UTC 24
Finished Sep 01 08:57:49 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140463748 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2140463748
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3290197189
Short name T323
Test name
Test status
Simulation time 11125387599 ps
CPU time 223.63 seconds
Started Sep 01 08:57:40 AM UTC 24
Finished Sep 01 09:01:27 AM UTC 24
Peak memory 256556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290197189 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.3290197189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.855055736
Short name T93
Test name
Test status
Simulation time 1380802776 ps
CPU time 15.16 seconds
Started Sep 01 08:57:40 AM UTC 24
Finished Sep 01 08:57:57 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855055736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.855055736
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3926230979
Short name T92
Test name
Test status
Simulation time 317443164 ps
CPU time 15.35 seconds
Started Sep 01 08:57:38 AM UTC 24
Finished Sep 01 08:57:55 AM UTC 24
Peak memory 221624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392623097
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.3926230979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4196517069
Short name T123
Test name
Test status
Simulation time 4314095593 ps
CPU time 375.7 seconds
Started Sep 01 08:57:40 AM UTC 24
Finished Sep 01 09:04:01 AM UTC 24
Peak memory 233176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4196517069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.4196517069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3950453836
Short name T95
Test name
Test status
Simulation time 132447637 ps
CPU time 7.12 seconds
Started Sep 01 08:57:51 AM UTC 24
Finished Sep 01 08:57:59 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950453836 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3950453836
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1575995942
Short name T290
Test name
Test status
Simulation time 2081580899 ps
CPU time 170.86 seconds
Started Sep 01 08:57:47 AM UTC 24
Finished Sep 01 09:00:41 AM UTC 24
Peak memory 221668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575995942 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.1575995942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3377097473
Short name T98
Test name
Test status
Simulation time 264105968 ps
CPU time 16.59 seconds
Started Sep 01 08:57:49 AM UTC 24
Finished Sep 01 08:58:07 AM UTC 24
Peak memory 221540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377097473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3377097473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1757756602
Short name T94
Test name
Test status
Simulation time 527847545 ps
CPU time 12.38 seconds
Started Sep 01 08:57:45 AM UTC 24
Finished Sep 01 08:57:58 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757756602 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1757756602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3129533359
Short name T97
Test name
Test status
Simulation time 880299704 ps
CPU time 21.06 seconds
Started Sep 01 08:57:42 AM UTC 24
Finished Sep 01 08:58:05 AM UTC 24
Peak memory 223592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312953335
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.3129533359
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.402554794
Short name T216
Test name
Test status
Simulation time 14886597805 ps
CPU time 69.98 seconds
Started Sep 01 08:57:50 AM UTC 24
Finished Sep 01 08:59:02 AM UTC 24
Peak memory 243160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=402554794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.rom_ctrl_stress_all_with_rand_reset.402554794
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3479023842
Short name T192
Test name
Test status
Simulation time 98611356 ps
CPU time 6.26 seconds
Started Sep 01 08:58:00 AM UTC 24
Finished Sep 01 08:58:08 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479023842 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3479023842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3848170176
Short name T302
Test name
Test status
Simulation time 8360310142 ps
CPU time 180.52 seconds
Started Sep 01 08:57:55 AM UTC 24
Finished Sep 01 09:00:58 AM UTC 24
Peak memory 258316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848170176 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.3848170176
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3384912847
Short name T196
Test name
Test status
Simulation time 1154448079 ps
CPU time 16.38 seconds
Started Sep 01 08:57:57 AM UTC 24
Finished Sep 01 08:58:15 AM UTC 24
Peak memory 221540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384912847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3384912847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1605418525
Short name T96
Test name
Test status
Simulation time 554144917 ps
CPU time 7.4 seconds
Started Sep 01 08:57:52 AM UTC 24
Finished Sep 01 08:58:00 AM UTC 24
Peak memory 221264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605418525 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1605418525
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1774733337
Short name T193
Test name
Test status
Simulation time 1228511495 ps
CPU time 17.94 seconds
Started Sep 01 08:57:52 AM UTC 24
Finished Sep 01 08:58:11 AM UTC 24
Peak memory 223736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177473333
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.1774733337
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2413177784
Short name T291
Test name
Test status
Simulation time 2338010720 ps
CPU time 159.2 seconds
Started Sep 01 08:57:59 AM UTC 24
Finished Sep 01 09:00:41 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2413177784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2413177784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.4279961676
Short name T197
Test name
Test status
Simulation time 171125569 ps
CPU time 6.06 seconds
Started Sep 01 08:58:12 AM UTC 24
Finished Sep 01 08:58:19 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279961676 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4279961676
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.397678553
Short name T324
Test name
Test status
Simulation time 10554678909 ps
CPU time 197.68 seconds
Started Sep 01 08:58:07 AM UTC 24
Finished Sep 01 09:01:28 AM UTC 24
Peak memory 257420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397678553 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.397678553
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.257704419
Short name T195
Test name
Test status
Simulation time 99940886 ps
CPU time 8.02 seconds
Started Sep 01 08:58:05 AM UTC 24
Finished Sep 01 08:58:14 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257704419 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.257704419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3091127842
Short name T194
Test name
Test status
Simulation time 245713460 ps
CPU time 8.96 seconds
Started Sep 01 08:58:01 AM UTC 24
Finished Sep 01 08:58:11 AM UTC 24
Peak memory 223400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309112784
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.3091127842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.125625508
Short name T241
Test name
Test status
Simulation time 6333747853 ps
CPU time 83.23 seconds
Started Sep 01 08:58:11 AM UTC 24
Finished Sep 01 08:59:36 AM UTC 24
Peak memory 232920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=125625508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.rom_ctrl_stress_all_with_rand_reset.125625508
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2325698452
Short name T202
Test name
Test status
Simulation time 132101383 ps
CPU time 7.09 seconds
Started Sep 01 08:58:27 AM UTC 24
Finished Sep 01 08:58:35 AM UTC 24
Peak memory 221520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325698452 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2325698452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2342823087
Short name T332
Test name
Test status
Simulation time 15321796285 ps
CPU time 205.18 seconds
Started Sep 01 08:58:16 AM UTC 24
Finished Sep 01 09:01:44 AM UTC 24
Peak memory 257444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342823087 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.2342823087
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.935437188
Short name T203
Test name
Test status
Simulation time 1048584372 ps
CPU time 14.6 seconds
Started Sep 01 08:58:20 AM UTC 24
Finished Sep 01 08:58:36 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935437188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.935437188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1948208131
Short name T198
Test name
Test status
Simulation time 139726202 ps
CPU time 9.16 seconds
Started Sep 01 08:58:15 AM UTC 24
Finished Sep 01 08:58:25 AM UTC 24
Peak memory 221400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948208131 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1948208131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3055813833
Short name T200
Test name
Test status
Simulation time 180346759 ps
CPU time 15.45 seconds
Started Sep 01 08:58:12 AM UTC 24
Finished Sep 01 08:58:28 AM UTC 24
Peak memory 223672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305581383
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.3055813833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.430220959
Short name T335
Test name
Test status
Simulation time 2650222905 ps
CPU time 202.34 seconds
Started Sep 01 08:58:26 AM UTC 24
Finished Sep 01 09:01:52 AM UTC 24
Peak memory 233112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=430220959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.rom_ctrl_stress_all_with_rand_reset.430220959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.771122095
Short name T207
Test name
Test status
Simulation time 516517685 ps
CPU time 7.31 seconds
Started Sep 01 08:58:40 AM UTC 24
Finished Sep 01 08:58:48 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771122095 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.771122095
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2523289711
Short name T304
Test name
Test status
Simulation time 10578217306 ps
CPU time 147.61 seconds
Started Sep 01 08:58:31 AM UTC 24
Finished Sep 01 09:01:01 AM UTC 24
Peak memory 256396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523289711 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.2523289711
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3936260479
Short name T210
Test name
Test status
Simulation time 667766050 ps
CPU time 14.57 seconds
Started Sep 01 08:58:36 AM UTC 24
Finished Sep 01 08:58:52 AM UTC 24
Peak memory 221540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936260479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3936260479
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1632118833
Short name T204
Test name
Test status
Simulation time 95024810 ps
CPU time 8.34 seconds
Started Sep 01 08:58:29 AM UTC 24
Finished Sep 01 08:58:39 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632118833 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1632118833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.7517568
Short name T213
Test name
Test status
Simulation time 407666691 ps
CPU time 28.29 seconds
Started Sep 01 08:58:27 AM UTC 24
Finished Sep 01 08:58:57 AM UTC 24
Peak memory 225708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7517568 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.7517568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1382463047
Short name T348
Test name
Test status
Simulation time 7265569807 ps
CPU time 267.81 seconds
Started Sep 01 08:58:37 AM UTC 24
Finished Sep 01 09:03:08 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1382463047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1382463047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1776828982
Short name T27
Test name
Test status
Simulation time 268467230 ps
CPU time 6.92 seconds
Started Sep 01 08:54:13 AM UTC 24
Finished Sep 01 08:54:22 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776828982 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1776828982
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.455363022
Short name T41
Test name
Test status
Simulation time 2648665776 ps
CPU time 130.67 seconds
Started Sep 01 08:54:04 AM UTC 24
Finished Sep 01 08:56:17 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455363022 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.455363022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3244191023
Short name T106
Test name
Test status
Simulation time 625286577 ps
CPU time 9.72 seconds
Started Sep 01 08:54:02 AM UTC 24
Finished Sep 01 08:54:13 AM UTC 24
Peak memory 221400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244191023 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3244191023
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2405998628
Short name T31
Test name
Test status
Simulation time 343089167 ps
CPU time 166.52 seconds
Started Sep 01 08:54:08 AM UTC 24
Finished Sep 01 08:56:58 AM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405998628 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2405998628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.2805749260
Short name T11
Test name
Test status
Simulation time 100818731 ps
CPU time 5.66 seconds
Started Sep 01 08:54:01 AM UTC 24
Finished Sep 01 08:54:08 AM UTC 24
Peak memory 223404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805749260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2805749260
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3446509294
Short name T29
Test name
Test status
Simulation time 316673910 ps
CPU time 24.19 seconds
Started Sep 01 08:54:01 AM UTC 24
Finished Sep 01 08:54:27 AM UTC 24
Peak memory 223664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344650929
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.3446509294
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1198391411
Short name T51
Test name
Test status
Simulation time 2974994517 ps
CPU time 186.44 seconds
Started Sep 01 08:54:08 AM UTC 24
Finished Sep 01 08:57:18 AM UTC 24
Peak memory 243160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1198391411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1198391411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2286258574
Short name T215
Test name
Test status
Simulation time 168751158 ps
CPU time 4.79 seconds
Started Sep 01 08:58:52 AM UTC 24
Finished Sep 01 08:58:58 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286258574 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2286258574
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2720440295
Short name T331
Test name
Test status
Simulation time 18211866339 ps
CPU time 171.63 seconds
Started Sep 01 08:58:49 AM UTC 24
Finished Sep 01 09:01:43 AM UTC 24
Peak memory 257400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720440295 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.2720440295
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3990857436
Short name T221
Test name
Test status
Simulation time 3111090520 ps
CPU time 16.53 seconds
Started Sep 01 08:58:51 AM UTC 24
Finished Sep 01 08:59:09 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990857436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3990857436
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1434351345
Short name T214
Test name
Test status
Simulation time 142650133 ps
CPU time 9.54 seconds
Started Sep 01 08:58:47 AM UTC 24
Finished Sep 01 08:58:57 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434351345 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1434351345
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1147428279
Short name T217
Test name
Test status
Simulation time 608157569 ps
CPU time 20.34 seconds
Started Sep 01 08:58:43 AM UTC 24
Finished Sep 01 08:59:04 AM UTC 24
Peak memory 223592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114742827
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.1147428279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.970116053
Short name T315
Test name
Test status
Simulation time 2702841906 ps
CPU time 141.55 seconds
Started Sep 01 08:58:51 AM UTC 24
Finished Sep 01 09:01:15 AM UTC 24
Peak memory 232920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=970116053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.rom_ctrl_stress_all_with_rand_reset.970116053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3852290958
Short name T220
Test name
Test status
Simulation time 132088789 ps
CPU time 7.11 seconds
Started Sep 01 08:58:59 AM UTC 24
Finished Sep 01 08:59:07 AM UTC 24
Peak memory 221584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852290958 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3852290958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3988297937
Short name T313
Test name
Test status
Simulation time 1792347324 ps
CPU time 130.77 seconds
Started Sep 01 08:58:56 AM UTC 24
Finished Sep 01 09:01:10 AM UTC 24
Peak memory 257152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988297937 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.3988297937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.226904401
Short name T224
Test name
Test status
Simulation time 667149428 ps
CPU time 13.67 seconds
Started Sep 01 08:58:56 AM UTC 24
Finished Sep 01 08:59:12 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226904401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.226904401
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3831300882
Short name T218
Test name
Test status
Simulation time 867640931 ps
CPU time 9.11 seconds
Started Sep 01 08:58:54 AM UTC 24
Finished Sep 01 08:59:05 AM UTC 24
Peak memory 221528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831300882 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3831300882
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1438106837
Short name T230
Test name
Test status
Simulation time 5501800959 ps
CPU time 25.3 seconds
Started Sep 01 08:58:53 AM UTC 24
Finished Sep 01 08:59:20 AM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143810683
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.1438106837
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.190660476
Short name T282
Test name
Test status
Simulation time 6700378083 ps
CPU time 87.98 seconds
Started Sep 01 08:58:57 AM UTC 24
Finished Sep 01 09:00:28 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=190660476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_stress_all_with_rand_reset.190660476
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2865206610
Short name T226
Test name
Test status
Simulation time 443014641 ps
CPU time 7.21 seconds
Started Sep 01 08:59:06 AM UTC 24
Finished Sep 01 08:59:14 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865206610 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2865206610
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1671904657
Short name T326
Test name
Test status
Simulation time 6001538920 ps
CPU time 147.53 seconds
Started Sep 01 08:59:03 AM UTC 24
Finished Sep 01 09:01:33 AM UTC 24
Peak memory 257436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671904657 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.1671904657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.776453412
Short name T229
Test name
Test status
Simulation time 521191874 ps
CPU time 12.13 seconds
Started Sep 01 08:59:04 AM UTC 24
Finished Sep 01 08:59:17 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776453412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.776453412
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.670636250
Short name T223
Test name
Test status
Simulation time 369713050 ps
CPU time 9.26 seconds
Started Sep 01 08:59:01 AM UTC 24
Finished Sep 01 08:59:11 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670636250 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.670636250
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2519910180
Short name T232
Test name
Test status
Simulation time 316407100 ps
CPU time 21.68 seconds
Started Sep 01 08:58:59 AM UTC 24
Finished Sep 01 08:59:22 AM UTC 24
Peak memory 223592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251991018
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.2519910180
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.949587691
Short name T265
Test name
Test status
Simulation time 1244983181 ps
CPU time 57.72 seconds
Started Sep 01 08:59:05 AM UTC 24
Finished Sep 01 09:00:04 AM UTC 24
Peak memory 228760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=949587691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_stress_all_with_rand_reset.949587691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2272441923
Short name T231
Test name
Test status
Simulation time 1762405903 ps
CPU time 7.27 seconds
Started Sep 01 08:59:12 AM UTC 24
Finished Sep 01 08:59:21 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272441923 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2272441923
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2147012833
Short name T339
Test name
Test status
Simulation time 5109051317 ps
CPU time 167.76 seconds
Started Sep 01 08:59:09 AM UTC 24
Finished Sep 01 09:02:00 AM UTC 24
Peak memory 244924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147012833 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.2147012833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.194157418
Short name T237
Test name
Test status
Simulation time 1033227171 ps
CPU time 16.26 seconds
Started Sep 01 08:59:11 AM UTC 24
Finished Sep 01 08:59:29 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194157418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.194157418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.4091231948
Short name T227
Test name
Test status
Simulation time 146521304 ps
CPU time 6.99 seconds
Started Sep 01 08:59:08 AM UTC 24
Finished Sep 01 08:59:16 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091231948 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4091231948
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.704833467
Short name T235
Test name
Test status
Simulation time 820480511 ps
CPU time 19.06 seconds
Started Sep 01 08:59:07 AM UTC 24
Finished Sep 01 08:59:27 AM UTC 24
Peak memory 223392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704833467
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.704833467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1786880536
Short name T283
Test name
Test status
Simulation time 5751700733 ps
CPU time 76.93 seconds
Started Sep 01 08:59:12 AM UTC 24
Finished Sep 01 09:00:31 AM UTC 24
Peak memory 232920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1786880536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1786880536
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2613889604
Short name T236
Test name
Test status
Simulation time 346816140 ps
CPU time 6.18 seconds
Started Sep 01 08:59:21 AM UTC 24
Finished Sep 01 08:59:28 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613889604 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2613889604
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.295801704
Short name T295
Test name
Test status
Simulation time 1567488551 ps
CPU time 92.3 seconds
Started Sep 01 08:59:17 AM UTC 24
Finished Sep 01 09:00:51 AM UTC 24
Peak memory 223524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295801704 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.295801704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.3029538060
Short name T240
Test name
Test status
Simulation time 995163941 ps
CPU time 15.38 seconds
Started Sep 01 08:59:18 AM UTC 24
Finished Sep 01 08:59:34 AM UTC 24
Peak memory 221604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029538060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3029538060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2821148269
Short name T234
Test name
Test status
Simulation time 1863895179 ps
CPU time 8.44 seconds
Started Sep 01 08:59:16 AM UTC 24
Finished Sep 01 08:59:25 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821148269 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2821148269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1648561890
Short name T247
Test name
Test status
Simulation time 1158130264 ps
CPU time 28.84 seconds
Started Sep 01 08:59:13 AM UTC 24
Finished Sep 01 08:59:43 AM UTC 24
Peak memory 225448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164856189
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.1648561890
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1024914574
Short name T261
Test name
Test status
Simulation time 2667295703 ps
CPU time 38.89 seconds
Started Sep 01 08:59:18 AM UTC 24
Finished Sep 01 08:59:58 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1024914574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1024914574
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.262855221
Short name T246
Test name
Test status
Simulation time 508459668 ps
CPU time 11.13 seconds
Started Sep 01 08:59:28 AM UTC 24
Finished Sep 01 08:59:41 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262855221 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.262855221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.993448626
Short name T327
Test name
Test status
Simulation time 1904133342 ps
CPU time 128.93 seconds
Started Sep 01 08:59:23 AM UTC 24
Finished Sep 01 09:01:34 AM UTC 24
Peak memory 256836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993448626 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.993448626
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.715721891
Short name T248
Test name
Test status
Simulation time 1465144026 ps
CPU time 16.88 seconds
Started Sep 01 08:59:26 AM UTC 24
Finished Sep 01 08:59:44 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715721891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.715721891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.489500784
Short name T238
Test name
Test status
Simulation time 595254799 ps
CPU time 9.09 seconds
Started Sep 01 08:59:22 AM UTC 24
Finished Sep 01 08:59:32 AM UTC 24
Peak memory 221672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489500784 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.489500784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.400732212
Short name T245
Test name
Test status
Simulation time 410910759 ps
CPU time 16.42 seconds
Started Sep 01 08:59:22 AM UTC 24
Finished Sep 01 08:59:40 AM UTC 24
Peak memory 223392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400732212
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.400732212
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3662651959
Short name T356
Test name
Test status
Simulation time 23637055954 ps
CPU time 477.18 seconds
Started Sep 01 08:59:27 AM UTC 24
Finished Sep 01 09:07:31 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3662651959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3662651959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1269235192
Short name T250
Test name
Test status
Simulation time 271835982 ps
CPU time 7.06 seconds
Started Sep 01 08:59:37 AM UTC 24
Finished Sep 01 08:59:45 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269235192 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1269235192
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3244903018
Short name T308
Test name
Test status
Simulation time 15607858806 ps
CPU time 89.58 seconds
Started Sep 01 08:59:33 AM UTC 24
Finished Sep 01 09:01:04 AM UTC 24
Peak memory 223580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244903018 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.3244903018
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.4017278534
Short name T252
Test name
Test status
Simulation time 169705519 ps
CPU time 12.87 seconds
Started Sep 01 08:59:34 AM UTC 24
Finished Sep 01 08:59:48 AM UTC 24
Peak memory 221480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017278534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4017278534
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.4223303159
Short name T244
Test name
Test status
Simulation time 464899182 ps
CPU time 8.52 seconds
Started Sep 01 08:59:29 AM UTC 24
Finished Sep 01 08:59:39 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223303159 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4223303159
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.4094192555
Short name T253
Test name
Test status
Simulation time 203614535 ps
CPU time 18.88 seconds
Started Sep 01 08:59:28 AM UTC 24
Finished Sep 01 08:59:48 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409419255
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.4094192555
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1076944577
Short name T311
Test name
Test status
Simulation time 1659039712 ps
CPU time 91.35 seconds
Started Sep 01 08:59:35 AM UTC 24
Finished Sep 01 09:01:08 AM UTC 24
Peak memory 228952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1076944577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1076944577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.89908298
Short name T255
Test name
Test status
Simulation time 333336149 ps
CPU time 5.63 seconds
Started Sep 01 08:59:44 AM UTC 24
Finished Sep 01 08:59:51 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89908298 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.89908298
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3497480113
Short name T329
Test name
Test status
Simulation time 4085327805 ps
CPU time 118.18 seconds
Started Sep 01 08:59:40 AM UTC 24
Finished Sep 01 09:01:40 AM UTC 24
Peak memory 257552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497480113 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.3497480113
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3252228946
Short name T259
Test name
Test status
Simulation time 492171443 ps
CPU time 16.8 seconds
Started Sep 01 08:59:40 AM UTC 24
Finished Sep 01 08:59:58 AM UTC 24
Peak memory 221540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252228946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3252228946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.972724855
Short name T254
Test name
Test status
Simulation time 365672673 ps
CPU time 8.04 seconds
Started Sep 01 08:59:40 AM UTC 24
Finished Sep 01 08:59:49 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972724855 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.972724855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.504128317
Short name T260
Test name
Test status
Simulation time 1108709083 ps
CPU time 18.17 seconds
Started Sep 01 08:59:39 AM UTC 24
Finished Sep 01 08:59:58 AM UTC 24
Peak memory 225520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504128317
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.504128317
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3956382573
Short name T298
Test name
Test status
Simulation time 3590536713 ps
CPU time 70.19 seconds
Started Sep 01 08:59:41 AM UTC 24
Finished Sep 01 09:00:53 AM UTC 24
Peak memory 230844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3956382573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3956382573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.404909962
Short name T258
Test name
Test status
Simulation time 278197186 ps
CPU time 6.25 seconds
Started Sep 01 08:59:50 AM UTC 24
Finished Sep 01 08:59:57 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404909962 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.404909962
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4284990347
Short name T337
Test name
Test status
Simulation time 17210148020 ps
CPU time 130.65 seconds
Started Sep 01 08:59:45 AM UTC 24
Finished Sep 01 09:01:58 AM UTC 24
Peak memory 223588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284990347 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.4284990347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2183365
Short name T266
Test name
Test status
Simulation time 335021616 ps
CPU time 16.8 seconds
Started Sep 01 08:59:46 AM UTC 24
Finished Sep 01 09:00:04 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_T
EST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctr
l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2183365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.4072874796
Short name T256
Test name
Test status
Simulation time 198372795 ps
CPU time 8.95 seconds
Started Sep 01 08:59:45 AM UTC 24
Finished Sep 01 08:59:55 AM UTC 24
Peak memory 221264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072874796 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4072874796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2475837996
Short name T262
Test name
Test status
Simulation time 800115937 ps
CPU time 15.04 seconds
Started Sep 01 08:59:45 AM UTC 24
Finished Sep 01 09:00:01 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247583799
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.2475837996
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.4204527441
Short name T268
Test name
Test status
Simulation time 500498409 ps
CPU time 6.82 seconds
Started Sep 01 08:59:57 AM UTC 24
Finished Sep 01 09:00:05 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204527441 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4204527441
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2448860234
Short name T353
Test name
Test status
Simulation time 46879089966 ps
CPU time 239.77 seconds
Started Sep 01 08:59:55 AM UTC 24
Finished Sep 01 09:03:58 AM UTC 24
Peak memory 257236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448860234 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.2448860234
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3711965975
Short name T271
Test name
Test status
Simulation time 760272121 ps
CPU time 14.84 seconds
Started Sep 01 08:59:56 AM UTC 24
Finished Sep 01 09:00:12 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711965975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3711965975
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.4090443537
Short name T263
Test name
Test status
Simulation time 144951561 ps
CPU time 9.44 seconds
Started Sep 01 08:59:52 AM UTC 24
Finished Sep 01 09:00:02 AM UTC 24
Peak memory 221464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090443537 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4090443537
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.2704938766
Short name T267
Test name
Test status
Simulation time 1748093292 ps
CPU time 13.75 seconds
Started Sep 01 08:59:50 AM UTC 24
Finished Sep 01 09:00:05 AM UTC 24
Peak memory 225448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270493876
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.2704938766
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2266266844
Short name T320
Test name
Test status
Simulation time 3320961368 ps
CPU time 84.85 seconds
Started Sep 01 08:59:56 AM UTC 24
Finished Sep 01 09:01:23 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2266266844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2266266844
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2505650523
Short name T34
Test name
Test status
Simulation time 499489851 ps
CPU time 5.88 seconds
Started Sep 01 08:54:30 AM UTC 24
Finished Sep 01 08:54:37 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505650523 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2505650523
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1019095121
Short name T42
Test name
Test status
Simulation time 4688013871 ps
CPU time 133.95 seconds
Started Sep 01 08:54:23 AM UTC 24
Finished Sep 01 08:56:39 AM UTC 24
Peak memory 242076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019095121 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.1019095121
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3202012975
Short name T37
Test name
Test status
Simulation time 1038088490 ps
CPU time 23.31 seconds
Started Sep 01 08:54:25 AM UTC 24
Finished Sep 01 08:54:49 AM UTC 24
Peak memory 221612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202012975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3202012975
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2325074552
Short name T33
Test name
Test status
Simulation time 541769736 ps
CPU time 8.45 seconds
Started Sep 01 08:54:23 AM UTC 24
Finished Sep 01 08:54:32 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325074552 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2325074552
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.3910857649
Short name T30
Test name
Test status
Simulation time 388525167 ps
CPU time 76.16 seconds
Started Sep 01 08:54:28 AM UTC 24
Finished Sep 01 08:55:46 AM UTC 24
Peak memory 256860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910857649 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3910857649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3808404743
Short name T61
Test name
Test status
Simulation time 557824095 ps
CPU time 9.26 seconds
Started Sep 01 08:54:14 AM UTC 24
Finished Sep 01 08:54:24 AM UTC 24
Peak memory 221548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808404743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3808404743
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3988091633
Short name T32
Test name
Test status
Simulation time 606900944 ps
CPU time 10.39 seconds
Started Sep 01 08:54:18 AM UTC 24
Finished Sep 01 08:54:29 AM UTC 24
Peak memory 221532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398809163
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.3988091633
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3877994386
Short name T19
Test name
Test status
Simulation time 2448931815 ps
CPU time 141.19 seconds
Started Sep 01 08:54:27 AM UTC 24
Finished Sep 01 08:56:51 AM UTC 24
Peak memory 241112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3877994386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3877994386
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.633025308
Short name T272
Test name
Test status
Simulation time 250219153 ps
CPU time 7.2 seconds
Started Sep 01 09:00:02 AM UTC 24
Finished Sep 01 09:00:13 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633025308 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.633025308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2891512444
Short name T333
Test name
Test status
Simulation time 1953848474 ps
CPU time 108.31 seconds
Started Sep 01 08:59:59 AM UTC 24
Finished Sep 01 09:01:50 AM UTC 24
Peak memory 253360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891512444 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.2891512444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1395100557
Short name T274
Test name
Test status
Simulation time 341603500 ps
CPU time 14.46 seconds
Started Sep 01 08:59:59 AM UTC 24
Finished Sep 01 09:00:15 AM UTC 24
Peak memory 221276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395100557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1395100557
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2007837241
Short name T270
Test name
Test status
Simulation time 146054564 ps
CPU time 9.92 seconds
Started Sep 01 08:59:59 AM UTC 24
Finished Sep 01 09:00:10 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007837241 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2007837241
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.434745290
Short name T276
Test name
Test status
Simulation time 3051039445 ps
CPU time 16.5 seconds
Started Sep 01 08:59:58 AM UTC 24
Finished Sep 01 09:00:16 AM UTC 24
Peak memory 225584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434745290
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.434745290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1965671446
Short name T347
Test name
Test status
Simulation time 3800434999 ps
CPU time 174.66 seconds
Started Sep 01 08:59:59 AM UTC 24
Finished Sep 01 09:02:57 AM UTC 24
Peak memory 239064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1965671446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1965671446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3689499125
Short name T273
Test name
Test status
Simulation time 2488583845 ps
CPU time 7.19 seconds
Started Sep 01 09:00:06 AM UTC 24
Finished Sep 01 09:00:14 AM UTC 24
Peak memory 221520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689499125 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3689499125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2288197237
Short name T330
Test name
Test status
Simulation time 4792024139 ps
CPU time 94.45 seconds
Started Sep 01 09:00:06 AM UTC 24
Finished Sep 01 09:01:42 AM UTC 24
Peak memory 257564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288197237 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.2288197237
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3405226325
Short name T278
Test name
Test status
Simulation time 2083788609 ps
CPU time 14.67 seconds
Started Sep 01 09:00:06 AM UTC 24
Finished Sep 01 09:00:22 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405226325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3405226325
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1561373852
Short name T275
Test name
Test status
Simulation time 367302217 ps
CPU time 8.32 seconds
Started Sep 01 09:00:06 AM UTC 24
Finished Sep 01 09:00:15 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561373852 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1561373852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3785547614
Short name T284
Test name
Test status
Simulation time 1205148200 ps
CPU time 25.04 seconds
Started Sep 01 09:00:06 AM UTC 24
Finished Sep 01 09:00:32 AM UTC 24
Peak memory 223480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378554761
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.3785547614
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1876040383
Short name T343
Test name
Test status
Simulation time 16173015059 ps
CPU time 136.65 seconds
Started Sep 01 09:00:06 AM UTC 24
Finished Sep 01 09:02:25 AM UTC 24
Peak memory 232920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1876040383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1876040383
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1825807661
Short name T211
Test name
Test status
Simulation time 348280725 ps
CPU time 6.41 seconds
Started Sep 01 09:00:16 AM UTC 24
Finished Sep 01 09:00:24 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825807661 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1825807661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3056660090
Short name T340
Test name
Test status
Simulation time 1582562781 ps
CPU time 108.38 seconds
Started Sep 01 09:00:13 AM UTC 24
Finished Sep 01 09:02:04 AM UTC 24
Peak memory 242004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056660090 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.3056660090
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.6719669
Short name T280
Test name
Test status
Simulation time 259453678 ps
CPU time 16.21 seconds
Started Sep 01 09:00:14 AM UTC 24
Finished Sep 01 09:00:32 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6719669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_T
EST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctr
l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.6719669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3091809194
Short name T277
Test name
Test status
Simulation time 914486042 ps
CPU time 7.03 seconds
Started Sep 01 09:00:11 AM UTC 24
Finished Sep 01 09:00:19 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091809194 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3091809194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.949954300
Short name T279
Test name
Test status
Simulation time 178729443 ps
CPU time 14.76 seconds
Started Sep 01 09:00:06 AM UTC 24
Finished Sep 01 09:00:22 AM UTC 24
Peak memory 221424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949954300
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.949954300
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1990646650
Short name T325
Test name
Test status
Simulation time 7418209174 ps
CPU time 72.42 seconds
Started Sep 01 09:00:15 AM UTC 24
Finished Sep 01 09:01:30 AM UTC 24
Peak memory 232920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1990646650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1990646650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.965303864
Short name T285
Test name
Test status
Simulation time 1237115123 ps
CPU time 6.85 seconds
Started Sep 01 09:00:25 AM UTC 24
Finished Sep 01 09:00:33 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965303864 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.965303864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1417213483
Short name T346
Test name
Test status
Simulation time 18847878421 ps
CPU time 148.06 seconds
Started Sep 01 09:00:20 AM UTC 24
Finished Sep 01 09:02:50 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417213483 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.1417213483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3818673748
Short name T288
Test name
Test status
Simulation time 697229866 ps
CPU time 14.53 seconds
Started Sep 01 09:00:23 AM UTC 24
Finished Sep 01 09:00:39 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818673748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3818673748
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1441947153
Short name T228
Test name
Test status
Simulation time 2179124162 ps
CPU time 6.52 seconds
Started Sep 01 09:00:16 AM UTC 24
Finished Sep 01 09:00:24 AM UTC 24
Peak memory 221400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441947153 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1441947153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3755633528
Short name T286
Test name
Test status
Simulation time 835402546 ps
CPU time 15.11 seconds
Started Sep 01 09:00:16 AM UTC 24
Finished Sep 01 09:00:33 AM UTC 24
Peak memory 223592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375563352
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.3755633528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2789446833
Short name T355
Test name
Test status
Simulation time 3844573747 ps
CPU time 289.16 seconds
Started Sep 01 09:00:23 AM UTC 24
Finished Sep 01 09:05:16 AM UTC 24
Peak memory 243160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2789446833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2789446833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.424413151
Short name T289
Test name
Test status
Simulation time 190965791 ps
CPU time 5.85 seconds
Started Sep 01 09:00:32 AM UTC 24
Finished Sep 01 09:00:39 AM UTC 24
Peak memory 221508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424413151 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.424413151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2824929032
Short name T351
Test name
Test status
Simulation time 5664885816 ps
CPU time 178.48 seconds
Started Sep 01 09:00:29 AM UTC 24
Finished Sep 01 09:03:30 AM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824929032 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.2824929032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.954813685
Short name T293
Test name
Test status
Simulation time 281663934 ps
CPU time 12.42 seconds
Started Sep 01 09:00:30 AM UTC 24
Finished Sep 01 09:00:44 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954813685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.954813685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2805983419
Short name T287
Test name
Test status
Simulation time 207485971 ps
CPU time 9.17 seconds
Started Sep 01 09:00:26 AM UTC 24
Finished Sep 01 09:00:36 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805983419 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2805983419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3792066639
Short name T299
Test name
Test status
Simulation time 1676573519 ps
CPU time 27.98 seconds
Started Sep 01 09:00:25 AM UTC 24
Finished Sep 01 09:00:54 AM UTC 24
Peak memory 227576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379206663
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.3792066639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2545007474
Short name T341
Test name
Test status
Simulation time 5276450381 ps
CPU time 90.33 seconds
Started Sep 01 09:00:32 AM UTC 24
Finished Sep 01 09:02:05 AM UTC 24
Peak memory 230984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2545007474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2545007474
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.770166075
Short name T294
Test name
Test status
Simulation time 131781953 ps
CPU time 7.25 seconds
Started Sep 01 09:00:40 AM UTC 24
Finished Sep 01 09:00:48 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770166075 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.770166075
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1844061093
Short name T344
Test name
Test status
Simulation time 8801424819 ps
CPU time 115.54 seconds
Started Sep 01 09:00:33 AM UTC 24
Finished Sep 01 09:02:31 AM UTC 24
Peak memory 253416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844061093 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.1844061093
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.712082036
Short name T300
Test name
Test status
Simulation time 531954210 ps
CPU time 15.56 seconds
Started Sep 01 09:00:37 AM UTC 24
Finished Sep 01 09:00:55 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712082036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.712082036
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.1049037817
Short name T292
Test name
Test status
Simulation time 143135549 ps
CPU time 8.84 seconds
Started Sep 01 09:00:33 AM UTC 24
Finished Sep 01 09:00:43 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049037817 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1049037817
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2486695630
Short name T297
Test name
Test status
Simulation time 191173526 ps
CPU time 18.31 seconds
Started Sep 01 09:00:33 AM UTC 24
Finished Sep 01 09:00:53 AM UTC 24
Peak memory 223544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248669563
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.2486695630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2607360919
Short name T328
Test name
Test status
Simulation time 3902847150 ps
CPU time 55.34 seconds
Started Sep 01 09:00:38 AM UTC 24
Finished Sep 01 09:01:36 AM UTC 24
Peak memory 230876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2607360919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2607360919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2306982313
Short name T301
Test name
Test status
Simulation time 127824804 ps
CPU time 7.2 seconds
Started Sep 01 09:00:49 AM UTC 24
Finished Sep 01 09:00:57 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306982313 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2306982313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3248842506
Short name T352
Test name
Test status
Simulation time 34136190649 ps
CPU time 174.8 seconds
Started Sep 01 09:00:42 AM UTC 24
Finished Sep 01 09:03:40 AM UTC 24
Peak memory 256428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248842506 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.3248842506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1106416675
Short name T305
Test name
Test status
Simulation time 3117952149 ps
CPU time 16.62 seconds
Started Sep 01 09:00:44 AM UTC 24
Finished Sep 01 09:01:02 AM UTC 24
Peak memory 221416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106416675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1106416675
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3977488508
Short name T296
Test name
Test status
Simulation time 882708549 ps
CPU time 9.23 seconds
Started Sep 01 09:00:42 AM UTC 24
Finished Sep 01 09:00:52 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977488508 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3977488508
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2196155939
Short name T303
Test name
Test status
Simulation time 688871361 ps
CPU time 17.9 seconds
Started Sep 01 09:00:40 AM UTC 24
Finished Sep 01 09:00:59 AM UTC 24
Peak memory 223400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219615593
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.2196155939
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2998480139
Short name T349
Test name
Test status
Simulation time 3335768579 ps
CPU time 140.87 seconds
Started Sep 01 09:00:45 AM UTC 24
Finished Sep 01 09:03:08 AM UTC 24
Peak memory 243352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2998480139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2998480139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1585843243
Short name T307
Test name
Test status
Simulation time 427115771 ps
CPU time 7.27 seconds
Started Sep 01 09:00:55 AM UTC 24
Finished Sep 01 09:01:04 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585843243 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1585843243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3812008332
Short name T345
Test name
Test status
Simulation time 7950286486 ps
CPU time 102.33 seconds
Started Sep 01 09:00:54 AM UTC 24
Finished Sep 01 09:02:39 AM UTC 24
Peak memory 256380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812008332 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.3812008332
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.715964556
Short name T319
Test name
Test status
Simulation time 988109925 ps
CPU time 23.52 seconds
Started Sep 01 09:00:54 AM UTC 24
Finished Sep 01 09:01:19 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715964556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.715964556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.617440420
Short name T306
Test name
Test status
Simulation time 141730717 ps
CPU time 9.5 seconds
Started Sep 01 09:00:53 AM UTC 24
Finished Sep 01 09:01:04 AM UTC 24
Peak memory 221608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617440420 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.617440420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1011325670
Short name T310
Test name
Test status
Simulation time 282414744 ps
CPU time 14.78 seconds
Started Sep 01 09:00:52 AM UTC 24
Finished Sep 01 09:01:08 AM UTC 24
Peak memory 223400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101132567
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.1011325670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4002340972
Short name T350
Test name
Test status
Simulation time 3753861353 ps
CPU time 143.19 seconds
Started Sep 01 09:00:55 AM UTC 24
Finished Sep 01 09:03:21 AM UTC 24
Peak memory 232920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4002340972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4002340972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.865106149
Short name T312
Test name
Test status
Simulation time 86222623 ps
CPU time 4.97 seconds
Started Sep 01 09:01:03 AM UTC 24
Finished Sep 01 09:01:09 AM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865106149 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.865106149
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3866197827
Short name T342
Test name
Test status
Simulation time 1924159726 ps
CPU time 82.76 seconds
Started Sep 01 09:01:00 AM UTC 24
Finished Sep 01 09:02:24 AM UTC 24
Peak memory 252988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866197827 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.3866197827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1563309535
Short name T318
Test name
Test status
Simulation time 1038364100 ps
CPU time 15.85 seconds
Started Sep 01 09:01:00 AM UTC 24
Finished Sep 01 09:01:17 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563309535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1563309535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.168634052
Short name T309
Test name
Test status
Simulation time 96306865 ps
CPU time 6.98 seconds
Started Sep 01 09:00:59 AM UTC 24
Finished Sep 01 09:01:07 AM UTC 24
Peak memory 221544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168634052 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.168634052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1938262172
Short name T322
Test name
Test status
Simulation time 1662812681 ps
CPU time 26.74 seconds
Started Sep 01 09:00:57 AM UTC 24
Finished Sep 01 09:01:26 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193826217
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.1938262172
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1870992277
Short name T336
Test name
Test status
Simulation time 21909822441 ps
CPU time 53.9 seconds
Started Sep 01 09:01:02 AM UTC 24
Finished Sep 01 09:01:57 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1870992277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1870992277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.2436319132
Short name T316
Test name
Test status
Simulation time 542692445 ps
CPU time 7.18 seconds
Started Sep 01 09:01:07 AM UTC 24
Finished Sep 01 09:01:15 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436319132 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2436319132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2644776601
Short name T354
Test name
Test status
Simulation time 5506325624 ps
CPU time 182.45 seconds
Started Sep 01 09:01:05 AM UTC 24
Finished Sep 01 09:04:10 AM UTC 24
Peak memory 242216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644776601 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.2644776601
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1883440057
Short name T317
Test name
Test status
Simulation time 257456340 ps
CPU time 10.43 seconds
Started Sep 01 09:01:05 AM UTC 24
Finished Sep 01 09:01:17 AM UTC 24
Peak memory 221348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883440057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1883440057
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2147197928
Short name T314
Test name
Test status
Simulation time 515791808 ps
CPU time 7.08 seconds
Started Sep 01 09:01:05 AM UTC 24
Finished Sep 01 09:01:13 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147197928 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2147197928
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2982824506
Short name T321
Test name
Test status
Simulation time 1132329581 ps
CPU time 19.11 seconds
Started Sep 01 09:01:05 AM UTC 24
Finished Sep 01 09:01:25 AM UTC 24
Peak memory 223464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298282450
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.2982824506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2075057271
Short name T56
Test name
Test status
Simulation time 260214659 ps
CPU time 6.01 seconds
Started Sep 01 08:54:47 AM UTC 24
Finished Sep 01 08:54:54 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075057271 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2075057271
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.924424569
Short name T23
Test name
Test status
Simulation time 1333358127 ps
CPU time 82.87 seconds
Started Sep 01 08:54:37 AM UTC 24
Finished Sep 01 08:56:02 AM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924424569 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.924424569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3369974554
Short name T38
Test name
Test status
Simulation time 4973604792 ps
CPU time 11.63 seconds
Started Sep 01 08:54:37 AM UTC 24
Finished Sep 01 08:54:50 AM UTC 24
Peak memory 221420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369974554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3369974554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3651336141
Short name T36
Test name
Test status
Simulation time 98282715 ps
CPU time 8.83 seconds
Started Sep 01 08:54:36 AM UTC 24
Finished Sep 01 08:54:46 AM UTC 24
Peak memory 221336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651336141 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3651336141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2621161961
Short name T35
Test name
Test status
Simulation time 1129266302 ps
CPU time 8.06 seconds
Started Sep 01 08:54:30 AM UTC 24
Finished Sep 01 08:54:39 AM UTC 24
Peak memory 221436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621161961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2621161961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3076786025
Short name T39
Test name
Test status
Simulation time 2219888111 ps
CPU time 16 seconds
Started Sep 01 08:54:33 AM UTC 24
Finished Sep 01 08:54:50 AM UTC 24
Peak memory 221488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307678602
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.3076786025
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1999142564
Short name T50
Test name
Test status
Simulation time 3819545499 ps
CPU time 145.38 seconds
Started Sep 01 08:54:41 AM UTC 24
Finished Sep 01 08:57:08 AM UTC 24
Peak memory 243272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1999142564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1999142564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.549688056
Short name T65
Test name
Test status
Simulation time 251152736 ps
CPU time 7.34 seconds
Started Sep 01 08:54:55 AM UTC 24
Finished Sep 01 08:55:04 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549688056 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.549688056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1860437273
Short name T169
Test name
Test status
Simulation time 1359865339 ps
CPU time 136.42 seconds
Started Sep 01 08:54:53 AM UTC 24
Finished Sep 01 08:57:12 AM UTC 24
Peak memory 257152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860437273 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.1860437273
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1358314966
Short name T45
Test name
Test status
Simulation time 260525479 ps
CPU time 12.93 seconds
Started Sep 01 08:54:54 AM UTC 24
Finished Sep 01 08:55:08 AM UTC 24
Peak memory 221356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358314966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1358314966
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2078483141
Short name T125
Test name
Test status
Simulation time 279723464 ps
CPU time 9.56 seconds
Started Sep 01 08:54:51 AM UTC 24
Finished Sep 01 08:55:01 AM UTC 24
Peak memory 221400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078483141 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2078483141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3118143367
Short name T57
Test name
Test status
Simulation time 678568404 ps
CPU time 8.12 seconds
Started Sep 01 08:54:50 AM UTC 24
Finished Sep 01 08:54:59 AM UTC 24
Peak memory 221340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118143367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3118143367
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2340108034
Short name T76
Test name
Test status
Simulation time 195804079 ps
CPU time 11.34 seconds
Started Sep 01 08:54:51 AM UTC 24
Finished Sep 01 08:55:03 AM UTC 24
Peak memory 223664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234010803
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.2340108034
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3421002891
Short name T66
Test name
Test status
Simulation time 308791039 ps
CPU time 6.21 seconds
Started Sep 01 08:55:06 AM UTC 24
Finished Sep 01 08:55:13 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421002891 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3421002891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1160955190
Short name T43
Test name
Test status
Simulation time 5465688777 ps
CPU time 125.33 seconds
Started Sep 01 08:55:03 AM UTC 24
Finished Sep 01 08:57:11 AM UTC 24
Peak memory 257416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160955190 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.1160955190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1034476239
Short name T139
Test name
Test status
Simulation time 986077670 ps
CPU time 14.5 seconds
Started Sep 01 08:55:05 AM UTC 24
Finished Sep 01 08:55:20 AM UTC 24
Peak memory 221356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034476239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1034476239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3140229624
Short name T107
Test name
Test status
Simulation time 190515734 ps
CPU time 7.99 seconds
Started Sep 01 08:55:02 AM UTC 24
Finished Sep 01 08:55:11 AM UTC 24
Peak memory 221264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140229624 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3140229624
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2701976442
Short name T77
Test name
Test status
Simulation time 275268798 ps
CPU time 9.24 seconds
Started Sep 01 08:54:56 AM UTC 24
Finished Sep 01 08:55:07 AM UTC 24
Peak memory 221420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701976442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2701976442
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.132569228
Short name T131
Test name
Test status
Simulation time 735337580 ps
CPU time 31.61 seconds
Started Sep 01 08:54:59 AM UTC 24
Finished Sep 01 08:55:32 AM UTC 24
Peak memory 227760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132569228
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.132569228
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2054256418
Short name T264
Test name
Test status
Simulation time 3934471784 ps
CPU time 294.54 seconds
Started Sep 01 08:55:05 AM UTC 24
Finished Sep 01 09:00:03 AM UTC 24
Peak memory 239192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2054256418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2054256418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.441390661
Short name T67
Test name
Test status
Simulation time 500823745 ps
CPU time 7.18 seconds
Started Sep 01 08:55:17 AM UTC 24
Finished Sep 01 08:55:25 AM UTC 24
Peak memory 221328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441390661 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.441390661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3676861479
Short name T185
Test name
Test status
Simulation time 7110129312 ps
CPU time 143.8 seconds
Started Sep 01 08:55:13 AM UTC 24
Finished Sep 01 08:57:39 AM UTC 24
Peak memory 242080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676861479 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.3676861479
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2955212568
Short name T132
Test name
Test status
Simulation time 184528221 ps
CPU time 8.97 seconds
Started Sep 01 08:55:14 AM UTC 24
Finished Sep 01 08:55:24 AM UTC 24
Peak memory 221548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955212568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2955212568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1562621362
Short name T108
Test name
Test status
Simulation time 1035785025 ps
CPU time 9.39 seconds
Started Sep 01 08:55:12 AM UTC 24
Finished Sep 01 08:55:22 AM UTC 24
Peak memory 221464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562621362 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1562621362
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1419499006
Short name T126
Test name
Test status
Simulation time 540005373 ps
CPU time 7.31 seconds
Started Sep 01 08:55:08 AM UTC 24
Finished Sep 01 08:55:16 AM UTC 24
Peak memory 221356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419499006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1419499006
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2216697803
Short name T138
Test name
Test status
Simulation time 1071616085 ps
CPU time 19.92 seconds
Started Sep 01 08:55:09 AM UTC 24
Finished Sep 01 08:55:30 AM UTC 24
Peak memory 223648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221669780
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.2216697803
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3766927582
Short name T124
Test name
Test status
Simulation time 18359991672 ps
CPU time 222.73 seconds
Started Sep 01 08:55:14 AM UTC 24
Finished Sep 01 08:59:00 AM UTC 24
Peak memory 245272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3766927582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3766927582
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2498252707
Short name T141
Test name
Test status
Simulation time 521190137 ps
CPU time 5.93 seconds
Started Sep 01 08:55:31 AM UTC 24
Finished Sep 01 08:55:38 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498252707 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2498252707
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1410718875
Short name T176
Test name
Test status
Simulation time 1913041634 ps
CPU time 119.68 seconds
Started Sep 01 08:55:25 AM UTC 24
Finished Sep 01 08:57:27 AM UTC 24
Peak memory 221548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410718875 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.1410718875
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1807394131
Short name T135
Test name
Test status
Simulation time 1056422311 ps
CPU time 15.53 seconds
Started Sep 01 08:55:27 AM UTC 24
Finished Sep 01 08:55:44 AM UTC 24
Peak memory 221352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807394131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1807394131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2348282704
Short name T109
Test name
Test status
Simulation time 138968232 ps
CPU time 7.3 seconds
Started Sep 01 08:55:23 AM UTC 24
Finished Sep 01 08:55:32 AM UTC 24
Peak memory 221656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348282704 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2348282704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1675397807
Short name T78
Test name
Test status
Simulation time 377923933 ps
CPU time 8.25 seconds
Started Sep 01 08:55:19 AM UTC 24
Finished Sep 01 08:55:29 AM UTC 24
Peak memory 221356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675397807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1675397807
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2186869199
Short name T137
Test name
Test status
Simulation time 2011076479 ps
CPU time 29.03 seconds
Started Sep 01 08:55:21 AM UTC 24
Finished Sep 01 08:55:52 AM UTC 24
Peak memory 225712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218686919
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.2186869199
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all/latest
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