| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.60 | 96.89 | 92.56 | 97.67 | 100.00 | 98.97 | 98.05 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 65.50 | 65.50 | 92.58 | 92.58 | 67.13 | 67.13 | 63.30 | 63.30 | 40.00 | 40.00 | 88.97 | 88.97 | 93.85 | 93.85 | 12.65 | 12.65 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1544365444 |
| 83.24 | 17.74 | 95.93 | 3.35 | 83.29 | 16.15 | 87.22 | 23.93 | 40.00 | 0.00 | 93.45 | 4.48 | 95.65 | 1.80 | 87.12 | 74.47 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2944248643 |
| 88.75 | 5.52 | 95.93 | 0.00 | 85.39 | 2.11 | 89.90 | 2.67 | 73.33 | 33.33 | 93.79 | 0.34 | 95.80 | 0.15 | 87.12 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3966141372 |
| 92.46 | 3.70 | 96.53 | 0.60 | 88.90 | 3.51 | 93.45 | 3.55 | 86.67 | 13.33 | 96.55 | 2.76 | 96.10 | 0.30 | 88.99 | 1.87 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2450191904 |
| 94.02 | 1.56 | 96.65 | 0.12 | 89.89 | 0.98 | 95.80 | 2.35 | 93.33 | 6.67 | 96.90 | 0.34 | 96.10 | 0.00 | 89.46 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.640173837 |
| 95.07 | 1.05 | 96.89 | 0.24 | 90.59 | 0.70 | 95.80 | 0.00 | 93.33 | 0.00 | 97.93 | 1.03 | 96.10 | 0.00 | 94.85 | 5.39 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1848792141 |
| 96.06 | 0.99 | 96.89 | 0.00 | 90.59 | 0.00 | 95.80 | 0.00 | 100.00 | 6.67 | 97.93 | 0.00 | 96.10 | 0.00 | 95.08 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3876948601 |
| 96.35 | 0.29 | 96.89 | 0.00 | 91.15 | 0.56 | 96.05 | 0.25 | 100.00 | 0.00 | 97.93 | 0.00 | 96.40 | 0.30 | 96.02 | 0.94 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1386033295 |
| 96.58 | 0.23 | 96.89 | 0.00 | 91.15 | 0.00 | 96.05 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 96.40 | 0.00 | 97.66 | 1.64 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1840950851 |
| 96.77 | 0.19 | 96.89 | 0.00 | 91.29 | 0.14 | 96.05 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 97.60 | 1.20 | 97.66 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2866498956 |
| 96.94 | 0.17 | 96.89 | 0.00 | 91.85 | 0.56 | 96.67 | 0.62 | 100.00 | 0.00 | 97.93 | 0.00 | 97.60 | 0.00 | 97.66 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.416310990 |
| 97.06 | 0.12 | 96.89 | 0.00 | 91.85 | 0.00 | 97.25 | 0.57 | 100.00 | 0.00 | 97.93 | 0.00 | 97.60 | 0.00 | 97.89 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.917124237 |
| 97.17 | 0.11 | 96.89 | 0.00 | 92.28 | 0.42 | 97.25 | 0.00 | 100.00 | 0.00 | 98.28 | 0.34 | 97.60 | 0.00 | 97.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3458096712 |
| 97.26 | 0.09 | 96.89 | 0.00 | 92.42 | 0.14 | 97.40 | 0.15 | 100.00 | 0.00 | 98.62 | 0.34 | 97.60 | 0.00 | 97.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2304030035 |
| 97.33 | 0.07 | 96.89 | 0.00 | 92.42 | 0.00 | 97.67 | 0.28 | 100.00 | 0.00 | 98.62 | 0.00 | 97.60 | 0.00 | 98.13 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3655767630 |
| 97.40 | 0.07 | 96.89 | 0.00 | 92.56 | 0.14 | 97.67 | 0.00 | 100.00 | 0.00 | 98.97 | 0.34 | 97.60 | 0.00 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.427375148 |
| 97.47 | 0.07 | 96.89 | 0.00 | 92.56 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.97 | 0.00 | 97.60 | 0.00 | 98.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2974802584 |
| 97.50 | 0.03 | 96.89 | 0.00 | 92.56 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.97 | 0.00 | 97.60 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1268602400 |
| 97.54 | 0.03 | 96.89 | 0.00 | 92.56 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.97 | 0.00 | 97.60 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.881995152 |
| 97.56 | 0.02 | 96.89 | 0.00 | 92.56 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.97 | 0.00 | 97.75 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.480745668 |
| 97.58 | 0.02 | 96.89 | 0.00 | 92.56 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.97 | 0.00 | 97.90 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.635381103 |
| 97.60 | 0.02 | 96.89 | 0.00 | 92.56 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.97 | 0.00 | 98.05 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1451801440 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1813716945 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1003986368 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3092739889 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1364319151 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3476100707 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.614225687 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.153447577 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2367620566 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1984265203 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2284437355 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1591719625 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1096155215 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.364831729 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1313533196 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3933171709 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1184132639 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1619498850 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1115505719 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.408560767 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.880491925 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2148735274 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3911139972 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2413472315 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.237219915 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3994365948 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.573617928 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4016406917 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.61480211 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2389109509 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2744549015 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4034272805 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2280854815 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.571215124 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2234497989 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.831560843 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3834927012 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2116006540 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1588168626 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3556991568 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2894780942 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2645861573 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1118938194 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1462188280 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2208207323 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4239210934 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2398668721 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1729648832 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.325012747 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4246158437 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.804694644 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3022657794 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1829097046 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.235444940 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2316834269 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.222111557 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.727697796 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1332388528 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3156639825 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1958824436 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.975752243 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1496802996 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.376815997 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2863080696 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.836977026 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3504082024 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3361969958 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.313094060 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.99349812 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.719160593 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3936410677 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4285135713 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4234235586 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3051024235 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1536329168 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.651213827 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4106002876 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.785471280 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3516320040 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1488527795 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3344145028 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3157379465 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2007837241 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.434745290 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1965671446 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3689499125 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2288197237 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3405226325 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1561373852 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3785547614 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1876040383 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1825807661 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3056660090 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.6719669 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3091809194 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.949954300 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1990646650 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.965303864 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1417213483 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3818673748 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1441947153 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3755633528 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2789446833 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.424413151 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2824929032 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.954813685 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2805983419 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3792066639 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2545007474 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.770166075 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1844061093 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.712082036 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.1049037817 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2486695630 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2607360919 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2306982313 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3248842506 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1106416675 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3977488508 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2196155939 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2998480139 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1585843243 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3812008332 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.715964556 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.617440420 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1011325670 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4002340972 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.865106149 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3866197827 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1563309535 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.168634052 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1938262172 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1870992277 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.2436319132 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2644776601 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1883440057 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2147197928 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2982824506 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2075057271 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.924424569 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3369974554 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3651336141 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2621161961 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3076786025 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1999142564 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.549688056 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1860437273 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1358314966 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2078483141 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3118143367 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2340108034 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3421002891 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1160955190 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1034476239 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3140229624 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2701976442 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.132569228 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2054256418 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.441390661 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3676861479 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2955212568 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1562621362 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1419499006 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2216697803 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3766927582 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2498252707 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1410718875 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1807394131 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2348282704 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1675397807 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2186869199 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.343708969 | Sep 01 08:52:34 AM UTC 24 | Sep 01 08:52:43 AM UTC 24 | 368244473 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.635381103 | Sep 01 08:52:43 AM UTC 24 | Sep 01 08:52:52 AM UTC 24 | 187424933 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1544365444 | Sep 01 08:52:35 AM UTC 24 | Sep 01 08:53:00 AM UTC 24 | 1072231869 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.752999061 | Sep 01 08:52:53 AM UTC 24 | Sep 01 08:53:09 AM UTC 24 | 693181552 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.546625030 | Sep 01 08:53:10 AM UTC 24 | Sep 01 08:53:17 AM UTC 24 | 168227614 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3655767630 | Sep 01 08:53:13 AM UTC 24 | Sep 01 08:53:23 AM UTC 24 | 535459990 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.569010302 | Sep 01 08:53:18 AM UTC 24 | Sep 01 08:53:28 AM UTC 24 | 1637719311 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1281772852 | Sep 01 08:53:24 AM UTC 24 | Sep 01 08:53:40 AM UTC 24 | 699506930 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.3465721706 | Sep 01 08:53:18 AM UTC 24 | Sep 01 08:53:40 AM UTC 24 | 296590484 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.416310990 | Sep 01 08:53:40 AM UTC 24 | Sep 01 08:53:48 AM UTC 24 | 87860940 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3539505619 | Sep 01 08:53:41 AM UTC 24 | Sep 01 08:53:50 AM UTC 24 | 238923557 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.958116159 | Sep 01 08:53:51 AM UTC 24 | Sep 01 08:54:01 AM UTC 24 | 137022993 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.390077541 | Sep 01 08:53:48 AM UTC 24 | Sep 01 08:54:04 AM UTC 24 | 593038654 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.2809537873 | Sep 01 08:54:00 AM UTC 24 | Sep 01 08:54:07 AM UTC 24 | 763431269 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.2805749260 | Sep 01 08:54:01 AM UTC 24 | Sep 01 08:54:08 AM UTC 24 | 100818731 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2450191904 | Sep 01 08:53:55 AM UTC 24 | Sep 01 08:54:13 AM UTC 24 | 253997610 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3244191023 | Sep 01 08:54:02 AM UTC 24 | Sep 01 08:54:13 AM UTC 24 | 625286577 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1776828982 | Sep 01 08:54:13 AM UTC 24 | Sep 01 08:54:22 AM UTC 24 | 268467230 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2304030035 | Sep 01 08:54:06 AM UTC 24 | Sep 01 08:54:22 AM UTC 24 | 666854003 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3808404743 | Sep 01 08:54:14 AM UTC 24 | Sep 01 08:54:24 AM UTC 24 | 557824095 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3446509294 | Sep 01 08:54:01 AM UTC 24 | Sep 01 08:54:27 AM UTC 24 | 316673910 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2622306654 | Sep 01 08:53:04 AM UTC 24 | Sep 01 08:54:29 AM UTC 24 | 2295698316 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3988091633 | Sep 01 08:54:18 AM UTC 24 | Sep 01 08:54:29 AM UTC 24 | 606900944 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2325074552 | Sep 01 08:54:23 AM UTC 24 | Sep 01 08:54:32 AM UTC 24 | 541769736 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2944248643 | Sep 01 08:53:00 AM UTC 24 | Sep 01 08:54:36 AM UTC 24 | 3574931631 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2505650523 | Sep 01 08:54:30 AM UTC 24 | Sep 01 08:54:37 AM UTC 24 | 499489851 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.2621161961 | Sep 01 08:54:30 AM UTC 24 | Sep 01 08:54:39 AM UTC 24 | 1129266302 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3651336141 | Sep 01 08:54:36 AM UTC 24 | Sep 01 08:54:46 AM UTC 24 | 98282715 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3202012975 | Sep 01 08:54:25 AM UTC 24 | Sep 01 08:54:49 AM UTC 24 | 1038088490 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3369974554 | Sep 01 08:54:37 AM UTC 24 | Sep 01 08:54:50 AM UTC 24 | 4973604792 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3076786025 | Sep 01 08:54:33 AM UTC 24 | Sep 01 08:54:50 AM UTC 24 | 2219888111 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.640173837 | Sep 01 08:52:44 AM UTC 24 | Sep 01 08:54:54 AM UTC 24 | 3450742737 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2075057271 | Sep 01 08:54:47 AM UTC 24 | Sep 01 08:54:54 AM UTC 24 | 260214659 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3118143367 | Sep 01 08:54:50 AM UTC 24 | Sep 01 08:54:59 AM UTC 24 | 678568404 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2078483141 | Sep 01 08:54:51 AM UTC 24 | Sep 01 08:55:01 AM UTC 24 | 279723464 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.755223011 | Sep 01 08:53:57 AM UTC 24 | Sep 01 08:55:03 AM UTC 24 | 552908222 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2340108034 | Sep 01 08:54:51 AM UTC 24 | Sep 01 08:55:03 AM UTC 24 | 195804079 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.549688056 | Sep 01 08:54:55 AM UTC 24 | Sep 01 08:55:04 AM UTC 24 | 251152736 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2701976442 | Sep 01 08:54:56 AM UTC 24 | Sep 01 08:55:07 AM UTC 24 | 275268798 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1358314966 | Sep 01 08:54:54 AM UTC 24 | Sep 01 08:55:08 AM UTC 24 | 260525479 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3140229624 | Sep 01 08:55:02 AM UTC 24 | Sep 01 08:55:11 AM UTC 24 | 190515734 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.661156700 | Sep 01 08:53:19 AM UTC 24 | Sep 01 08:55:12 AM UTC 24 | 13029375757 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3421002891 | Sep 01 08:55:06 AM UTC 24 | Sep 01 08:55:13 AM UTC 24 | 308791039 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1419499006 | Sep 01 08:55:08 AM UTC 24 | Sep 01 08:55:16 AM UTC 24 | 540005373 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1034476239 | Sep 01 08:55:05 AM UTC 24 | Sep 01 08:55:20 AM UTC 24 | 986077670 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1562621362 | Sep 01 08:55:12 AM UTC 24 | Sep 01 08:55:22 AM UTC 24 | 1035785025 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2955212568 | Sep 01 08:55:14 AM UTC 24 | Sep 01 08:55:24 AM UTC 24 | 184528221 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.441390661 | Sep 01 08:55:17 AM UTC 24 | Sep 01 08:55:25 AM UTC 24 | 500823745 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1675397807 | Sep 01 08:55:19 AM UTC 24 | Sep 01 08:55:29 AM UTC 24 | 377923933 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2216697803 | Sep 01 08:55:09 AM UTC 24 | Sep 01 08:55:30 AM UTC 24 | 1071616085 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2348282704 | Sep 01 08:55:23 AM UTC 24 | Sep 01 08:55:32 AM UTC 24 | 138968232 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.132569228 | Sep 01 08:54:59 AM UTC 24 | Sep 01 08:55:32 AM UTC 24 | 735337580 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1386033295 | Sep 01 08:53:30 AM UTC 24 | Sep 01 08:55:36 AM UTC 24 | 1959995667 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2498252707 | Sep 01 08:55:31 AM UTC 24 | Sep 01 08:55:38 AM UTC 24 | 521190137 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.441561273 | Sep 01 08:55:33 AM UTC 24 | Sep 01 08:55:43 AM UTC 24 | 577627743 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1807394131 | Sep 01 08:55:27 AM UTC 24 | Sep 01 08:55:44 AM UTC 24 | 1056422311 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1789351053 | Sep 01 08:53:29 AM UTC 24 | Sep 01 08:55:45 AM UTC 24 | 36690828242 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.3910857649 | Sep 01 08:54:28 AM UTC 24 | Sep 01 08:55:46 AM UTC 24 | 388525167 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.82132044 | Sep 01 08:55:33 AM UTC 24 | Sep 01 08:55:51 AM UTC 24 | 252193325 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2186869199 | Sep 01 08:55:21 AM UTC 24 | Sep 01 08:55:52 AM UTC 24 | 2011076479 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3979251685 | Sep 01 08:55:45 AM UTC 24 | Sep 01 08:55:52 AM UTC 24 | 195282606 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.4162669532 | Sep 01 08:55:38 AM UTC 24 | Sep 01 08:55:54 AM UTC 24 | 171988702 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2008915735 | Sep 01 08:55:46 AM UTC 24 | Sep 01 08:55:56 AM UTC 24 | 187222075 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3385120360 | Sep 01 08:55:55 AM UTC 24 | Sep 01 08:56:02 AM UTC 24 | 334758533 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.2367598289 | Sep 01 08:55:46 AM UTC 24 | Sep 01 08:56:02 AM UTC 24 | 224565850 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.924424569 | Sep 01 08:54:37 AM UTC 24 | Sep 01 08:56:02 AM UTC 24 | 1333358127 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3966141372 | Sep 01 08:53:54 AM UTC 24 | Sep 01 08:56:07 AM UTC 24 | 9170198296 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2944180071 | Sep 01 08:55:59 AM UTC 24 | Sep 01 08:56:09 AM UTC 24 | 139699520 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2728145585 | Sep 01 08:55:53 AM UTC 24 | Sep 01 08:56:10 AM UTC 24 | 509281774 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.987201130 | Sep 01 08:56:03 AM UTC 24 | Sep 01 08:56:11 AM UTC 24 | 250790265 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.413147579 | Sep 01 08:56:03 AM UTC 24 | Sep 01 08:56:11 AM UTC 24 | 1325931122 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1711586153 | Sep 01 08:55:57 AM UTC 24 | Sep 01 08:56:12 AM UTC 24 | 272701065 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.455363022 | Sep 01 08:54:04 AM UTC 24 | Sep 01 08:56:17 AM UTC 24 | 2648665776 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3298889073 | Sep 01 08:56:02 AM UTC 24 | Sep 01 08:56:18 AM UTC 24 | 754873595 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1621305726 | Sep 01 08:56:12 AM UTC 24 | Sep 01 08:56:19 AM UTC 24 | 89246862 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.352715010 | Sep 01 08:56:13 AM UTC 24 | Sep 01 08:56:21 AM UTC 24 | 553921244 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.669125093 | Sep 01 08:56:08 AM UTC 24 | Sep 01 08:56:22 AM UTC 24 | 498486092 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1739007660 | Sep 01 08:55:54 AM UTC 24 | Sep 01 08:56:23 AM UTC 24 | 1760371310 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1275090264 | Sep 01 08:56:19 AM UTC 24 | Sep 01 08:56:24 AM UTC 24 | 349514258 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3724416570 | Sep 01 08:56:03 AM UTC 24 | Sep 01 08:56:27 AM UTC 24 | 1054685700 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3343214346 | Sep 01 08:56:13 AM UTC 24 | Sep 01 08:56:30 AM UTC 24 | 4827676066 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1956115506 | Sep 01 08:56:22 AM UTC 24 | Sep 01 08:56:33 AM UTC 24 | 145644503 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2238754437 | Sep 01 08:56:26 AM UTC 24 | Sep 01 08:56:35 AM UTC 24 | 338114823 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3714468086 | Sep 01 08:56:23 AM UTC 24 | Sep 01 08:56:35 AM UTC 24 | 498354237 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.1862639658 | Sep 01 08:56:20 AM UTC 24 | Sep 01 08:56:36 AM UTC 24 | 278049604 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.217775599 | Sep 01 08:56:15 AM UTC 24 | Sep 01 08:56:37 AM UTC 24 | 1008160164 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1019095121 | Sep 01 08:54:23 AM UTC 24 | Sep 01 08:56:39 AM UTC 24 | 4688013871 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.4211407358 | Sep 01 08:56:31 AM UTC 24 | Sep 01 08:56:40 AM UTC 24 | 391295935 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2109820716 | Sep 01 08:56:37 AM UTC 24 | Sep 01 08:56:44 AM UTC 24 | 88951420 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.104504297 | Sep 01 08:56:27 AM UTC 24 | Sep 01 08:56:45 AM UTC 24 | 423154834 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1703902371 | Sep 01 08:56:36 AM UTC 24 | Sep 01 08:56:49 AM UTC 24 | 876999813 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2517897884 | Sep 01 08:56:39 AM UTC 24 | Sep 01 08:56:50 AM UTC 24 | 560635262 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3877994386 | Sep 01 08:54:27 AM UTC 24 | Sep 01 08:56:51 AM UTC 24 | 2448931815 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1791744147 | Sep 01 08:56:45 AM UTC 24 | Sep 01 08:56:54 AM UTC 24 | 262658211 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.553778873 | Sep 01 08:56:41 AM UTC 24 | Sep 01 08:56:57 AM UTC 24 | 1034955592 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2405998628 | Sep 01 08:54:08 AM UTC 24 | Sep 01 08:56:58 AM UTC 24 | 343089167 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1534465086 | Sep 01 08:56:38 AM UTC 24 | Sep 01 08:56:59 AM UTC 24 | 1235371038 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2603047371 | Sep 01 08:56:50 AM UTC 24 | Sep 01 08:57:01 AM UTC 24 | 275046197 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.945412841 | Sep 01 08:56:53 AM UTC 24 | Sep 01 08:57:08 AM UTC 24 | 334358186 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3088603528 | Sep 01 08:57:00 AM UTC 24 | Sep 01 08:57:08 AM UTC 24 | 141297108 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1999142564 | Sep 01 08:54:41 AM UTC 24 | Sep 01 08:57:08 AM UTC 24 | 3819545499 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1311336763 | Sep 01 08:56:58 AM UTC 24 | Sep 01 08:57:09 AM UTC 24 | 990912061 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2338891648 | Sep 01 08:56:49 AM UTC 24 | Sep 01 08:57:09 AM UTC 24 | 1978246735 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1160955190 | Sep 01 08:55:03 AM UTC 24 | Sep 01 08:57:11 AM UTC 24 | 5465688777 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1860437273 | Sep 01 08:54:53 AM UTC 24 | Sep 01 08:57:12 AM UTC 24 | 1359865339 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1485776420 | Sep 01 08:55:37 AM UTC 24 | Sep 01 08:57:13 AM UTC 24 | 16625285907 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.645083203 | Sep 01 08:57:09 AM UTC 24 | Sep 01 08:57:16 AM UTC 24 | 176143342 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.4137614090 | Sep 01 08:57:04 AM UTC 24 | Sep 01 08:57:17 AM UTC 24 | 264131101 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1198391411 | Sep 01 08:54:08 AM UTC 24 | Sep 01 08:57:18 AM UTC 24 | 2974994517 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2135182639 | Sep 01 08:56:59 AM UTC 24 | Sep 01 08:57:18 AM UTC 24 | 1135014613 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3616046700 | Sep 01 08:57:10 AM UTC 24 | Sep 01 08:57:21 AM UTC 24 | 637422266 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2289008576 | Sep 01 08:57:14 AM UTC 24 | Sep 01 08:57:22 AM UTC 24 | 132000146 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4075674577 | Sep 01 08:56:10 AM UTC 24 | Sep 01 08:57:23 AM UTC 24 | 17011622377 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1410718875 | Sep 01 08:55:25 AM UTC 24 | Sep 01 08:57:27 AM UTC 24 | 1913041634 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2525590335 | Sep 01 08:57:09 AM UTC 24 | Sep 01 08:57:28 AM UTC 24 | 413117339 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.4283286725 | Sep 01 08:57:12 AM UTC 24 | Sep 01 08:57:29 AM UTC 24 | 626463682 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1440767714 | Sep 01 08:57:18 AM UTC 24 | Sep 01 08:57:29 AM UTC 24 | 505752768 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1655824103 | Sep 01 08:57:23 AM UTC 24 | Sep 01 08:57:30 AM UTC 24 | 155723917 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3057948264 | Sep 01 08:56:03 AM UTC 24 | Sep 01 08:57:31 AM UTC 24 | 15639519416 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3526056381 | Sep 01 08:57:17 AM UTC 24 | Sep 01 08:57:33 AM UTC 24 | 567981920 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.917124237 | Sep 01 08:54:54 AM UTC 24 | Sep 01 08:57:34 AM UTC 24 | 13277240997 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.265034608 | Sep 01 08:57:19 AM UTC 24 | Sep 01 08:57:36 AM UTC 24 | 482987297 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2311071401 | Sep 01 08:57:27 AM UTC 24 | Sep 01 08:57:37 AM UTC 24 | 531747735 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.659002387 | Sep 01 08:53:55 AM UTC 24 | Sep 01 08:57:37 AM UTC 24 | 3299020165 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1223435269 | Sep 01 08:56:13 AM UTC 24 | Sep 01 08:57:38 AM UTC 24 | 1584517256 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3522579177 | Sep 01 08:57:31 AM UTC 24 | Sep 01 08:57:39 AM UTC 24 | 502319158 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3676861479 | Sep 01 08:55:13 AM UTC 24 | Sep 01 08:57:39 AM UTC 24 | 7110129312 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3885794946 | Sep 01 08:57:24 AM UTC 24 | Sep 01 08:57:40 AM UTC 24 | 576898212 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.4223216759 | Sep 01 08:57:32 AM UTC 24 | Sep 01 08:57:41 AM UTC 24 | 187337762 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.4038382063 | Sep 01 08:57:32 AM UTC 24 | Sep 01 08:57:44 AM UTC 24 | 161979901 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3000766959 | Sep 01 08:57:38 AM UTC 24 | Sep 01 08:57:46 AM UTC 24 | 88157413 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4201726169 | Sep 01 08:57:29 AM UTC 24 | Sep 01 08:57:47 AM UTC 24 | 1132510438 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.2140463748 | Sep 01 08:57:41 AM UTC 24 | Sep 01 08:57:49 AM UTC 24 | 89973209 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1451801440 | Sep 01 08:57:39 AM UTC 24 | Sep 01 08:57:50 AM UTC 24 | 138663663 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1257231194 | Sep 01 08:55:59 AM UTC 24 | Sep 01 08:57:51 AM UTC 24 | 1963856536 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3946338573 | Sep 01 08:57:35 AM UTC 24 | Sep 01 08:57:51 AM UTC 24 | 168767914 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3926230979 | Sep 01 08:57:38 AM UTC 24 | Sep 01 08:57:55 AM UTC 24 | 317443164 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.855055736 | Sep 01 08:57:40 AM UTC 24 | Sep 01 08:57:57 AM UTC 24 | 1380802776 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1757756602 | Sep 01 08:57:45 AM UTC 24 | Sep 01 08:57:58 AM UTC 24 | 527847545 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3950453836 | Sep 01 08:57:51 AM UTC 24 | Sep 01 08:57:59 AM UTC 24 | 132447637 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1605418525 | Sep 01 08:57:52 AM UTC 24 | Sep 01 08:58:00 AM UTC 24 | 554144917 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3129533359 | Sep 01 08:57:42 AM UTC 24 | Sep 01 08:58:05 AM UTC 24 | 880299704 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3377097473 | Sep 01 08:57:49 AM UTC 24 | Sep 01 08:58:07 AM UTC 24 | 264105968 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3479023842 | Sep 01 08:58:00 AM UTC 24 | Sep 01 08:58:08 AM UTC 24 | 98611356 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1774733337 | Sep 01 08:57:52 AM UTC 24 | Sep 01 08:58:11 AM UTC 24 | 1228511495 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3091127842 | Sep 01 08:58:01 AM UTC 24 | Sep 01 08:58:11 AM UTC 24 | 245713460 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.257704419 | Sep 01 08:58:05 AM UTC 24 | Sep 01 08:58:14 AM UTC 24 | 99940886 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3384912847 | Sep 01 08:57:57 AM UTC 24 | Sep 01 08:58:15 AM UTC 24 | 1154448079 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.4279961676 | Sep 01 08:58:12 AM UTC 24 | Sep 01 08:58:19 AM UTC 24 | 171125569 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1948208131 | Sep 01 08:58:15 AM UTC 24 | Sep 01 08:58:25 AM UTC 24 | 139726202 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2341234638 | Sep 01 08:57:09 AM UTC 24 | Sep 01 08:58:26 AM UTC 24 | 7138231717 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.427375148 | Sep 01 08:58:09 AM UTC 24 | Sep 01 08:58:26 AM UTC 24 | 262283212 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3055813833 | Sep 01 08:58:12 AM UTC 24 | Sep 01 08:58:28 AM UTC 24 | 180346759 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3339836051 | Sep 01 08:57:37 AM UTC 24 | Sep 01 08:58:30 AM UTC 24 | 1106545324 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2325698452 | Sep 01 08:58:27 AM UTC 24 | Sep 01 08:58:35 AM UTC 24 | 132101383 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.935437188 | Sep 01 08:58:20 AM UTC 24 | Sep 01 08:58:36 AM UTC 24 | 1048584372 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1632118833 | Sep 01 08:58:29 AM UTC 24 | Sep 01 08:58:39 AM UTC 24 | 95024810 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.933349865 | Sep 01 08:57:02 AM UTC 24 | Sep 01 08:58:42 AM UTC 24 | 1318826390 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1419703954 | Sep 01 08:55:51 AM UTC 24 | Sep 01 08:58:46 AM UTC 24 | 1812264466 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.771122095 | Sep 01 08:58:40 AM UTC 24 | Sep 01 08:58:48 AM UTC 24 | 516517685 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.26401617 | Sep 01 08:56:34 AM UTC 24 | Sep 01 08:58:50 AM UTC 24 | 13836962142 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3747820290 | Sep 01 08:56:52 AM UTC 24 | Sep 01 08:58:50 AM UTC 24 | 9997238132 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3936260479 | Sep 01 08:58:36 AM UTC 24 | Sep 01 08:58:52 AM UTC 24 | 667766050 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1825807661 | Sep 01 09:00:16 AM UTC 24 | Sep 01 09:00:24 AM UTC 24 | 348280725 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.420715061 | Sep 01 08:55:44 AM UTC 24 | Sep 01 08:58:55 AM UTC 24 | 18393072368 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.7517568 | Sep 01 08:58:27 AM UTC 24 | Sep 01 08:58:57 AM UTC 24 | 407666691 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1434351345 | Sep 01 08:58:47 AM UTC 24 | Sep 01 08:58:57 AM UTC 24 | 142650133 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2286258574 | Sep 01 08:58:52 AM UTC 24 | Sep 01 08:58:58 AM UTC 24 | 168751158 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3766927582 | Sep 01 08:55:14 AM UTC 24 | Sep 01 08:59:00 AM UTC 24 | 18359991672 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.402554794 | Sep 01 08:57:50 AM UTC 24 | Sep 01 08:59:02 AM UTC 24 | 14886597805 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1147428279 | Sep 01 08:58:43 AM UTC 24 | Sep 01 08:59:04 AM UTC 24 | 608157569 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3831300882 | Sep 01 08:58:54 AM UTC 24 | Sep 01 08:59:05 AM UTC 24 | 867640931 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1222817397 | Sep 01 08:56:05 AM UTC 24 | Sep 01 08:59:06 AM UTC 24 | 6243548570 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3852290958 | Sep 01 08:58:59 AM UTC 24 | Sep 01 08:59:07 AM UTC 24 | 132088789 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3990857436 | Sep 01 08:58:51 AM UTC 24 | Sep 01 08:59:09 AM UTC 24 | 3111090520 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1862133692 | Sep 01 08:56:36 AM UTC 24 | Sep 01 08:59:10 AM UTC 24 | 3152862331 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.670636250 | Sep 01 08:59:01 AM UTC 24 | Sep 01 08:59:11 AM UTC 24 | 369713050 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.226904401 | Sep 01 08:58:56 AM UTC 24 | Sep 01 08:59:12 AM UTC 24 | 667149428 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3876948601 | Sep 01 08:56:23 AM UTC 24 | Sep 01 08:59:12 AM UTC 24 | 3913627960 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2865206610 | Sep 01 08:59:06 AM UTC 24 | Sep 01 08:59:14 AM UTC 24 | 443014641 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.4091231948 | Sep 01 08:59:08 AM UTC 24 | Sep 01 08:59:16 AM UTC 24 | 146521304 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1441947153 | Sep 01 09:00:16 AM UTC 24 | Sep 01 09:00:24 AM UTC 24 | 2179124162 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.776453412 | Sep 01 08:59:04 AM UTC 24 | Sep 01 08:59:17 AM UTC 24 | 521191874 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1438106837 | Sep 01 08:58:53 AM UTC 24 | Sep 01 08:59:20 AM UTC 24 | 5501800959 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2272441923 | Sep 01 08:59:12 AM UTC 24 | Sep 01 08:59:21 AM UTC 24 | 1762405903 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2519910180 | Sep 01 08:58:59 AM UTC 24 | Sep 01 08:59:22 AM UTC 24 | 316407100 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1648228160 | Sep 01 08:57:10 AM UTC 24 | Sep 01 08:59:22 AM UTC 24 | 3916177591 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2821148269 | Sep 01 08:59:16 AM UTC 24 | Sep 01 08:59:25 AM UTC 24 | 1863895179 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.704833467 | Sep 01 08:59:07 AM UTC 24 | Sep 01 08:59:27 AM UTC 24 | 820480511 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2613889604 | Sep 01 08:59:21 AM UTC 24 | Sep 01 08:59:28 AM UTC 24 | 346816140 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.194157418 | Sep 01 08:59:11 AM UTC 24 | Sep 01 08:59:29 AM UTC 24 | 1033227171 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.489500784 | Sep 01 08:59:22 AM UTC 24 | Sep 01 08:59:32 AM UTC 24 | 595254799 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.891684853 | Sep 01 08:57:19 AM UTC 24 | Sep 01 08:59:33 AM UTC 24 | 8923737989 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.3029538060 | Sep 01 08:59:18 AM UTC 24 | Sep 01 08:59:34 AM UTC 24 | 995163941 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.125625508 | Sep 01 08:58:11 AM UTC 24 | Sep 01 08:59:36 AM UTC 24 | 6333747853 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1373790334 | Sep 01 08:56:25 AM UTC 24 | Sep 01 08:59:38 AM UTC 24 | 22682789133 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1946743190 | Sep 01 08:56:40 AM UTC 24 | Sep 01 08:59:39 AM UTC 24 | 9961835535 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.4223303159 | Sep 01 08:59:29 AM UTC 24 | Sep 01 08:59:39 AM UTC 24 | 464899182 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.400732212 | Sep 01 08:59:22 AM UTC 24 | Sep 01 08:59:40 AM UTC 24 | 410910759 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.262855221 | Sep 01 08:59:28 AM UTC 24 | Sep 01 08:59:41 AM UTC 24 | 508459668 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1648561890 | Sep 01 08:59:13 AM UTC 24 | Sep 01 08:59:43 AM UTC 24 | 1158130264 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.715721891 | Sep 01 08:59:26 AM UTC 24 | Sep 01 08:59:44 AM UTC 24 | 1465144026 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2294735183 | Sep 01 08:56:55 AM UTC 24 | Sep 01 08:59:45 AM UTC 24 | 34964165103 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1269235192 | Sep 01 08:59:37 AM UTC 24 | Sep 01 08:59:45 AM UTC 24 | 271835982 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3747336516 | Sep 01 08:57:30 AM UTC 24 | Sep 01 08:59:46 AM UTC 24 | 13909472519 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.4017278534 | Sep 01 08:59:34 AM UTC 24 | Sep 01 08:59:48 AM UTC 24 | 169705519 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.4094192555 | Sep 01 08:59:28 AM UTC 24 | Sep 01 08:59:48 AM UTC 24 | 203614535 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.972724855 | Sep 01 08:59:40 AM UTC 24 | Sep 01 08:59:49 AM UTC 24 | 365672673 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.89908298 | Sep 01 08:59:44 AM UTC 24 | Sep 01 08:59:51 AM UTC 24 | 333336149 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.4072874796 | Sep 01 08:59:45 AM UTC 24 | Sep 01 08:59:55 AM UTC 24 | 198372795 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4286370906 | Sep 01 08:57:34 AM UTC 24 | Sep 01 08:59:56 AM UTC 24 | 3548140524 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.404909962 | Sep 01 08:59:50 AM UTC 24 | Sep 01 08:59:57 AM UTC 24 | 278197186 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.3252228946 | Sep 01 08:59:40 AM UTC 24 | Sep 01 08:59:58 AM UTC 24 | 492171443 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.504128317 | Sep 01 08:59:39 AM UTC 24 | Sep 01 08:59:58 AM UTC 24 | 1108709083 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1024914574 | Sep 01 08:59:18 AM UTC 24 | Sep 01 08:59:58 AM UTC 24 | 2667295703 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2475837996 | Sep 01 08:59:45 AM UTC 24 | Sep 01 09:00:01 AM UTC 24 | 800115937 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.4090443537 | Sep 01 08:59:52 AM UTC 24 | Sep 01 09:00:02 AM UTC 24 | 144951561 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2054256418 | Sep 01 08:55:05 AM UTC 24 | Sep 01 09:00:03 AM UTC 24 | 3934471784 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.949587691 | Sep 01 08:59:05 AM UTC 24 | Sep 01 09:00:04 AM UTC 24 | 1244983181 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2183365 | Sep 01 08:59:46 AM UTC 24 | Sep 01 09:00:04 AM UTC 24 | 335021616 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.2704938766 | Sep 01 08:59:50 AM UTC 24 | Sep 01 09:00:05 AM UTC 24 | 1748093292 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.4204527441 | Sep 01 08:59:57 AM UTC 24 | Sep 01 09:00:05 AM UTC 24 | 500498409 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.722167143 | Sep 01 08:57:27 AM UTC 24 | Sep 01 09:00:05 AM UTC 24 | 6442954586 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2007837241 | Sep 01 08:59:59 AM UTC 24 | Sep 01 09:00:10 AM UTC 24 | 146054564 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3711965975 | Sep 01 08:59:56 AM UTC 24 | Sep 01 09:00:12 AM UTC 24 | 760272121 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.633025308 | Sep 01 09:00:02 AM UTC 24 | Sep 01 09:00:13 AM UTC 24 | 250219153 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3689499125 | Sep 01 09:00:06 AM UTC 24 | Sep 01 09:00:14 AM UTC 24 | 2488583845 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1395100557 | Sep 01 08:59:59 AM UTC 24 | Sep 01 09:00:15 AM UTC 24 | 341603500 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1561373852 | Sep 01 09:00:06 AM UTC 24 | Sep 01 09:00:15 AM UTC 24 | 367302217 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.434745290 | Sep 01 08:59:58 AM UTC 24 | Sep 01 09:00:16 AM UTC 24 | 3051039445 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3091809194 | Sep 01 09:00:11 AM UTC 24 | Sep 01 09:00:19 AM UTC 24 | 914486042 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3405226325 | Sep 01 09:00:06 AM UTC 24 | Sep 01 09:00:22 AM UTC 24 | 2083788609 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.949954300 | Sep 01 09:00:06 AM UTC 24 | Sep 01 09:00:22 AM UTC 24 | 178729443 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.6719669 | Sep 01 09:00:14 AM UTC 24 | Sep 01 09:00:32 AM UTC 24 | 259453678 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1379666524 | Sep 01 08:56:18 AM UTC 24 | Sep 01 09:00:25 AM UTC 24 | 6473593404 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.190660476 | Sep 01 08:58:57 AM UTC 24 | Sep 01 09:00:28 AM UTC 24 | 6700378083 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1786880536 | Sep 01 08:59:12 AM UTC 24 | Sep 01 09:00:31 AM UTC 24 | 5751700733 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3785547614 | Sep 01 09:00:06 AM UTC 24 | Sep 01 09:00:32 AM UTC 24 | 1205148200 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.965303864 | Sep 01 09:00:25 AM UTC 24 | Sep 01 09:00:33 AM UTC 24 | 1237115123 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3755633528 | Sep 01 09:00:16 AM UTC 24 | Sep 01 09:00:33 AM UTC 24 | 835402546 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2805983419 | Sep 01 09:00:26 AM UTC 24 | Sep 01 09:00:36 AM UTC 24 | 207485971 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3818673748 | Sep 01 09:00:23 AM UTC 24 | Sep 01 09:00:39 AM UTC 24 | 697229866 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.424413151 | Sep 01 09:00:32 AM UTC 24 | Sep 01 09:00:39 AM UTC 24 | 190965791 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1575995942 | Sep 01 08:57:47 AM UTC 24 | Sep 01 09:00:41 AM UTC 24 | 2081580899 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2413177784 | Sep 01 08:57:59 AM UTC 24 | Sep 01 09:00:41 AM UTC 24 | 2338010720 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.1049037817 | Sep 01 09:00:33 AM UTC 24 | Sep 01 09:00:43 AM UTC 24 | 143135549 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.954813685 | Sep 01 09:00:30 AM UTC 24 | Sep 01 09:00:44 AM UTC 24 | 281663934 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.770166075 | Sep 01 09:00:40 AM UTC 24 | Sep 01 09:00:48 AM UTC 24 | 131781953 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.295801704 | Sep 01 08:59:17 AM UTC 24 | Sep 01 09:00:51 AM UTC 24 | 1567488551 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3977488508 | Sep 01 09:00:42 AM UTC 24 | Sep 01 09:00:52 AM UTC 24 | 882708549 ps |
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