Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.65 96.89 92.56 97.67 100.00 98.62 98.05 99.77


Total tests in report: 456
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.62 63.62 92.58 92.58 66.71 66.71 51.00 51.00 40.00 40.00 87.93 87.93 93.55 93.55 13.58 13.58 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.310184639
80.34 16.72 95.93 3.35 77.11 10.39 76.20 25.20 40.00 0.00 90.69 2.76 95.35 1.80 87.12 73.54 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.387871635
88.39 8.05 95.93 0.00 79.63 2.53 89.03 12.82 80.00 40.00 91.03 0.34 95.50 0.15 87.59 0.47 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.388497030
92.28 3.90 96.29 0.36 85.96 6.32 92.10 3.08 93.33 13.33 94.14 3.10 95.65 0.15 88.52 0.94 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.651909830
93.45 1.17 96.41 0.12 86.10 0.14 92.75 0.65 100.00 6.67 94.48 0.34 95.65 0.00 88.76 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2336706488
94.56 1.11 96.65 0.24 88.06 1.97 95.60 2.85 100.00 0.00 96.21 1.72 95.95 0.30 89.46 0.70 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2088588541
95.58 1.02 96.89 0.24 88.76 0.70 95.60 0.00 100.00 0.00 97.24 1.03 95.95 0.00 94.61 5.15 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3619173230
96.08 0.50 96.89 0.00 90.31 1.54 96.45 0.85 100.00 0.00 97.93 0.69 96.10 0.15 94.85 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.389392737
96.37 0.29 96.89 0.00 91.01 0.70 96.55 0.10 100.00 0.00 97.93 0.00 96.40 0.30 95.78 0.94 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1887274643
96.57 0.20 96.89 0.00 91.01 0.00 96.55 0.00 100.00 0.00 97.93 0.00 96.40 0.00 97.19 1.41 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2582603470
96.76 0.19 96.89 0.00 91.15 0.14 96.55 0.00 100.00 0.00 97.93 0.00 97.60 1.20 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2100690100
96.91 0.15 96.89 0.00 91.29 0.14 97.10 0.55 100.00 0.00 98.28 0.34 97.60 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1557313497
97.04 0.13 96.89 0.00 91.85 0.56 97.10 0.00 100.00 0.00 98.62 0.34 97.60 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3163593848
97.16 0.12 96.89 0.00 92.42 0.56 97.38 0.28 100.00 0.00 98.62 0.00 97.60 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.65411895
97.26 0.10 96.89 0.00 92.42 0.00 97.38 0.00 100.00 0.00 98.62 0.00 97.60 0.00 97.89 0.70 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4126242919
97.32 0.07 96.89 0.00 92.42 0.00 97.38 0.00 100.00 0.00 98.62 0.00 97.60 0.00 98.36 0.47 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.861541950
97.39 0.07 96.89 0.00 92.42 0.00 97.38 0.00 100.00 0.00 98.62 0.00 97.60 0.00 98.83 0.47 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2946964407
97.45 0.06 96.89 0.00 92.42 0.00 97.55 0.17 100.00 0.00 98.62 0.00 97.60 0.00 99.06 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1345127092
97.48 0.03 96.89 0.00 92.42 0.00 97.55 0.00 100.00 0.00 98.62 0.00 97.60 0.00 99.30 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.917439108
97.52 0.03 96.89 0.00 92.42 0.00 97.55 0.00 100.00 0.00 98.62 0.00 97.60 0.00 99.53 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3077031244
97.55 0.03 96.89 0.00 92.42 0.00 97.55 0.00 100.00 0.00 98.62 0.00 97.60 0.00 99.77 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3094253682
97.58 0.03 96.89 0.00 92.42 0.00 97.60 0.05 100.00 0.00 98.62 0.00 97.75 0.15 99.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1064489560
97.60 0.02 96.89 0.00 92.42 0.00 97.60 0.00 100.00 0.00 98.62 0.00 97.90 0.15 99.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3651719079
97.62 0.02 96.89 0.00 92.42 0.00 97.60 0.00 100.00 0.00 98.62 0.00 98.05 0.15 99.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.2198868375
97.64 0.02 96.89 0.00 92.56 0.14 97.60 0.00 100.00 0.00 98.62 0.00 98.05 0.00 99.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3049439814
97.65 0.01 96.89 0.00 92.56 0.00 97.67 0.07 100.00 0.00 98.62 0.00 98.05 0.00 99.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2487614667

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3947715987
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1907944512
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.308483588
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3688297501
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3557774170
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2209790183
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1481086975
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1286857692
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1132010675
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2806488175
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1487886570
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3008216660
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.63364137
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.70906660
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3454765782
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3380677940
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.688212708
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1251453522
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4107494199
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2453196665
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2001448388
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2669219246
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1233393542
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2529911552
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2200475691
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1907541445
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.781981015
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.47190847
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4248137147
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2536300452
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3811471813
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3267293164
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3992041993
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2017539812
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2065632049
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.328372999
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1275921998
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.225154771
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3508163495
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3220869052
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1951996032
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3242539454
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.492561785
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2367428025
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3070832471
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4151460503
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3270882915
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1773548985
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.563822619
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2949052333
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1242106205
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1410567917
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.976102983
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3261928818
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2582042566
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1262556086
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3292242803
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1463050836
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4077031109
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1660528417
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2200465940
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3423930219
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1825476219
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.752405706
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2123691254
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3979774451
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3665688931
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.896917899
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1061628228
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2743284577
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.558728585
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3757704578
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1284720984
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2734405811
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.972623434
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1859166739
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3516443340
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1180583904
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1899170444
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1980961524
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3550606810
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.785168616
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/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.2668549565
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/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1877771165
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2824416503
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/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3447627569
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3965484391
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2028998818
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3967692305
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/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.4114972745
/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1072174107
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/workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.324832216



Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.651909830 Sep 04 05:29:55 AM UTC 24 Sep 04 05:30:06 AM UTC 24 279443821 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.222444639 Sep 04 05:30:00 AM UTC 24 Sep 04 05:30:11 AM UTC 24 136292627 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.310184639 Sep 04 05:29:55 AM UTC 24 Sep 04 05:30:13 AM UTC 24 1167568098 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3863769809 Sep 04 05:30:10 AM UTC 24 Sep 04 05:30:18 AM UTC 24 89269713 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1791115807 Sep 04 05:30:03 AM UTC 24 Sep 04 05:30:20 AM UTC 24 695929566 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.604046986 Sep 04 05:30:12 AM UTC 24 Sep 04 05:30:22 AM UTC 24 753723804 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3106757665 Sep 04 05:30:13 AM UTC 24 Sep 04 05:30:22 AM UTC 24 98127335 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2102526975 Sep 04 05:30:12 AM UTC 24 Sep 04 05:30:28 AM UTC 24 1523299892 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.65411895 Sep 04 05:30:20 AM UTC 24 Sep 04 05:30:29 AM UTC 24 262130089 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.2255040079 Sep 04 05:30:23 AM UTC 24 Sep 04 05:30:29 AM UTC 24 543302632 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2487614667 Sep 04 05:30:18 AM UTC 24 Sep 04 05:30:36 AM UTC 24 497485903 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1176729318 Sep 04 05:30:23 AM UTC 24 Sep 04 05:30:38 AM UTC 24 5585407933 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.583736427 Sep 04 05:30:33 AM UTC 24 Sep 04 05:30:40 AM UTC 24 190703142 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.4101238331 Sep 04 05:30:37 AM UTC 24 Sep 04 05:30:48 AM UTC 24 743756446 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.769599227 Sep 04 05:30:23 AM UTC 24 Sep 04 05:30:48 AM UTC 24 311263393 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1557313497 Sep 04 05:30:30 AM UTC 24 Sep 04 05:30:48 AM UTC 24 3544209845 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3893271206 Sep 04 05:30:41 AM UTC 24 Sep 04 05:30:51 AM UTC 24 281852466 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2088588541 Sep 04 05:30:41 AM UTC 24 Sep 04 05:30:57 AM UTC 24 1198839808 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.619745533 Sep 04 05:30:48 AM UTC 24 Sep 04 05:30:57 AM UTC 24 256768389 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2696944514 Sep 04 05:30:49 AM UTC 24 Sep 04 05:30:59 AM UTC 24 493096800 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.2362701758 Sep 04 05:30:48 AM UTC 24 Sep 04 05:31:00 AM UTC 24 277734702 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2474151473 Sep 04 05:30:39 AM UTC 24 Sep 04 05:31:01 AM UTC 24 195942048 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2105563308 Sep 04 05:30:51 AM UTC 24 Sep 04 05:31:05 AM UTC 24 530855415 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1978251313 Sep 04 05:31:00 AM UTC 24 Sep 04 05:31:08 AM UTC 24 179319818 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2166890706 Sep 04 05:30:58 AM UTC 24 Sep 04 05:31:11 AM UTC 24 250422610 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.4114972745 Sep 04 05:31:01 AM UTC 24 Sep 04 05:31:12 AM UTC 24 269002433 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3714909428 Sep 04 05:31:04 AM UTC 24 Sep 04 05:31:15 AM UTC 24 100172360 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3967692305 Sep 04 05:31:05 AM UTC 24 Sep 04 05:31:19 AM UTC 24 1132352314 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3965484391 Sep 04 05:31:11 AM UTC 24 Sep 04 05:31:19 AM UTC 24 91003189 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.389392737 Sep 04 05:31:02 AM UTC 24 Sep 04 05:31:22 AM UTC 24 448361915 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.4181298783 Sep 04 05:31:12 AM UTC 24 Sep 04 05:31:23 AM UTC 24 143669292 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3894086057 Sep 04 05:31:15 AM UTC 24 Sep 04 05:31:26 AM UTC 24 141878433 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1931451528 Sep 04 05:31:23 AM UTC 24 Sep 04 05:31:30 AM UTC 24 522574268 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1393977557 Sep 04 05:31:15 AM UTC 24 Sep 04 05:31:30 AM UTC 24 96285525 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.565993862 Sep 04 05:31:24 AM UTC 24 Sep 04 05:31:34 AM UTC 24 1507984256 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2989519997 Sep 04 05:31:20 AM UTC 24 Sep 04 05:31:36 AM UTC 24 640010536 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.331097641 Sep 04 05:31:27 AM UTC 24 Sep 04 05:31:38 AM UTC 24 783332478 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.387871635 Sep 04 05:30:30 AM UTC 24 Sep 04 05:31:39 AM UTC 24 11938969748 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.242127175 Sep 04 05:31:37 AM UTC 24 Sep 04 05:31:46 AM UTC 24 544415518 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2229778991 Sep 04 05:31:37 AM UTC 24 Sep 04 05:31:47 AM UTC 24 195988545 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.4045537242 Sep 04 05:31:31 AM UTC 24 Sep 04 05:31:48 AM UTC 24 175835089 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3223260963 Sep 04 05:31:39 AM UTC 24 Sep 04 05:31:49 AM UTC 24 181525042 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1064489560 Sep 04 05:30:14 AM UTC 24 Sep 04 05:31:53 AM UTC 24 1730319438 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3971092205 Sep 04 05:31:26 AM UTC 24 Sep 04 05:31:53 AM UTC 24 408105720 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.4255909209 Sep 04 05:31:48 AM UTC 24 Sep 04 05:31:54 AM UTC 24 249826396 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3134756442 Sep 04 05:31:49 AM UTC 24 Sep 04 05:31:58 AM UTC 24 183251806 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3517099949 Sep 04 05:31:50 AM UTC 24 Sep 04 05:32:00 AM UTC 24 437072670 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.2603506944 Sep 04 05:31:38 AM UTC 24 Sep 04 05:32:00 AM UTC 24 623787512 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1345127092 Sep 04 05:30:46 AM UTC 24 Sep 04 05:32:00 AM UTC 24 3855506978 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2805505835 Sep 04 05:31:54 AM UTC 24 Sep 04 05:32:01 AM UTC 24 359812933 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2953504668 Sep 04 05:31:47 AM UTC 24 Sep 04 05:32:02 AM UTC 24 175725983 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1887274643 Sep 04 05:30:06 AM UTC 24 Sep 04 05:32:05 AM UTC 24 979414498 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3896857008 Sep 04 05:30:31 AM UTC 24 Sep 04 05:32:06 AM UTC 24 713374359 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2326985301 Sep 04 05:32:01 AM UTC 24 Sep 04 05:32:10 AM UTC 24 445531929 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.4136014612 Sep 04 05:31:55 AM UTC 24 Sep 04 05:32:11 AM UTC 24 699495265 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.104199094 Sep 04 05:32:01 AM UTC 24 Sep 04 05:32:11 AM UTC 24 100269543 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.4286958090 Sep 04 05:32:07 AM UTC 24 Sep 04 05:32:12 AM UTC 24 521464296 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.201357961 Sep 04 05:32:03 AM UTC 24 Sep 04 05:32:16 AM UTC 24 174147146 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.1212713624 Sep 04 05:32:11 AM UTC 24 Sep 04 05:32:25 AM UTC 24 504863422 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.2698380346 Sep 04 05:32:17 AM UTC 24 Sep 04 05:32:26 AM UTC 24 127103032 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2575398638 Sep 04 05:30:19 AM UTC 24 Sep 04 05:32:27 AM UTC 24 294898893 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3187285533 Sep 04 05:32:08 AM UTC 24 Sep 04 05:32:27 AM UTC 24 930320886 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1553933304 Sep 04 05:32:12 AM UTC 24 Sep 04 05:32:29 AM UTC 24 252060787 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.388497030 Sep 04 05:30:27 AM UTC 24 Sep 04 05:32:30 AM UTC 24 7095143051 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1882867432 Sep 04 05:32:01 AM UTC 24 Sep 04 05:32:32 AM UTC 24 804391350 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.164140558 Sep 04 05:32:26 AM UTC 24 Sep 04 05:32:37 AM UTC 24 144589340 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.1582544570 Sep 04 05:32:31 AM UTC 24 Sep 04 05:32:40 AM UTC 24 564781301 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1656681705 Sep 04 05:32:32 AM UTC 24 Sep 04 05:32:41 AM UTC 24 401630989 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1603221094 Sep 04 05:32:28 AM UTC 24 Sep 04 05:32:41 AM UTC 24 1508752600 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.312698414 Sep 04 05:31:35 AM UTC 24 Sep 04 05:32:42 AM UTC 24 1725090618 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3573324495 Sep 04 05:32:42 AM UTC 24 Sep 04 05:32:48 AM UTC 24 334454068 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.183106590 Sep 04 05:32:26 AM UTC 24 Sep 04 05:32:49 AM UTC 24 1135388657 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2289299875 Sep 04 05:30:59 AM UTC 24 Sep 04 05:32:51 AM UTC 24 1204401246 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.160657570 Sep 04 05:32:43 AM UTC 24 Sep 04 05:32:53 AM UTC 24 586156820 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1330545749 Sep 04 05:32:31 AM UTC 24 Sep 04 05:32:56 AM UTC 24 543129595 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1737996317 Sep 04 05:32:38 AM UTC 24 Sep 04 05:32:56 AM UTC 24 395638492 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1594747499 Sep 04 05:32:53 AM UTC 24 Sep 04 05:33:05 AM UTC 24 495763021 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.4058213791 Sep 04 05:30:46 AM UTC 24 Sep 04 05:33:06 AM UTC 24 372603083 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.264376177 Sep 04 05:32:50 AM UTC 24 Sep 04 05:33:07 AM UTC 24 694631101 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.62109570 Sep 04 05:32:42 AM UTC 24 Sep 04 05:33:12 AM UTC 24 293129861 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3195818555 Sep 04 05:32:58 AM UTC 24 Sep 04 05:33:12 AM UTC 24 516809518 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2444918944 Sep 04 05:32:29 AM UTC 24 Sep 04 05:33:14 AM UTC 24 2910758766 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3945396054 Sep 04 05:32:07 AM UTC 24 Sep 04 05:33:14 AM UTC 24 5947685216 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.1398807049 Sep 04 05:32:56 AM UTC 24 Sep 04 05:33:17 AM UTC 24 1193255026 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.4158801525 Sep 04 05:33:13 AM UTC 24 Sep 04 05:33:22 AM UTC 24 127379412 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.2898632708 Sep 04 05:33:07 AM UTC 24 Sep 04 05:33:22 AM UTC 24 336883039 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2301867713 Sep 04 05:33:14 AM UTC 24 Sep 04 05:33:24 AM UTC 24 386253816 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1211319833 Sep 04 05:33:22 AM UTC 24 Sep 04 05:33:31 AM UTC 24 128598106 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2437300772 Sep 04 05:32:12 AM UTC 24 Sep 04 05:33:32 AM UTC 24 14496153798 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2618423883 Sep 04 05:33:24 AM UTC 24 Sep 04 05:33:34 AM UTC 24 97519293 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.4158077769 Sep 04 05:33:18 AM UTC 24 Sep 04 05:33:34 AM UTC 24 340889312 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2744501351 Sep 04 05:33:23 AM UTC 24 Sep 04 05:33:40 AM UTC 24 318310481 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1944932272 Sep 04 05:33:36 AM UTC 24 Sep 04 05:33:42 AM UTC 24 130899584 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2614626342 Sep 04 05:33:32 AM UTC 24 Sep 04 05:33:45 AM UTC 24 664551151 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.526579572 Sep 04 05:33:13 AM UTC 24 Sep 04 05:33:46 AM UTC 24 560953851 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.375330985 Sep 04 05:33:43 AM UTC 24 Sep 04 05:33:52 AM UTC 24 239275300 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.981893990 Sep 04 05:31:48 AM UTC 24 Sep 04 05:33:57 AM UTC 24 7218148304 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3587356845 Sep 04 05:33:42 AM UTC 24 Sep 04 05:34:00 AM UTC 24 1869148888 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1061765585 Sep 04 05:30:57 AM UTC 24 Sep 04 05:34:01 AM UTC 24 15352144678 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.281833868 Sep 04 05:33:47 AM UTC 24 Sep 04 05:34:03 AM UTC 24 694106130 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.650724201 Sep 04 05:33:58 AM UTC 24 Sep 04 05:34:05 AM UTC 24 89340305 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2028998818 Sep 04 05:31:05 AM UTC 24 Sep 04 05:34:08 AM UTC 24 4545313165 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3049439814 Sep 04 05:30:00 AM UTC 24 Sep 04 05:34:11 AM UTC 24 14626460194 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1575263356 Sep 04 05:34:02 AM UTC 24 Sep 04 05:34:12 AM UTC 24 894419076 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.286645252 Sep 04 05:34:09 AM UTC 24 Sep 04 05:34:16 AM UTC 24 290581535 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2768643772 Sep 04 05:30:41 AM UTC 24 Sep 04 05:34:18 AM UTC 24 19007318317 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3493295673 Sep 04 05:31:43 AM UTC 24 Sep 04 05:34:21 AM UTC 24 2076376046 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.440694667 Sep 04 05:34:01 AM UTC 24 Sep 04 05:34:22 AM UTC 24 3218245918 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1004202224 Sep 04 05:34:13 AM UTC 24 Sep 04 05:34:22 AM UTC 24 186001443 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1317650927 Sep 04 05:34:04 AM UTC 24 Sep 04 05:34:23 AM UTC 24 252233667 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.324832216 Sep 04 05:31:58 AM UTC 24 Sep 04 05:34:28 AM UTC 24 2076622148 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1563172135 Sep 04 05:31:18 AM UTC 24 Sep 04 05:34:28 AM UTC 24 15389855792 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.4152348808 Sep 04 05:34:23 AM UTC 24 Sep 04 05:34:31 AM UTC 24 501518201 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1794822918 Sep 04 05:32:01 AM UTC 24 Sep 04 05:34:33 AM UTC 24 10052219199 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2167482030 Sep 04 05:34:12 AM UTC 24 Sep 04 05:34:34 AM UTC 24 531627872 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3927242335 Sep 04 05:33:06 AM UTC 24 Sep 04 05:34:34 AM UTC 24 3535345832 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.310911934 Sep 04 05:34:19 AM UTC 24 Sep 04 05:34:35 AM UTC 24 300042229 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2294868988 Sep 04 05:34:24 AM UTC 24 Sep 04 05:34:35 AM UTC 24 180754173 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2871821816 Sep 04 05:34:23 AM UTC 24 Sep 04 05:34:35 AM UTC 24 234075789 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3133710135 Sep 04 05:34:32 AM UTC 24 Sep 04 05:34:37 AM UTC 24 85889002 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.486699003 Sep 04 05:32:13 AM UTC 24 Sep 04 05:34:40 AM UTC 24 10654253726 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2336706488 Sep 04 05:32:41 AM UTC 24 Sep 04 05:34:40 AM UTC 24 17227865268 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3912994100 Sep 04 05:34:35 AM UTC 24 Sep 04 05:34:43 AM UTC 24 102054158 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3256881925 Sep 04 05:34:37 AM UTC 24 Sep 04 05:34:44 AM UTC 24 87223365 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2998148961 Sep 04 05:34:28 AM UTC 24 Sep 04 05:34:45 AM UTC 24 759819077 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1235269101 Sep 04 05:32:27 AM UTC 24 Sep 04 05:34:47 AM UTC 24 7930747903 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1079127181 Sep 04 05:34:38 AM UTC 24 Sep 04 05:34:51 AM UTC 24 923130541 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2228064345 Sep 04 05:34:41 AM UTC 24 Sep 04 05:34:51 AM UTC 24 388053494 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1967921359 Sep 04 05:30:19 AM UTC 24 Sep 04 05:34:53 AM UTC 24 4456472684 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3846393812 Sep 04 05:34:46 AM UTC 24 Sep 04 05:34:53 AM UTC 24 172994612 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1013844383 Sep 04 05:31:20 AM UTC 24 Sep 04 05:34:54 AM UTC 24 3320237003 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3786061090 Sep 04 05:34:36 AM UTC 24 Sep 04 05:34:54 AM UTC 24 996364860 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.1705201757 Sep 04 05:34:35 AM UTC 24 Sep 04 05:34:55 AM UTC 24 406871765 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2077515249 Sep 04 05:31:31 AM UTC 24 Sep 04 05:34:56 AM UTC 24 3433460642 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.322837251 Sep 04 05:34:52 AM UTC 24 Sep 04 05:35:01 AM UTC 24 1340032502 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1825443249 Sep 04 05:34:44 AM UTC 24 Sep 04 05:35:03 AM UTC 24 263798019 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3794933418 Sep 04 05:34:37 AM UTC 24 Sep 04 05:35:03 AM UTC 24 560657912 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.2397178558 Sep 04 05:34:55 AM UTC 24 Sep 04 05:35:04 AM UTC 24 132783894 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3195492343 Sep 04 05:32:33 AM UTC 24 Sep 04 05:35:04 AM UTC 24 2176681276 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1072174107 Sep 04 05:31:08 AM UTC 24 Sep 04 05:35:06 AM UTC 24 2587961233 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.214447913 Sep 04 05:34:56 AM UTC 24 Sep 04 05:35:07 AM UTC 24 1920247653 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.4216506431 Sep 04 05:35:03 AM UTC 24 Sep 04 05:35:12 AM UTC 24 149103844 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.3165394698 Sep 04 05:34:54 AM UTC 24 Sep 04 05:35:12 AM UTC 24 256881689 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2011116119 Sep 04 05:34:55 AM UTC 24 Sep 04 05:35:13 AM UTC 24 1084968328 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3682731407 Sep 04 05:34:05 AM UTC 24 Sep 04 05:35:13 AM UTC 24 2763643946 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1678786729 Sep 04 05:35:05 AM UTC 24 Sep 04 05:35:15 AM UTC 24 394121077 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2480027290 Sep 04 05:35:02 AM UTC 24 Sep 04 05:35:15 AM UTC 24 175739457 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.4158152637 Sep 04 05:35:13 AM UTC 24 Sep 04 05:35:18 AM UTC 24 88207195 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.3983196500 Sep 04 05:35:05 AM UTC 24 Sep 04 05:35:19 AM UTC 24 529084737 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2749942454 Sep 04 05:35:08 AM UTC 24 Sep 04 05:35:22 AM UTC 24 170100061 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.4042493110 Sep 04 05:35:13 AM UTC 24 Sep 04 05:35:23 AM UTC 24 118847041 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.3966392637 Sep 04 05:35:14 AM UTC 24 Sep 04 05:35:24 AM UTC 24 110011095 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2839516163 Sep 04 05:35:20 AM UTC 24 Sep 04 05:35:28 AM UTC 24 259654376 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.597492408 Sep 04 05:34:48 AM UTC 24 Sep 04 05:35:28 AM UTC 24 2026907025 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.106169309 Sep 04 05:35:16 AM UTC 24 Sep 04 05:35:30 AM UTC 24 878724498 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3506914130 Sep 04 05:35:23 AM UTC 24 Sep 04 05:35:31 AM UTC 24 122405190 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.4131272280 Sep 04 05:35:24 AM UTC 24 Sep 04 05:35:34 AM UTC 24 186958990 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2299871507 Sep 04 05:35:31 AM UTC 24 Sep 04 05:35:39 AM UTC 24 347513833 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2688558379 Sep 04 05:35:34 AM UTC 24 Sep 04 05:35:44 AM UTC 24 96125437 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3987041412 Sep 04 05:34:45 AM UTC 24 Sep 04 05:35:47 AM UTC 24 5772844781 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2712887272 Sep 04 05:31:54 AM UTC 24 Sep 04 05:35:47 AM UTC 24 4435421224 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1522312077 Sep 04 05:35:29 AM UTC 24 Sep 04 05:35:48 AM UTC 24 261105390 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2636579994 Sep 04 05:35:32 AM UTC 24 Sep 04 05:35:50 AM UTC 24 196391341 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4085620902 Sep 04 05:33:46 AM UTC 24 Sep 04 05:35:52 AM UTC 24 2185226930 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2497076460 Sep 04 05:33:15 AM UTC 24 Sep 04 05:35:54 AM UTC 24 11884943674 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1899228312 Sep 04 05:35:48 AM UTC 24 Sep 04 05:35:55 AM UTC 24 695111775 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2073936250 Sep 04 05:35:49 AM UTC 24 Sep 04 05:35:58 AM UTC 24 386777285 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3132175437 Sep 04 05:34:54 AM UTC 24 Sep 04 05:35:58 AM UTC 24 5879817057 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.457488041 Sep 04 05:35:45 AM UTC 24 Sep 04 05:36:00 AM UTC 24 1038891835 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.2198868375 Sep 04 05:35:51 AM UTC 24 Sep 04 05:36:00 AM UTC 24 143493435 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4126242919 Sep 04 05:33:22 AM UTC 24 Sep 04 05:36:03 AM UTC 24 5578756438 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1207532161 Sep 04 05:34:41 AM UTC 24 Sep 04 05:36:05 AM UTC 24 1831249541 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2920807556 Sep 04 05:35:58 AM UTC 24 Sep 04 05:36:06 AM UTC 24 257628966 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3627325803 Sep 04 05:35:20 AM UTC 24 Sep 04 05:36:07 AM UTC 24 4706852225 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3698074077 Sep 04 05:35:55 AM UTC 24 Sep 04 05:36:07 AM UTC 24 955460565 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3313048692 Sep 04 05:36:00 AM UTC 24 Sep 04 05:36:10 AM UTC 24 521709084 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2756237771 Sep 04 05:30:58 AM UTC 24 Sep 04 05:36:11 AM UTC 24 3986218594 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1860581832 Sep 04 05:33:31 AM UTC 24 Sep 04 05:36:15 AM UTC 24 4615466278 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.630465519 Sep 04 05:36:07 AM UTC 24 Sep 04 05:36:16 AM UTC 24 651272366 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3803153465 Sep 04 05:36:04 AM UTC 24 Sep 04 05:36:16 AM UTC 24 727140944 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.3190927694 Sep 04 05:35:59 AM UTC 24 Sep 04 05:36:17 AM UTC 24 575280676 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1217390089 Sep 04 05:36:08 AM UTC 24 Sep 04 05:36:19 AM UTC 24 558182449 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.243259669 Sep 04 05:33:35 AM UTC 24 Sep 04 05:36:22 AM UTC 24 4339152280 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.4198160943 Sep 04 05:36:16 AM UTC 24 Sep 04 05:36:23 AM UTC 24 436717657 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2454878911 Sep 04 05:34:36 AM UTC 24 Sep 04 05:36:27 AM UTC 24 3881562850 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1608491429 Sep 04 05:36:11 AM UTC 24 Sep 04 05:36:28 AM UTC 24 4147518080 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.163052709 Sep 04 05:36:17 AM UTC 24 Sep 04 05:36:28 AM UTC 24 532442795 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.329374222 Sep 04 05:36:08 AM UTC 24 Sep 04 05:36:33 AM UTC 24 2174095787 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2669594701 Sep 04 05:36:25 AM UTC 24 Sep 04 05:36:33 AM UTC 24 131681242 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3606987048 Sep 04 05:37:36 AM UTC 24 Sep 04 05:37:43 AM UTC 24 89333517 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.4043712234 Sep 04 05:36:20 AM UTC 24 Sep 04 05:36:36 AM UTC 24 499515879 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4114704830 Sep 04 05:36:29 AM UTC 24 Sep 04 05:36:39 AM UTC 24 508067845 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.4120195739 Sep 04 05:36:28 AM UTC 24 Sep 04 05:36:40 AM UTC 24 127677819 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2909636859 Sep 04 05:36:36 AM UTC 24 Sep 04 05:36:44 AM UTC 24 85667187 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2566281764 Sep 04 05:35:29 AM UTC 24 Sep 04 05:36:45 AM UTC 24 1306327511 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3339462039 Sep 04 05:36:17 AM UTC 24 Sep 04 05:36:45 AM UTC 24 2232365990 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.3939225492 Sep 04 05:36:34 AM UTC 24 Sep 04 05:36:49 AM UTC 24 993709395 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3004980927 Sep 04 05:36:42 AM UTC 24 Sep 04 05:36:52 AM UTC 24 371857344 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2339409257 Sep 04 05:35:15 AM UTC 24 Sep 04 05:36:54 AM UTC 24 2737075403 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.1182232174 Sep 04 05:36:49 AM UTC 24 Sep 04 05:36:56 AM UTC 24 350382925 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3526813002 Sep 04 05:34:17 AM UTC 24 Sep 04 05:36:57 AM UTC 24 7929571849 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1063480523 Sep 04 05:35:03 AM UTC 24 Sep 04 05:36:59 AM UTC 24 1518938242 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.145406930 Sep 04 05:32:48 AM UTC 24 Sep 04 05:36:59 AM UTC 24 58416063981 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1059870579 Sep 04 05:36:39 AM UTC 24 Sep 04 05:37:00 AM UTC 24 4110410068 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.478754943 Sep 04 05:36:46 AM UTC 24 Sep 04 05:37:02 AM UTC 24 377801665 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3432887871 Sep 04 05:36:54 AM UTC 24 Sep 04 05:37:04 AM UTC 24 460146402 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1635592290 Sep 04 05:37:00 AM UTC 24 Sep 04 05:37:09 AM UTC 24 500710373 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.41335602 Sep 04 05:35:07 AM UTC 24 Sep 04 05:37:13 AM UTC 24 2191551598 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.375574769 Sep 04 05:36:58 AM UTC 24 Sep 04 05:37:14 AM UTC 24 177002991 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.501815945 Sep 04 05:37:02 AM UTC 24 Sep 04 05:37:16 AM UTC 24 525559167 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.656818933 Sep 04 05:35:39 AM UTC 24 Sep 04 05:37:17 AM UTC 24 5200634928 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2486476315 Sep 04 05:34:29 AM UTC 24 Sep 04 05:37:18 AM UTC 24 2509997404 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.774568097 Sep 04 05:37:01 AM UTC 24 Sep 04 05:37:20 AM UTC 24 147696576 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2849676667 Sep 04 05:37:15 AM UTC 24 Sep 04 05:37:20 AM UTC 24 762130053 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2817347704 Sep 04 05:36:09 AM UTC 24 Sep 04 05:37:23 AM UTC 24 2605447416 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1919889245 Sep 04 05:37:10 AM UTC 24 Sep 04 05:37:24 AM UTC 24 1040036377 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2859623010 Sep 04 05:36:53 AM UTC 24 Sep 04 05:37:27 AM UTC 24 2305506980 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2459538378 Sep 04 05:34:22 AM UTC 24 Sep 04 05:37:28 AM UTC 24 3055920053 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1915323415 Sep 04 05:37:18 AM UTC 24 Sep 04 05:37:29 AM UTC 24 281887683 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2263159605 Sep 04 05:36:22 AM UTC 24 Sep 04 05:37:29 AM UTC 24 2554790508 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3981445996 Sep 04 05:34:57 AM UTC 24 Sep 04 05:37:29 AM UTC 24 1577331626 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.2177362429 Sep 04 05:37:22 AM UTC 24 Sep 04 05:37:30 AM UTC 24 249444751 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3841172795 Sep 04 05:35:56 AM UTC 24 Sep 04 05:37:30 AM UTC 24 2490962520 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4266046576 Sep 04 05:36:02 AM UTC 24 Sep 04 05:37:30 AM UTC 24 4150029911 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1348213090 Sep 04 05:37:25 AM UTC 24 Sep 04 05:37:33 AM UTC 24 130711397 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.2818149489 Sep 04 05:37:24 AM UTC 24 Sep 04 05:37:34 AM UTC 24 337840023 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.721706037 Sep 04 05:37:30 AM UTC 24 Sep 04 05:37:35 AM UTC 24 87488871 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3645343651 Sep 04 05:35:13 AM UTC 24 Sep 04 05:37:36 AM UTC 24 1990649638 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1054189768 Sep 04 05:37:20 AM UTC 24 Sep 04 05:37:38 AM UTC 24 4123749423 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.859315338 Sep 04 05:37:17 AM UTC 24 Sep 04 05:37:38 AM UTC 24 1174436115 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.4203438092 Sep 04 05:37:31 AM UTC 24 Sep 04 05:37:42 AM UTC 24 139655706 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1480397437 Sep 04 05:37:31 AM UTC 24 Sep 04 05:37:42 AM UTC 24 1278597203 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.495534167 Sep 04 05:37:37 AM UTC 24 Sep 04 05:37:45 AM UTC 24 539023047 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2205459677 Sep 04 05:34:04 AM UTC 24 Sep 04 05:37:45 AM UTC 24 3433145052 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1398608039 Sep 04 05:37:30 AM UTC 24 Sep 04 05:37:47 AM UTC 24 251569159 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2562047398 Sep 04 05:37:43 AM UTC 24 Sep 04 05:37:52 AM UTC 24 369141863 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.1166649849 Sep 04 05:37:30 AM UTC 24 Sep 04 05:37:54 AM UTC 24 2970186581 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2824416503 Sep 04 05:38:43 AM UTC 24 Sep 04 05:41:11 AM UTC 24 2575384331 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1458664271 Sep 04 05:37:46 AM UTC 24 Sep 04 05:37:55 AM UTC 24 258700862 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2796171963 Sep 04 05:37:39 AM UTC 24 Sep 04 05:37:56 AM UTC 24 351815931 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1539440159 Sep 04 05:34:52 AM UTC 24 Sep 04 05:37:56 AM UTC 24 3360041245 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2045121473 Sep 04 05:32:51 AM UTC 24 Sep 04 05:37:59 AM UTC 24 15309659762 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1634922605 Sep 04 05:35:25 AM UTC 24 Sep 04 05:37:59 AM UTC 24 4532697632 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.22220526 Sep 04 05:36:45 AM UTC 24 Sep 04 05:38:02 AM UTC 24 4104082110 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2302231184 Sep 04 05:37:55 AM UTC 24 Sep 04 05:38:03 AM UTC 24 168551577 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3124046264 Sep 04 05:37:36 AM UTC 24 Sep 04 05:38:03 AM UTC 24 313896041 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.3798250183 Sep 04 05:37:57 AM UTC 24 Sep 04 05:38:05 AM UTC 24 406984700 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1099125506 Sep 04 05:37:48 AM UTC 24 Sep 04 05:38:07 AM UTC 24 534528409 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2984313330 Sep 04 05:38:02 AM UTC 24 Sep 04 05:38:11 AM UTC 24 272772871 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.870879320 Sep 04 05:37:44 AM UTC 24 Sep 04 05:38:12 AM UTC 24 281292042 ps
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