Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

593044

1

T1

46

T2

276

T3

15

full_word

366634

1

T1

4

T2

28

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	959368	1			T1	50		T2	304		T3	21
auto[TlIntgErrCmd]	109	1			T74	3		T75	5		T76	5
auto[TlIntgErrData]	95	1			T74	4		T75	2		T76	10
auto[TlIntgErrBoth]	106	1			T74	3		T75	3		T76	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175104

1

T1

50

T2

304

T3

21

auto[1]

784574

1

T11

15041

T12

7562

T13

17225

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	86130	1			T1	46		T2	276		T3	15
auto[TlIntgErrNone]	partial	auto[1]	506620	1			T11	9307		T12	5123		T13	10604
auto[TlIntgErrNone]	full_word	auto[0]	88839	1			T1	4		T2	28		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	277779	1			T11	5734		T12	2439		T13	6621
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T75	2		T76	3		T135	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T74	3		T75	3		T76	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T142	1		T143	1		T144	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T141	1		T145	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T74	1		T76	4		T141	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T74	3		T75	2		T76	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T145	1		T142	1		T146	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T147	1		T146	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T74	3		T75	2		T76	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T75	1		T76	3		T135	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T136	1		T140	1		T148	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T149	1		-	-		-	-