Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_kmac_cg	100.00	1	100	1	64	64

---

Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_kmac_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00

Variables for Group Instance rom_ctrl_kmac_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_kmac_done	3	0	3	100.00	100	1	1	0
cp_kmac_ready	4	0	4	100.00	100	1	1	0

Summary for Variable cp_kmac_done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_kmac_done

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
kmac_first	462	1			T5	1		T9	2		T14	2
same_cycle	13	1			T23	1		T49	1		T58	1
rom_first	1201	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_kmac_ready

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_kmac_ready

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stall_repeat	4974164	1			T2	37246		T3	2332		T4	2064
stall_long	378521	1			T2	4444		T30	4409		T134	13289
stall_1	3706665	1			T2	774		T3	4600		T4	4082
zero_delay_5	7036119	1			T1	8180		T2	1		T3	536