Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

613430

1

T1

281

T2

43

T5

19

full_word

381480

1

T1

30

T2

5

T5

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	994590	1			T1	311		T2	48		T5	25
auto[TlIntgErrCmd]	97	1			T66	2		T67	3		T68	3
auto[TlIntgErrData]	108	1			T66	6		T67	3		T68	2
auto[TlIntgErrBoth]	115	1			T66	2		T67	4		T68	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179862

1

T1

311

T2

48

T5

25

auto[1]

815048

1

T11

2283

T12

9772

T13

9646

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	87450	1			T1	281		T2	43		T5	19
auto[TlIntgErrNone]	partial	auto[1]	525684	1			T11	1171		T12	6344		T13	6613
auto[TlIntgErrNone]	full_word	auto[0]	92279	1			T1	30		T2	5		T5	6
auto[TlIntgErrNone]	full_word	auto[1]	289177	1			T11	1112		T12	3428		T13	3033
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T66	1		T67	2		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T66	1		T67	1		T68	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T68	1		T117	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T118	1		T115	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T66	2		T67	2		T68	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T66	3		T67	1		T68	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T118	1		T117	2		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T66	1		T117	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T66	1		T67	2		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T67	1		T68	4		T114	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T66	1		T115	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T67	1		T119	1		T122	2