| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.49 | 96.77 | 91.99 | 97.67 | 100.00 | 98.19 | 98.06 | 99.77 |
| T302 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3041994125 | Sep 18 07:50:47 AM UTC 24 | Sep 18 07:50:54 AM UTC 24 | 490486928 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3123079619 | Sep 18 07:50:46 AM UTC 24 | Sep 18 07:50:56 AM UTC 24 | 276950029 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1565108050 | Sep 18 07:48:39 AM UTC 24 | Sep 18 07:50:56 AM UTC 24 | 3376456414 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3287891890 | Sep 18 07:50:14 AM UTC 24 | Sep 18 07:50:57 AM UTC 24 | 1934111234 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3720585299 | Sep 18 07:50:48 AM UTC 24 | Sep 18 07:50:58 AM UTC 24 | 521572573 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3764134640 | Sep 18 07:50:48 AM UTC 24 | Sep 18 07:50:58 AM UTC 24 | 98109239 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1166264735 | Sep 18 07:50:47 AM UTC 24 | Sep 18 07:50:58 AM UTC 24 | 874650790 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.489908459 | Sep 18 07:50:35 AM UTC 24 | Sep 18 07:51:01 AM UTC 24 | 584282117 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1615223891 | Sep 18 07:50:53 AM UTC 24 | Sep 18 07:51:01 AM UTC 24 | 259920533 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1803773093 | Sep 18 07:50:56 AM UTC 24 | Sep 18 07:51:03 AM UTC 24 | 603806865 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.525308514 | Sep 18 07:50:53 AM UTC 24 | Sep 18 07:51:05 AM UTC 24 | 175980461 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3154476251 | Sep 18 07:50:59 AM UTC 24 | Sep 18 07:51:07 AM UTC 24 | 516740226 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1473118870 | Sep 18 07:47:16 AM UTC 24 | Sep 18 07:51:07 AM UTC 24 | 8050255680 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3323173380 | Sep 18 07:50:57 AM UTC 24 | Sep 18 07:51:09 AM UTC 24 | 1666557500 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.490088910 | Sep 18 07:50:46 AM UTC 24 | Sep 18 07:51:09 AM UTC 24 | 838874457 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1580185399 | Sep 18 07:50:38 AM UTC 24 | Sep 18 07:51:10 AM UTC 24 | 1349689902 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1637701778 | Sep 18 07:51:02 AM UTC 24 | Sep 18 07:51:12 AM UTC 24 | 167640499 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.202215116 | Sep 18 07:50:47 AM UTC 24 | Sep 18 07:51:12 AM UTC 24 | 1288815501 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3043451470 | Sep 18 07:51:06 AM UTC 24 | Sep 18 07:51:13 AM UTC 24 | 333913413 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1146348940 | Sep 18 07:51:00 AM UTC 24 | Sep 18 07:51:15 AM UTC 24 | 219049388 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.493410515 | Sep 18 07:50:31 AM UTC 24 | Sep 18 07:51:16 AM UTC 24 | 1148815721 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2660714598 | Sep 18 07:51:08 AM UTC 24 | Sep 18 07:51:18 AM UTC 24 | 1282187649 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3652725679 | Sep 18 07:50:54 AM UTC 24 | Sep 18 07:51:20 AM UTC 24 | 299436411 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.765284028 | Sep 18 07:51:12 AM UTC 24 | Sep 18 07:51:20 AM UTC 24 | 127719885 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2234591553 | Sep 18 07:49:30 AM UTC 24 | Sep 18 07:51:22 AM UTC 24 | 9707245197 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1960161399 | Sep 18 07:51:04 AM UTC 24 | Sep 18 07:51:22 AM UTC 24 | 996895817 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.4250261840 | Sep 18 07:51:10 AM UTC 24 | Sep 18 07:51:22 AM UTC 24 | 1104348408 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.726840157 | Sep 18 07:48:54 AM UTC 24 | Sep 18 07:51:24 AM UTC 24 | 29482659842 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3013102710 | Sep 18 07:50:00 AM UTC 24 | Sep 18 07:51:25 AM UTC 24 | 18802591086 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1653933683 | Sep 18 07:50:21 AM UTC 24 | Sep 18 07:51:25 AM UTC 24 | 7338670831 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.30603501 | Sep 18 07:47:39 AM UTC 24 | Sep 18 07:51:28 AM UTC 24 | 14399411710 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.981407034 | Sep 18 07:51:08 AM UTC 24 | Sep 18 07:51:32 AM UTC 24 | 1133820358 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3723404207 | Sep 18 07:49:47 AM UTC 24 | Sep 18 07:51:38 AM UTC 24 | 1617086978 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2930143005 | Sep 18 07:48:50 AM UTC 24 | Sep 18 07:51:50 AM UTC 24 | 16302977543 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1278951454 | Sep 18 07:50:17 AM UTC 24 | Sep 18 07:51:51 AM UTC 24 | 4194666905 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3542318841 | Sep 18 07:50:23 AM UTC 24 | Sep 18 07:51:54 AM UTC 24 | 5227321982 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2186779225 | Sep 18 07:49:23 AM UTC 24 | Sep 18 07:51:54 AM UTC 24 | 10639407498 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1265793941 | Sep 18 07:51:09 AM UTC 24 | Sep 18 07:52:15 AM UTC 24 | 911878774 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2396645671 | Sep 18 07:49:41 AM UTC 24 | Sep 18 07:52:21 AM UTC 24 | 5190455090 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1155071459 | Sep 18 07:50:12 AM UTC 24 | Sep 18 07:52:22 AM UTC 24 | 2824211187 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1998074214 | Sep 18 07:51:03 AM UTC 24 | Sep 18 07:52:26 AM UTC 24 | 3782698970 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4139860250 | Sep 18 07:50:16 AM UTC 24 | Sep 18 07:52:27 AM UTC 24 | 4692601220 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1089153601 | Sep 18 07:49:16 AM UTC 24 | Sep 18 07:52:44 AM UTC 24 | 22739778440 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2209536994 | Sep 18 07:50:52 AM UTC 24 | Sep 18 07:52:46 AM UTC 24 | 2443288530 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2451266693 | Sep 18 07:49:58 AM UTC 24 | Sep 18 07:52:47 AM UTC 24 | 2753553160 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.959628700 | Sep 18 07:50:57 AM UTC 24 | Sep 18 07:52:51 AM UTC 24 | 8044336293 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2969607880 | Sep 18 07:50:03 AM UTC 24 | Sep 18 07:52:57 AM UTC 24 | 8587853456 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4158340954 | Sep 18 07:48:32 AM UTC 24 | Sep 18 07:53:13 AM UTC 24 | 19392905740 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1967370409 | Sep 18 07:48:12 AM UTC 24 | Sep 18 07:53:20 AM UTC 24 | 4229091488 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3215045526 | Sep 18 07:49:34 AM UTC 24 | Sep 18 07:53:20 AM UTC 24 | 3466166282 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1385890238 | Sep 18 07:50:46 AM UTC 24 | Sep 18 07:53:22 AM UTC 24 | 18696523110 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.72483311 | Sep 18 07:50:37 AM UTC 24 | Sep 18 07:53:22 AM UTC 24 | 15911851347 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1898719139 | Sep 18 07:50:37 AM UTC 24 | Sep 18 07:53:27 AM UTC 24 | 3013872237 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3898411504 | Sep 18 07:50:29 AM UTC 24 | Sep 18 07:53:29 AM UTC 24 | 13980482151 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.969291843 | Sep 18 07:50:42 AM UTC 24 | Sep 18 07:53:31 AM UTC 24 | 5635429660 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4086222934 | Sep 18 07:50:53 AM UTC 24 | Sep 18 07:53:33 AM UTC 24 | 18400526959 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2908104364 | Sep 18 07:51:10 AM UTC 24 | Sep 18 07:53:36 AM UTC 24 | 4236811656 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3115862538 | Sep 18 07:50:39 AM UTC 24 | Sep 18 07:53:40 AM UTC 24 | 35486187741 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2546381760 | Sep 18 07:49:28 AM UTC 24 | Sep 18 07:53:55 AM UTC 24 | 3753732590 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1756989947 | Sep 18 07:50:07 AM UTC 24 | Sep 18 07:54:08 AM UTC 24 | 7919976048 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.291743344 | Sep 18 07:50:58 AM UTC 24 | Sep 18 07:55:48 AM UTC 24 | 9317438750 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1088900813 | Sep 18 07:51:05 AM UTC 24 | Sep 18 07:56:17 AM UTC 24 | 19685438327 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3047199240 | Sep 18 07:51:17 AM UTC 24 | Sep 18 07:51:24 AM UTC 24 | 251817962 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3736545879 | Sep 18 07:51:14 AM UTC 24 | Sep 18 07:51:26 AM UTC 24 | 462981266 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2840720363 | Sep 18 07:51:19 AM UTC 24 | Sep 18 07:51:27 AM UTC 24 | 273017801 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3523755000 | Sep 18 07:51:21 AM UTC 24 | Sep 18 07:51:29 AM UTC 24 | 251888375 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2313049636 | Sep 18 07:51:23 AM UTC 24 | Sep 18 07:51:30 AM UTC 24 | 497640339 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.403168622 | Sep 18 07:51:23 AM UTC 24 | Sep 18 07:51:30 AM UTC 24 | 85843350 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1277783683 | Sep 18 07:51:21 AM UTC 24 | Sep 18 07:51:30 AM UTC 24 | 560454941 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.135937504 | Sep 18 07:51:23 AM UTC 24 | Sep 18 07:51:30 AM UTC 24 | 492938709 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3096730044 | Sep 18 07:51:25 AM UTC 24 | Sep 18 07:51:32 AM UTC 24 | 144508938 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3603677689 | Sep 18 07:51:26 AM UTC 24 | Sep 18 07:51:33 AM UTC 24 | 1032794750 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.382359949 | Sep 18 07:51:12 AM UTC 24 | Sep 18 07:51:35 AM UTC 24 | 2000640838 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2127672659 | Sep 18 07:51:26 AM UTC 24 | Sep 18 07:51:35 AM UTC 24 | 165095673 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3637561764 | Sep 18 07:51:28 AM UTC 24 | Sep 18 07:51:37 AM UTC 24 | 263175122 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2258424473 | Sep 18 07:51:32 AM UTC 24 | Sep 18 07:51:37 AM UTC 24 | 433720036 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1972620099 | Sep 18 07:51:30 AM UTC 24 | Sep 18 07:51:37 AM UTC 24 | 616776127 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1615726184 | Sep 18 07:51:30 AM UTC 24 | Sep 18 07:51:38 AM UTC 24 | 126200164 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.241609570 | Sep 18 07:51:29 AM UTC 24 | Sep 18 07:51:38 AM UTC 24 | 132524346 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1538156936 | Sep 18 07:51:30 AM UTC 24 | Sep 18 07:51:38 AM UTC 24 | 621573054 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1530505722 | Sep 18 07:51:28 AM UTC 24 | Sep 18 07:51:38 AM UTC 24 | 706648942 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3958510788 | Sep 18 07:51:36 AM UTC 24 | Sep 18 07:51:43 AM UTC 24 | 368528056 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1255190291 | Sep 18 07:52:08 AM UTC 24 | Sep 18 07:52:17 AM UTC 24 | 131852808 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4006206661 | Sep 18 07:51:37 AM UTC 24 | Sep 18 07:51:44 AM UTC 24 | 86268149 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2408021742 | Sep 18 07:51:36 AM UTC 24 | Sep 18 07:51:44 AM UTC 24 | 1546863347 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2099678085 | Sep 18 07:51:33 AM UTC 24 | Sep 18 07:51:44 AM UTC 24 | 89422370 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1499210795 | Sep 18 07:51:34 AM UTC 24 | Sep 18 07:51:45 AM UTC 24 | 493335992 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3360942110 | Sep 18 07:51:38 AM UTC 24 | Sep 18 07:51:45 AM UTC 24 | 757852235 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2636263752 | Sep 18 07:51:38 AM UTC 24 | Sep 18 07:51:46 AM UTC 24 | 255233714 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2616823612 | Sep 18 07:51:38 AM UTC 24 | Sep 18 07:51:47 AM UTC 24 | 199450582 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.100832023 | Sep 18 07:51:38 AM UTC 24 | Sep 18 07:51:47 AM UTC 24 | 522055758 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2400748077 | Sep 18 07:51:42 AM UTC 24 | Sep 18 07:51:50 AM UTC 24 | 322151644 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2438167456 | Sep 18 07:51:39 AM UTC 24 | Sep 18 07:51:50 AM UTC 24 | 578762817 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.328324712 | Sep 18 07:51:25 AM UTC 24 | Sep 18 07:51:52 AM UTC 24 | 373099844 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3604218561 | Sep 18 07:51:44 AM UTC 24 | Sep 18 07:51:53 AM UTC 24 | 127105942 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4175832013 | Sep 18 07:51:45 AM UTC 24 | Sep 18 07:51:53 AM UTC 24 | 655898897 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2104567376 | Sep 18 07:51:46 AM UTC 24 | Sep 18 07:51:53 AM UTC 24 | 170399785 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3852369253 | Sep 18 07:51:47 AM UTC 24 | Sep 18 07:51:53 AM UTC 24 | 554392209 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3886817547 | Sep 18 07:51:46 AM UTC 24 | Sep 18 07:51:54 AM UTC 24 | 694693607 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2002477639 | Sep 18 07:51:45 AM UTC 24 | Sep 18 07:51:55 AM UTC 24 | 132964311 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.358010765 | Sep 18 07:51:46 AM UTC 24 | Sep 18 07:51:57 AM UTC 24 | 572472173 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1338393790 | Sep 18 07:51:51 AM UTC 24 | Sep 18 07:51:57 AM UTC 24 | 86407762 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3791445625 | Sep 18 07:51:51 AM UTC 24 | Sep 18 07:51:57 AM UTC 24 | 249083573 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.607885329 | Sep 18 07:51:48 AM UTC 24 | Sep 18 07:51:57 AM UTC 24 | 702795552 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2913110146 | Sep 18 07:51:53 AM UTC 24 | Sep 18 07:52:01 AM UTC 24 | 89900212 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3169955917 | Sep 18 07:51:53 AM UTC 24 | Sep 18 07:52:01 AM UTC 24 | 126396670 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1484016368 | Sep 18 07:51:54 AM UTC 24 | Sep 18 07:52:01 AM UTC 24 | 1669124135 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1665204036 | Sep 18 07:51:56 AM UTC 24 | Sep 18 07:52:01 AM UTC 24 | 2067386374 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3579266974 | Sep 18 07:51:54 AM UTC 24 | Sep 18 07:52:01 AM UTC 24 | 849752563 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2277980926 | Sep 18 07:51:26 AM UTC 24 | Sep 18 07:52:03 AM UTC 24 | 972717799 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.388906141 | Sep 18 07:51:32 AM UTC 24 | Sep 18 07:52:03 AM UTC 24 | 2282171355 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1728748625 | Sep 18 07:51:51 AM UTC 24 | Sep 18 07:52:04 AM UTC 24 | 924746014 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3252993329 | Sep 18 07:51:53 AM UTC 24 | Sep 18 07:52:05 AM UTC 24 | 498152126 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3237008344 | Sep 18 07:51:58 AM UTC 24 | Sep 18 07:52:05 AM UTC 24 | 95983782 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1389888450 | Sep 18 07:51:56 AM UTC 24 | Sep 18 07:52:06 AM UTC 24 | 759987794 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3382848527 | Sep 18 07:51:58 AM UTC 24 | Sep 18 07:52:07 AM UTC 24 | 236533849 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.454010978 | Sep 18 07:52:02 AM UTC 24 | Sep 18 07:52:09 AM UTC 24 | 588726327 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.386259388 | Sep 18 07:51:58 AM UTC 24 | Sep 18 07:52:09 AM UTC 24 | 129697534 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1845129005 | Sep 18 07:52:02 AM UTC 24 | Sep 18 07:52:10 AM UTC 24 | 127337188 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2174460898 | Sep 18 07:51:39 AM UTC 24 | Sep 18 07:52:13 AM UTC 24 | 3574739467 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1255756007 | Sep 18 07:51:48 AM UTC 24 | Sep 18 07:52:13 AM UTC 24 | 363910396 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.162525377 | Sep 18 07:52:05 AM UTC 24 | Sep 18 07:52:14 AM UTC 24 | 262952969 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4291602644 | Sep 18 07:52:02 AM UTC 24 | Sep 18 07:52:15 AM UTC 24 | 1000283351 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.938623930 | Sep 18 07:52:04 AM UTC 24 | Sep 18 07:52:15 AM UTC 24 | 263737004 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.395133723 | Sep 18 07:52:10 AM UTC 24 | Sep 18 07:52:17 AM UTC 24 | 87446526 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2056408070 | Sep 18 07:52:05 AM UTC 24 | Sep 18 07:52:16 AM UTC 24 | 955321879 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2693534578 | Sep 18 07:52:07 AM UTC 24 | Sep 18 07:52:16 AM UTC 24 | 291200314 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.113154124 | Sep 18 07:52:11 AM UTC 24 | Sep 18 07:52:17 AM UTC 24 | 89231675 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3452513693 | Sep 18 07:52:13 AM UTC 24 | Sep 18 07:52:22 AM UTC 24 | 203255008 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2443259914 | Sep 18 07:52:16 AM UTC 24 | Sep 18 07:52:23 AM UTC 24 | 314022805 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2932289267 | Sep 18 07:52:16 AM UTC 24 | Sep 18 07:52:24 AM UTC 24 | 517979622 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3224424637 | Sep 18 07:52:14 AM UTC 24 | Sep 18 07:52:24 AM UTC 24 | 962779370 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3499423701 | Sep 18 07:52:18 AM UTC 24 | Sep 18 07:52:26 AM UTC 24 | 127077857 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1995706986 | Sep 18 07:52:16 AM UTC 24 | Sep 18 07:52:26 AM UTC 24 | 600768897 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3994840879 | Sep 18 07:52:16 AM UTC 24 | Sep 18 07:52:26 AM UTC 24 | 139612814 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1398513053 | Sep 18 07:51:56 AM UTC 24 | Sep 18 07:52:26 AM UTC 24 | 3139686286 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.228026622 | Sep 18 07:51:58 AM UTC 24 | Sep 18 07:52:27 AM UTC 24 | 7145850412 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2051104785 | Sep 18 07:52:19 AM UTC 24 | Sep 18 07:52:27 AM UTC 24 | 273689268 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2337351706 | Sep 18 07:52:22 AM UTC 24 | Sep 18 07:52:28 AM UTC 24 | 358778802 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1289866286 | Sep 18 07:52:25 AM UTC 24 | Sep 18 07:52:32 AM UTC 24 | 488864904 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3968174887 | Sep 18 07:52:25 AM UTC 24 | Sep 18 07:52:32 AM UTC 24 | 168734330 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2920635374 | Sep 18 07:51:15 AM UTC 24 | Sep 18 07:52:34 AM UTC 24 | 507072085 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2446423259 | Sep 18 07:51:56 AM UTC 24 | Sep 18 07:52:35 AM UTC 24 | 700147993 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3304015038 | Sep 18 07:52:27 AM UTC 24 | Sep 18 07:52:35 AM UTC 24 | 633523279 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1552766792 | Sep 18 07:52:27 AM UTC 24 | Sep 18 07:52:35 AM UTC 24 | 132325081 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4253897681 | Sep 18 07:52:23 AM UTC 24 | Sep 18 07:52:36 AM UTC 24 | 88867120 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.263730606 | Sep 18 07:52:28 AM UTC 24 | Sep 18 07:52:37 AM UTC 24 | 1125548065 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.577212566 | Sep 18 07:52:28 AM UTC 24 | Sep 18 07:52:38 AM UTC 24 | 536364456 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2997205430 | Sep 18 07:52:27 AM UTC 24 | Sep 18 07:52:39 AM UTC 24 | 127604860 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3547458324 | Sep 18 07:52:28 AM UTC 24 | Sep 18 07:52:40 AM UTC 24 | 519274587 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1978016735 | Sep 18 07:52:35 AM UTC 24 | Sep 18 07:52:42 AM UTC 24 | 350995036 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.105433296 | Sep 18 07:52:34 AM UTC 24 | Sep 18 07:52:42 AM UTC 24 | 133655339 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1237748060 | Sep 18 07:52:14 AM UTC 24 | Sep 18 07:52:45 AM UTC 24 | 2241392768 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4251948060 | Sep 18 07:52:04 AM UTC 24 | Sep 18 07:52:45 AM UTC 24 | 552613095 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2047872925 | Sep 18 07:52:36 AM UTC 24 | Sep 18 07:52:46 AM UTC 24 | 587364171 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.361157684 | Sep 18 07:52:39 AM UTC 24 | Sep 18 07:52:46 AM UTC 24 | 88992952 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2216264483 | Sep 18 07:52:37 AM UTC 24 | Sep 18 07:52:46 AM UTC 24 | 497497715 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4234832833 | Sep 18 07:52:36 AM UTC 24 | Sep 18 07:52:48 AM UTC 24 | 761216526 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.683485746 | Sep 18 07:52:16 AM UTC 24 | Sep 18 07:52:49 AM UTC 24 | 1943294298 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3324751512 | Sep 18 07:52:02 AM UTC 24 | Sep 18 07:52:49 AM UTC 24 | 891611176 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3225756771 | Sep 18 07:52:40 AM UTC 24 | Sep 18 07:52:50 AM UTC 24 | 538985722 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1096689377 | Sep 18 07:52:07 AM UTC 24 | Sep 18 07:52:50 AM UTC 24 | 3280384192 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2137234544 | Sep 18 07:52:46 AM UTC 24 | Sep 18 07:52:53 AM UTC 24 | 384101417 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1255544008 | Sep 18 07:52:46 AM UTC 24 | Sep 18 07:52:54 AM UTC 24 | 379245203 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3999796060 | Sep 18 07:52:48 AM UTC 24 | Sep 18 07:52:55 AM UTC 24 | 497706191 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1346603106 | Sep 18 07:52:47 AM UTC 24 | Sep 18 07:52:55 AM UTC 24 | 131949223 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.585419341 | Sep 18 07:52:44 AM UTC 24 | Sep 18 07:52:55 AM UTC 24 | 334670752 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3944480766 | Sep 18 07:52:23 AM UTC 24 | Sep 18 07:52:55 AM UTC 24 | 3253149000 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.180562177 | Sep 18 07:52:46 AM UTC 24 | Sep 18 07:52:56 AM UTC 24 | 101248746 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3811708716 | Sep 18 07:52:48 AM UTC 24 | Sep 18 07:52:56 AM UTC 24 | 102590465 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3996133960 | Sep 18 07:52:51 AM UTC 24 | Sep 18 07:52:57 AM UTC 24 | 86724568 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3621050402 | Sep 18 07:52:51 AM UTC 24 | Sep 18 07:52:59 AM UTC 24 | 263034750 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4150318337 | Sep 18 07:52:52 AM UTC 24 | Sep 18 07:52:59 AM UTC 24 | 139309521 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2018178099 | Sep 18 07:52:47 AM UTC 24 | Sep 18 07:53:00 AM UTC 24 | 487254931 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2252158567 | Sep 18 07:52:15 AM UTC 24 | Sep 18 07:53:00 AM UTC 24 | 199961283 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.372001339 | Sep 18 07:52:49 AM UTC 24 | Sep 18 07:53:01 AM UTC 24 | 429182036 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4223806066 | Sep 18 07:52:36 AM UTC 24 | Sep 18 07:53:03 AM UTC 24 | 537732481 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1064575560 | Sep 18 07:51:34 AM UTC 24 | Sep 18 07:53:03 AM UTC 24 | 538188157 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1617732279 | Sep 18 07:52:56 AM UTC 24 | Sep 18 07:53:03 AM UTC 24 | 168040971 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4105728414 | Sep 18 07:52:56 AM UTC 24 | Sep 18 07:53:04 AM UTC 24 | 126819453 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.195110993 | Sep 18 07:52:17 AM UTC 24 | Sep 18 07:53:04 AM UTC 24 | 602915921 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3954371038 | Sep 18 07:52:56 AM UTC 24 | Sep 18 07:53:05 AM UTC 24 | 220140054 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3527197376 | Sep 18 07:52:54 AM UTC 24 | Sep 18 07:53:05 AM UTC 24 | 163214549 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1515596506 | Sep 18 07:52:58 AM UTC 24 | Sep 18 07:53:06 AM UTC 24 | 113628854 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1709346633 | Sep 18 07:52:27 AM UTC 24 | Sep 18 07:53:06 AM UTC 24 | 16678846303 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2604277986 | Sep 18 07:52:58 AM UTC 24 | Sep 18 07:53:07 AM UTC 24 | 567740031 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3917228368 | Sep 18 07:52:57 AM UTC 24 | Sep 18 07:53:08 AM UTC 24 | 89567367 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1983858185 | Sep 18 07:52:28 AM UTC 24 | Sep 18 07:53:08 AM UTC 24 | 803492634 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1868139071 | Sep 18 07:52:59 AM UTC 24 | Sep 18 07:53:09 AM UTC 24 | 278646538 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2256135048 | Sep 18 07:52:24 AM UTC 24 | Sep 18 07:53:11 AM UTC 24 | 2607594865 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3337331684 | Sep 18 07:51:39 AM UTC 24 | Sep 18 07:53:12 AM UTC 24 | 568804274 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3783539766 | Sep 18 07:52:33 AM UTC 24 | Sep 18 07:53:13 AM UTC 24 | 429143568 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.228130556 | Sep 18 07:52:40 AM UTC 24 | Sep 18 07:53:16 AM UTC 24 | 6037698106 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2962151908 | Sep 18 07:52:37 AM UTC 24 | Sep 18 07:53:19 AM UTC 24 | 293872062 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4046491836 | Sep 18 07:52:47 AM UTC 24 | Sep 18 07:53:20 AM UTC 24 | 563610942 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1608348816 | Sep 18 07:52:49 AM UTC 24 | Sep 18 07:53:21 AM UTC 24 | 798226258 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2348079168 | Sep 18 07:52:01 AM UTC 24 | Sep 18 07:53:21 AM UTC 24 | 836923805 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1287318962 | Sep 18 07:52:44 AM UTC 24 | Sep 18 07:53:28 AM UTC 24 | 186708307 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3446004105 | Sep 18 07:52:56 AM UTC 24 | Sep 18 07:53:29 AM UTC 24 | 8354192775 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2332121696 | Sep 18 07:51:50 AM UTC 24 | Sep 18 07:53:31 AM UTC 24 | 295209458 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.712347860 | Sep 18 07:52:50 AM UTC 24 | Sep 18 07:53:31 AM UTC 24 | 938544752 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3716371338 | Sep 18 07:52:47 AM UTC 24 | Sep 18 07:53:33 AM UTC 24 | 250925522 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1961321000 | Sep 18 07:52:10 AM UTC 24 | Sep 18 07:53:34 AM UTC 24 | 1012335917 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3138448137 | Sep 18 07:52:53 AM UTC 24 | Sep 18 07:53:41 AM UTC 24 | 6242835586 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.147873782 | Sep 18 07:52:55 AM UTC 24 | Sep 18 07:53:42 AM UTC 24 | 375157094 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2140764504 | Sep 18 07:52:27 AM UTC 24 | Sep 18 07:53:45 AM UTC 24 | 1476897654 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4081003640 | Sep 18 07:52:57 AM UTC 24 | Sep 18 07:54:14 AM UTC 24 | 261910108 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.117936043 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1069645549 ps |
| CPU time | 19.95 seconds |
| Started | Sep 18 07:42:06 AM UTC 24 |
| Finished | Sep 18 07:42:27 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117936043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.117936043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.755814957 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8679250492 ps |
| CPU time | 189.48 seconds |
| Started | Sep 18 07:42:19 AM UTC 24 |
| Finished | Sep 18 07:45:31 AM UTC 24 |
| Peak memory | 233152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=755814957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.rom_ctrl_stress_all_with_rand_reset.755814957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2794150632 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12166674301 ps |
| CPU time | 152.29 seconds |
| Started | Sep 18 07:43:24 AM UTC 24 |
| Finished | Sep 18 07:45:59 AM UTC 24 |
| Peak memory | 225956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794150632 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.2794150632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.226842072 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 724147519 ps |
| CPU time | 84.38 seconds |
| Started | Sep 18 07:42:48 AM UTC 24 |
| Finished | Sep 18 07:44:14 AM UTC 24 |
| Peak memory | 259264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226842072 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.226842072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1166870571 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6554920575 ps |
| CPU time | 108.79 seconds |
| Started | Sep 18 07:46:19 AM UTC 24 |
| Finished | Sep 18 07:48:10 AM UTC 24 |
| Peak memory | 247496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166870571 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.1166870571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.448533675 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 992757167 ps |
| CPU time | 34.25 seconds |
| Started | Sep 18 07:43:26 AM UTC 24 |
| Finished | Sep 18 07:44:02 AM UTC 24 |
| Peak memory | 230976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=448533675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.rom_ctrl_stress_all_with_rand_reset.448533675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1064575560 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 538188157 ps |
| CPU time | 87.22 seconds |
| Started | Sep 18 07:51:34 AM UTC 24 |
| Finished | Sep 18 07:53:03 AM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064575560 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.1064575560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3509274124 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 250977622 ps |
| CPU time | 16.39 seconds |
| Started | Sep 18 07:42:17 AM UTC 24 |
| Finished | Sep 18 07:42:34 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509274124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3509274124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.403168622 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 85843350 ps |
| CPU time | 6.26 seconds |
| Started | Sep 18 07:51:23 AM UTC 24 |
| Finished | Sep 18 07:51:30 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403168622 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.403168622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2140764504 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1476897654 ps |
| CPU time | 75.67 seconds |
| Started | Sep 18 07:52:27 AM UTC 24 |
| Finished | Sep 18 07:53:45 AM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140764504 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.2140764504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3995440008 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3942206549 ps |
| CPU time | 21.05 seconds |
| Started | Sep 18 07:44:40 AM UTC 24 |
| Finished | Sep 18 07:45:02 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995440008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3995440008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3546216436 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 168264669 ps |
| CPU time | 6.18 seconds |
| Started | Sep 18 07:43:36 AM UTC 24 |
| Finished | Sep 18 07:43:44 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546216436 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3546216436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3473028852 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1002742872 ps |
| CPU time | 18.91 seconds |
| Started | Sep 18 07:48:52 AM UTC 24 |
| Finished | Sep 18 07:49:12 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347302885 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.3473028852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3783539766 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 429143568 ps |
| CPU time | 39.09 seconds |
| Started | Sep 18 07:52:33 AM UTC 24 |
| Finished | Sep 18 07:53:13 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783539766 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.3783539766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1961321000 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1012335917 ps |
| CPU time | 82.67 seconds |
| Started | Sep 18 07:52:10 AM UTC 24 |
| Finished | Sep 18 07:53:34 AM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961321000 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.1961321000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1452291024 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 96045362 ps |
| CPU time | 8.49 seconds |
| Started | Sep 18 07:42:07 AM UTC 24 |
| Finished | Sep 18 07:42:16 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452291024 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1452291024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3085721720 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 7037642052 ps |
| CPU time | 253.01 seconds |
| Started | Sep 18 07:44:44 AM UTC 24 |
| Finished | Sep 18 07:49:01 AM UTC 24 |
| Peak memory | 241280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3085721720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3085721720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.328324712 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 373099844 ps |
| CPU time | 26.24 seconds |
| Started | Sep 18 07:51:25 AM UTC 24 |
| Finished | Sep 18 07:51:52 AM UTC 24 |
| Peak memory | 222160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328324712 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.328324712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1804427635 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1601906476 ps |
| CPU time | 95.06 seconds |
| Started | Sep 18 07:46:59 AM UTC 24 |
| Finished | Sep 18 07:48:36 AM UTC 24 |
| Peak memory | 258692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804427635 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.1804427635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.135937504 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 492938709 ps |
| CPU time | 6.6 seconds |
| Started | Sep 18 07:51:23 AM UTC 24 |
| Finished | Sep 18 07:51:30 AM UTC 24 |
| Peak memory | 222136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135937504 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.135937504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1546911774 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 381631244 ps |
| CPU time | 9.47 seconds |
| Started | Sep 18 07:47:02 AM UTC 24 |
| Finished | Sep 18 07:47:13 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546911774 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1546911774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2313049636 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 497640339 ps |
| CPU time | 6.28 seconds |
| Started | Sep 18 07:51:23 AM UTC 24 |
| Finished | Sep 18 07:51:30 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313049636 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.2313049636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1277783683 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 560454941 ps |
| CPU time | 8.77 seconds |
| Started | Sep 18 07:51:21 AM UTC 24 |
| Finished | Sep 18 07:51:30 AM UTC 24 |
| Peak memory | 222196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277783683 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.1277783683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3096730044 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 144508938 ps |
| CPU time | 6.01 seconds |
| Started | Sep 18 07:51:25 AM UTC 24 |
| Finished | Sep 18 07:51:32 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3096730044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r om_ctrl_csr_mem_rw_with_rand_reset.3096730044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3523755000 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 251888375 ps |
| CPU time | 7.38 seconds |
| Started | Sep 18 07:51:21 AM UTC 24 |
| Finished | Sep 18 07:51:29 AM UTC 24 |
| Peak memory | 229536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523755000 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3523755000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2840720363 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 273017801 ps |
| CPU time | 7.41 seconds |
| Started | Sep 18 07:51:19 AM UTC 24 |
| Finished | Sep 18 07:51:27 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840720363 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.2840720363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3047199240 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 251817962 ps |
| CPU time | 6.88 seconds |
| Started | Sep 18 07:51:17 AM UTC 24 |
| Finished | Sep 18 07:51:24 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047199240 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.3047199240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.382359949 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2000640838 ps |
| CPU time | 20.95 seconds |
| Started | Sep 18 07:51:12 AM UTC 24 |
| Finished | Sep 18 07:51:35 AM UTC 24 |
| Peak memory | 222288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382359949 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.382359949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3736545879 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 462981266 ps |
| CPU time | 10.02 seconds |
| Started | Sep 18 07:51:14 AM UTC 24 |
| Finished | Sep 18 07:51:26 AM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736545879 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3736545879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2920635374 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 507072085 ps |
| CPU time | 77.18 seconds |
| Started | Sep 18 07:51:15 AM UTC 24 |
| Finished | Sep 18 07:52:34 AM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920635374 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.2920635374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1538156936 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 621573054 ps |
| CPU time | 6.52 seconds |
| Started | Sep 18 07:51:30 AM UTC 24 |
| Finished | Sep 18 07:51:38 AM UTC 24 |
| Peak memory | 222092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538156936 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.1538156936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1615726184 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 126200164 ps |
| CPU time | 5.99 seconds |
| Started | Sep 18 07:51:30 AM UTC 24 |
| Finished | Sep 18 07:51:38 AM UTC 24 |
| Peak memory | 222196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615726184 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.1615726184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1530505722 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 706648942 ps |
| CPU time | 9.03 seconds |
| Started | Sep 18 07:51:28 AM UTC 24 |
| Finished | Sep 18 07:51:38 AM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530505722 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.1530505722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2258424473 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 433720036 ps |
| CPU time | 4.4 seconds |
| Started | Sep 18 07:51:32 AM UTC 24 |
| Finished | Sep 18 07:51:37 AM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2258424473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r om_ctrl_csr_mem_rw_with_rand_reset.2258424473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.241609570 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 132524346 ps |
| CPU time | 7.3 seconds |
| Started | Sep 18 07:51:29 AM UTC 24 |
| Finished | Sep 18 07:51:38 AM UTC 24 |
| Peak memory | 229384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241609570 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.241609570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3637561764 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 263175122 ps |
| CPU time | 7.34 seconds |
| Started | Sep 18 07:51:28 AM UTC 24 |
| Finished | Sep 18 07:51:37 AM UTC 24 |
| Peak memory | 221904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637561764 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.3637561764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3603677689 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1032794750 ps |
| CPU time | 6.05 seconds |
| Started | Sep 18 07:51:26 AM UTC 24 |
| Finished | Sep 18 07:51:33 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603677689 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.3603677689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1972620099 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 616776127 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 07:51:30 AM UTC 24 |
| Finished | Sep 18 07:51:37 AM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972620099 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.1972620099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2127672659 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 165095673 ps |
| CPU time | 8.25 seconds |
| Started | Sep 18 07:51:26 AM UTC 24 |
| Finished | Sep 18 07:51:35 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127672659 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2127672659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2277980926 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 972717799 ps |
| CPU time | 35.92 seconds |
| Started | Sep 18 07:51:26 AM UTC 24 |
| Finished | Sep 18 07:52:03 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277980926 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.2277980926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2337351706 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 358778802 ps |
| CPU time | 4.94 seconds |
| Started | Sep 18 07:52:22 AM UTC 24 |
| Finished | Sep 18 07:52:28 AM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2337351706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. rom_ctrl_csr_mem_rw_with_rand_reset.2337351706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3499423701 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 127077857 ps |
| CPU time | 7.27 seconds |
| Started | Sep 18 07:52:18 AM UTC 24 |
| Finished | Sep 18 07:52:26 AM UTC 24 |
| Peak memory | 221988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499423701 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3499423701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.683485746 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1943294298 ps |
| CPU time | 30.87 seconds |
| Started | Sep 18 07:52:16 AM UTC 24 |
| Finished | Sep 18 07:52:49 AM UTC 24 |
| Peak memory | 222228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683485746 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.683485746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2051104785 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 273689268 ps |
| CPU time | 7.46 seconds |
| Started | Sep 18 07:52:19 AM UTC 24 |
| Finished | Sep 18 07:52:27 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051104785 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.2051104785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1995706986 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 600768897 ps |
| CPU time | 8.67 seconds |
| Started | Sep 18 07:52:16 AM UTC 24 |
| Finished | Sep 18 07:52:26 AM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995706986 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1995706986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.195110993 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 602915921 ps |
| CPU time | 45.4 seconds |
| Started | Sep 18 07:52:17 AM UTC 24 |
| Finished | Sep 18 07:53:04 AM UTC 24 |
| Peak memory | 229468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195110993 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.195110993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3304015038 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 633523279 ps |
| CPU time | 6.97 seconds |
| Started | Sep 18 07:52:27 AM UTC 24 |
| Finished | Sep 18 07:52:35 AM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3304015038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rom_ctrl_csr_mem_rw_with_rand_reset.3304015038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1289866286 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 488864904 ps |
| CPU time | 6.16 seconds |
| Started | Sep 18 07:52:25 AM UTC 24 |
| Finished | Sep 18 07:52:32 AM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289866286 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1289866286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3944480766 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3253149000 ps |
| CPU time | 31.34 seconds |
| Started | Sep 18 07:52:23 AM UTC 24 |
| Finished | Sep 18 07:52:55 AM UTC 24 |
| Peak memory | 222284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944480766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.3944480766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3968174887 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 168734330 ps |
| CPU time | 6.26 seconds |
| Started | Sep 18 07:52:25 AM UTC 24 |
| Finished | Sep 18 07:52:32 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968174887 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.3968174887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4253897681 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 88867120 ps |
| CPU time | 12.06 seconds |
| Started | Sep 18 07:52:23 AM UTC 24 |
| Finished | Sep 18 07:52:36 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253897681 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4253897681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2256135048 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2607594865 ps |
| CPU time | 45 seconds |
| Started | Sep 18 07:52:24 AM UTC 24 |
| Finished | Sep 18 07:53:11 AM UTC 24 |
| Peak memory | 224300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256135048 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.2256135048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.577212566 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 536364456 ps |
| CPU time | 8.42 seconds |
| Started | Sep 18 07:52:28 AM UTC 24 |
| Finished | Sep 18 07:52:38 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=577212566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.r om_ctrl_csr_mem_rw_with_rand_reset.577212566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1552766792 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 132325081 ps |
| CPU time | 7.18 seconds |
| Started | Sep 18 07:52:27 AM UTC 24 |
| Finished | Sep 18 07:52:35 AM UTC 24 |
| Peak memory | 222188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552766792 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1552766792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1709346633 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 16678846303 ps |
| CPU time | 37.45 seconds |
| Started | Sep 18 07:52:27 AM UTC 24 |
| Finished | Sep 18 07:53:06 AM UTC 24 |
| Peak memory | 222148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709346633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.1709346633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.263730606 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1125548065 ps |
| CPU time | 7.29 seconds |
| Started | Sep 18 07:52:28 AM UTC 24 |
| Finished | Sep 18 07:52:37 AM UTC 24 |
| Peak memory | 229416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263730606 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.263730606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2997205430 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 127604860 ps |
| CPU time | 11.17 seconds |
| Started | Sep 18 07:52:27 AM UTC 24 |
| Finished | Sep 18 07:52:39 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997205430 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2997205430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2047872925 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 587364171 ps |
| CPU time | 8.71 seconds |
| Started | Sep 18 07:52:36 AM UTC 24 |
| Finished | Sep 18 07:52:46 AM UTC 24 |
| Peak memory | 228276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2047872925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. rom_ctrl_csr_mem_rw_with_rand_reset.2047872925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.105433296 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 133655339 ps |
| CPU time | 7.53 seconds |
| Started | Sep 18 07:52:34 AM UTC 24 |
| Finished | Sep 18 07:52:42 AM UTC 24 |
| Peak memory | 222060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105433296 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.105433296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1983858185 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 803492634 ps |
| CPU time | 38.29 seconds |
| Started | Sep 18 07:52:28 AM UTC 24 |
| Finished | Sep 18 07:53:08 AM UTC 24 |
| Peak memory | 222156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983858185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.1983858185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1978016735 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 350995036 ps |
| CPU time | 6.25 seconds |
| Started | Sep 18 07:52:35 AM UTC 24 |
| Finished | Sep 18 07:52:42 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978016735 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.1978016735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3547458324 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 519274587 ps |
| CPU time | 10.36 seconds |
| Started | Sep 18 07:52:28 AM UTC 24 |
| Finished | Sep 18 07:52:40 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547458324 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3547458324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3225756771 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 538985722 ps |
| CPU time | 6.64 seconds |
| Started | Sep 18 07:52:40 AM UTC 24 |
| Finished | Sep 18 07:52:50 AM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3225756771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rom_ctrl_csr_mem_rw_with_rand_reset.3225756771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2216264483 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 497497715 ps |
| CPU time | 7.5 seconds |
| Started | Sep 18 07:52:37 AM UTC 24 |
| Finished | Sep 18 07:52:46 AM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216264483 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2216264483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4223806066 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 537732481 ps |
| CPU time | 25.48 seconds |
| Started | Sep 18 07:52:36 AM UTC 24 |
| Finished | Sep 18 07:53:03 AM UTC 24 |
| Peak memory | 222156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223806066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.4223806066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.361157684 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 88992952 ps |
| CPU time | 5.92 seconds |
| Started | Sep 18 07:52:39 AM UTC 24 |
| Finished | Sep 18 07:52:46 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361157684 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.361157684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4234832833 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 761216526 ps |
| CPU time | 11.02 seconds |
| Started | Sep 18 07:52:36 AM UTC 24 |
| Finished | Sep 18 07:52:48 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234832833 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4234832833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2962151908 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 293872062 ps |
| CPU time | 40.07 seconds |
| Started | Sep 18 07:52:37 AM UTC 24 |
| Finished | Sep 18 07:53:19 AM UTC 24 |
| Peak memory | 224184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962151908 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.2962151908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2137234544 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 384101417 ps |
| CPU time | 6.27 seconds |
| Started | Sep 18 07:52:46 AM UTC 24 |
| Finished | Sep 18 07:52:53 AM UTC 24 |
| Peak memory | 229604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2137234544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rom_ctrl_csr_mem_rw_with_rand_reset.2137234544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1255544008 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 379245203 ps |
| CPU time | 6.91 seconds |
| Started | Sep 18 07:52:46 AM UTC 24 |
| Finished | Sep 18 07:52:54 AM UTC 24 |
| Peak memory | 222060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255544008 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1255544008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.228130556 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 6037698106 ps |
| CPU time | 31.96 seconds |
| Started | Sep 18 07:52:40 AM UTC 24 |
| Finished | Sep 18 07:53:16 AM UTC 24 |
| Peak memory | 222228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228130556 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.228130556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.180562177 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 101248746 ps |
| CPU time | 8.89 seconds |
| Started | Sep 18 07:52:46 AM UTC 24 |
| Finished | Sep 18 07:52:56 AM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180562177 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.180562177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.585419341 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 334670752 ps |
| CPU time | 9.4 seconds |
| Started | Sep 18 07:52:44 AM UTC 24 |
| Finished | Sep 18 07:52:55 AM UTC 24 |
| Peak memory | 226388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585419341 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.585419341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1287318962 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 186708307 ps |
| CPU time | 41.39 seconds |
| Started | Sep 18 07:52:44 AM UTC 24 |
| Finished | Sep 18 07:53:28 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287318962 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.1287318962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3811708716 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 102590465 ps |
| CPU time | 6.72 seconds |
| Started | Sep 18 07:52:48 AM UTC 24 |
| Finished | Sep 18 07:52:56 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3811708716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rom_ctrl_csr_mem_rw_with_rand_reset.3811708716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1346603106 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 131949223 ps |
| CPU time | 6.93 seconds |
| Started | Sep 18 07:52:47 AM UTC 24 |
| Finished | Sep 18 07:52:55 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346603106 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1346603106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4046491836 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 563610942 ps |
| CPU time | 32.3 seconds |
| Started | Sep 18 07:52:47 AM UTC 24 |
| Finished | Sep 18 07:53:20 AM UTC 24 |
| Peak memory | 222156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046491836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.4046491836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3999796060 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 497706191 ps |
| CPU time | 5.23 seconds |
| Started | Sep 18 07:52:48 AM UTC 24 |
| Finished | Sep 18 07:52:55 AM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999796060 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.3999796060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2018178099 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 487254931 ps |
| CPU time | 11.81 seconds |
| Started | Sep 18 07:52:47 AM UTC 24 |
| Finished | Sep 18 07:53:00 AM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018178099 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2018178099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3716371338 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 250925522 ps |
| CPU time | 44.3 seconds |
| Started | Sep 18 07:52:47 AM UTC 24 |
| Finished | Sep 18 07:53:33 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716371338 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.3716371338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4150318337 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 139309521 ps |
| CPU time | 5.71 seconds |
| Started | Sep 18 07:52:52 AM UTC 24 |
| Finished | Sep 18 07:52:59 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4150318337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rom_ctrl_csr_mem_rw_with_rand_reset.4150318337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3996133960 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 86724568 ps |
| CPU time | 4.88 seconds |
| Started | Sep 18 07:52:51 AM UTC 24 |
| Finished | Sep 18 07:52:57 AM UTC 24 |
| Peak memory | 222060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996133960 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3996133960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1608348816 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 798226258 ps |
| CPU time | 30.54 seconds |
| Started | Sep 18 07:52:49 AM UTC 24 |
| Finished | Sep 18 07:53:21 AM UTC 24 |
| Peak memory | 222220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608348816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.1608348816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3621050402 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 263034750 ps |
| CPU time | 6.08 seconds |
| Started | Sep 18 07:52:51 AM UTC 24 |
| Finished | Sep 18 07:52:59 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621050402 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.3621050402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.372001339 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 429182036 ps |
| CPU time | 11.13 seconds |
| Started | Sep 18 07:52:49 AM UTC 24 |
| Finished | Sep 18 07:53:01 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372001339 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.372001339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.712347860 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 938544752 ps |
| CPU time | 39.86 seconds |
| Started | Sep 18 07:52:50 AM UTC 24 |
| Finished | Sep 18 07:53:31 AM UTC 24 |
| Peak memory | 224240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712347860 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.712347860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3954371038 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 220140054 ps |
| CPU time | 7.53 seconds |
| Started | Sep 18 07:52:56 AM UTC 24 |
| Finished | Sep 18 07:53:05 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3954371038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. rom_ctrl_csr_mem_rw_with_rand_reset.3954371038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1617732279 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 168040971 ps |
| CPU time | 6.33 seconds |
| Started | Sep 18 07:52:56 AM UTC 24 |
| Finished | Sep 18 07:53:03 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617732279 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1617732279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3138448137 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6242835586 ps |
| CPU time | 47.26 seconds |
| Started | Sep 18 07:52:53 AM UTC 24 |
| Finished | Sep 18 07:53:41 AM UTC 24 |
| Peak memory | 222220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138448137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.3138448137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4105728414 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 126819453 ps |
| CPU time | 7.23 seconds |
| Started | Sep 18 07:52:56 AM UTC 24 |
| Finished | Sep 18 07:53:04 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105728414 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.4105728414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3527197376 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 163214549 ps |
| CPU time | 10.37 seconds |
| Started | Sep 18 07:52:54 AM UTC 24 |
| Finished | Sep 18 07:53:05 AM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527197376 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3527197376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.147873782 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 375157094 ps |
| CPU time | 46.18 seconds |
| Started | Sep 18 07:52:55 AM UTC 24 |
| Finished | Sep 18 07:53:42 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147873782 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.147873782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1868139071 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 278646538 ps |
| CPU time | 8.79 seconds |
| Started | Sep 18 07:52:59 AM UTC 24 |
| Finished | Sep 18 07:53:09 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1868139071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rom_ctrl_csr_mem_rw_with_rand_reset.1868139071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1515596506 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 113628854 ps |
| CPU time | 6.32 seconds |
| Started | Sep 18 07:52:58 AM UTC 24 |
| Finished | Sep 18 07:53:06 AM UTC 24 |
| Peak memory | 228268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515596506 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1515596506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3446004105 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 8354192775 ps |
| CPU time | 31.35 seconds |
| Started | Sep 18 07:52:56 AM UTC 24 |
| Finished | Sep 18 07:53:29 AM UTC 24 |
| Peak memory | 222220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446004105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.3446004105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2604277986 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 567740031 ps |
| CPU time | 7.72 seconds |
| Started | Sep 18 07:52:58 AM UTC 24 |
| Finished | Sep 18 07:53:07 AM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604277986 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.2604277986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3917228368 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 89567367 ps |
| CPU time | 9.6 seconds |
| Started | Sep 18 07:52:57 AM UTC 24 |
| Finished | Sep 18 07:53:08 AM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917228368 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3917228368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4081003640 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 261910108 ps |
| CPU time | 75.37 seconds |
| Started | Sep 18 07:52:57 AM UTC 24 |
| Finished | Sep 18 07:54:14 AM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081003640 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.4081003640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2636263752 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 255233714 ps |
| CPU time | 6.68 seconds |
| Started | Sep 18 07:51:38 AM UTC 24 |
| Finished | Sep 18 07:51:46 AM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636263752 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.2636263752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2616823612 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 199450582 ps |
| CPU time | 7.55 seconds |
| Started | Sep 18 07:51:38 AM UTC 24 |
| Finished | Sep 18 07:51:47 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616823612 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.2616823612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3958510788 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 368528056 ps |
| CPU time | 6.32 seconds |
| Started | Sep 18 07:51:36 AM UTC 24 |
| Finished | Sep 18 07:51:43 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958510788 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.3958510788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.100832023 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 522055758 ps |
| CPU time | 8.08 seconds |
| Started | Sep 18 07:51:38 AM UTC 24 |
| Finished | Sep 18 07:51:47 AM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=100832023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.ro m_ctrl_csr_mem_rw_with_rand_reset.100832023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4006206661 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 86268149 ps |
| CPU time | 6.16 seconds |
| Started | Sep 18 07:51:37 AM UTC 24 |
| Finished | Sep 18 07:51:44 AM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006206661 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4006206661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2408021742 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1546863347 ps |
| CPU time | 7.36 seconds |
| Started | Sep 18 07:51:36 AM UTC 24 |
| Finished | Sep 18 07:51:44 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408021742 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.2408021742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1499210795 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 493335992 ps |
| CPU time | 9.86 seconds |
| Started | Sep 18 07:51:34 AM UTC 24 |
| Finished | Sep 18 07:51:45 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499210795 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.1499210795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.388906141 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2282171355 ps |
| CPU time | 30.57 seconds |
| Started | Sep 18 07:51:32 AM UTC 24 |
| Finished | Sep 18 07:52:03 AM UTC 24 |
| Peak memory | 222288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388906141 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.388906141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3360942110 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 757852235 ps |
| CPU time | 5.78 seconds |
| Started | Sep 18 07:51:38 AM UTC 24 |
| Finished | Sep 18 07:51:45 AM UTC 24 |
| Peak memory | 228976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360942110 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.3360942110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2099678085 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 89422370 ps |
| CPU time | 10.39 seconds |
| Started | Sep 18 07:51:33 AM UTC 24 |
| Finished | Sep 18 07:51:44 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099678085 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2099678085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2104567376 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 170399785 ps |
| CPU time | 6.29 seconds |
| Started | Sep 18 07:51:46 AM UTC 24 |
| Finished | Sep 18 07:51:53 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104567376 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.2104567376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3886817547 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 694693607 ps |
| CPU time | 7.69 seconds |
| Started | Sep 18 07:51:46 AM UTC 24 |
| Finished | Sep 18 07:51:54 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886817547 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.3886817547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2002477639 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 132964311 ps |
| CPU time | 9.37 seconds |
| Started | Sep 18 07:51:45 AM UTC 24 |
| Finished | Sep 18 07:51:55 AM UTC 24 |
| Peak memory | 229264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002477639 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.2002477639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3852369253 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 554392209 ps |
| CPU time | 5.56 seconds |
| Started | Sep 18 07:51:47 AM UTC 24 |
| Finished | Sep 18 07:51:53 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3852369253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r om_ctrl_csr_mem_rw_with_rand_reset.3852369253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4175832013 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 655898897 ps |
| CPU time | 7.09 seconds |
| Started | Sep 18 07:51:45 AM UTC 24 |
| Finished | Sep 18 07:51:53 AM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175832013 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4175832013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3604218561 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 127105942 ps |
| CPU time | 7.04 seconds |
| Started | Sep 18 07:51:44 AM UTC 24 |
| Finished | Sep 18 07:51:53 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604218561 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.3604218561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2400748077 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 322151644 ps |
| CPU time | 6.15 seconds |
| Started | Sep 18 07:51:42 AM UTC 24 |
| Finished | Sep 18 07:51:50 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400748077 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.2400748077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2174460898 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3574739467 ps |
| CPU time | 32.46 seconds |
| Started | Sep 18 07:51:39 AM UTC 24 |
| Finished | Sep 18 07:52:13 AM UTC 24 |
| Peak memory | 222164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174460898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.2174460898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.358010765 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 572472173 ps |
| CPU time | 9.88 seconds |
| Started | Sep 18 07:51:46 AM UTC 24 |
| Finished | Sep 18 07:51:57 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358010765 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.358010765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2438167456 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 578762817 ps |
| CPU time | 9.55 seconds |
| Started | Sep 18 07:51:39 AM UTC 24 |
| Finished | Sep 18 07:51:50 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438167456 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2438167456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3337331684 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 568804274 ps |
| CPU time | 90.4 seconds |
| Started | Sep 18 07:51:39 AM UTC 24 |
| Finished | Sep 18 07:53:12 AM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337331684 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.3337331684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3252993329 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 498152126 ps |
| CPU time | 10.22 seconds |
| Started | Sep 18 07:51:53 AM UTC 24 |
| Finished | Sep 18 07:52:05 AM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252993329 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.3252993329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3169955917 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 126396670 ps |
| CPU time | 6.96 seconds |
| Started | Sep 18 07:51:53 AM UTC 24 |
| Finished | Sep 18 07:52:01 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169955917 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.3169955917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1728748625 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 924746014 ps |
| CPU time | 11.81 seconds |
| Started | Sep 18 07:51:51 AM UTC 24 |
| Finished | Sep 18 07:52:04 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728748625 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.1728748625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3579266974 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 849752563 ps |
| CPU time | 6.09 seconds |
| Started | Sep 18 07:51:54 AM UTC 24 |
| Finished | Sep 18 07:52:01 AM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3579266974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r om_ctrl_csr_mem_rw_with_rand_reset.3579266974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2913110146 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 89900212 ps |
| CPU time | 6.43 seconds |
| Started | Sep 18 07:51:53 AM UTC 24 |
| Finished | Sep 18 07:52:01 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913110146 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2913110146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1338393790 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 86407762 ps |
| CPU time | 4.41 seconds |
| Started | Sep 18 07:51:51 AM UTC 24 |
| Finished | Sep 18 07:51:57 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338393790 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.1338393790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3791445625 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 249083573 ps |
| CPU time | 4.94 seconds |
| Started | Sep 18 07:51:51 AM UTC 24 |
| Finished | Sep 18 07:51:57 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791445625 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.3791445625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1255756007 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 363910396 ps |
| CPU time | 24.06 seconds |
| Started | Sep 18 07:51:48 AM UTC 24 |
| Finished | Sep 18 07:52:13 AM UTC 24 |
| Peak memory | 222164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255756007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1255756007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1484016368 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1669124135 ps |
| CPU time | 5.94 seconds |
| Started | Sep 18 07:51:54 AM UTC 24 |
| Finished | Sep 18 07:52:01 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484016368 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.1484016368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.607885329 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 702795552 ps |
| CPU time | 8.51 seconds |
| Started | Sep 18 07:51:48 AM UTC 24 |
| Finished | Sep 18 07:51:57 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607885329 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.607885329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2332121696 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 295209458 ps |
| CPU time | 99.24 seconds |
| Started | Sep 18 07:51:50 AM UTC 24 |
| Finished | Sep 18 07:53:31 AM UTC 24 |
| Peak memory | 224184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332121696 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.2332121696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3382848527 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 236533849 ps |
| CPU time | 7.95 seconds |
| Started | Sep 18 07:51:58 AM UTC 24 |
| Finished | Sep 18 07:52:07 AM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3382848527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r om_ctrl_csr_mem_rw_with_rand_reset.3382848527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1665204036 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2067386374 ps |
| CPU time | 4.75 seconds |
| Started | Sep 18 07:51:56 AM UTC 24 |
| Finished | Sep 18 07:52:01 AM UTC 24 |
| Peak memory | 222252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665204036 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1665204036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1398513053 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3139686286 ps |
| CPU time | 29.75 seconds |
| Started | Sep 18 07:51:56 AM UTC 24 |
| Finished | Sep 18 07:52:26 AM UTC 24 |
| Peak memory | 222228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398513053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.1398513053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3237008344 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 95983782 ps |
| CPU time | 6.4 seconds |
| Started | Sep 18 07:51:58 AM UTC 24 |
| Finished | Sep 18 07:52:05 AM UTC 24 |
| Peak memory | 222188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237008344 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.3237008344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1389888450 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 759987794 ps |
| CPU time | 9.02 seconds |
| Started | Sep 18 07:51:56 AM UTC 24 |
| Finished | Sep 18 07:52:06 AM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389888450 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1389888450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2446423259 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 700147993 ps |
| CPU time | 37.71 seconds |
| Started | Sep 18 07:51:56 AM UTC 24 |
| Finished | Sep 18 07:52:35 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446423259 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.2446423259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.454010978 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 588726327 ps |
| CPU time | 5.5 seconds |
| Started | Sep 18 07:52:02 AM UTC 24 |
| Finished | Sep 18 07:52:09 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=454010978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ro m_ctrl_csr_mem_rw_with_rand_reset.454010978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1845129005 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 127337188 ps |
| CPU time | 7.38 seconds |
| Started | Sep 18 07:52:02 AM UTC 24 |
| Finished | Sep 18 07:52:10 AM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845129005 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1845129005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.228026622 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 7145850412 ps |
| CPU time | 27.73 seconds |
| Started | Sep 18 07:51:58 AM UTC 24 |
| Finished | Sep 18 07:52:27 AM UTC 24 |
| Peak memory | 222160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228026622 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.228026622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4291602644 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1000283351 ps |
| CPU time | 11.69 seconds |
| Started | Sep 18 07:52:02 AM UTC 24 |
| Finished | Sep 18 07:52:15 AM UTC 24 |
| Peak memory | 222120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291602644 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.4291602644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.386259388 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 129697534 ps |
| CPU time | 9.82 seconds |
| Started | Sep 18 07:51:58 AM UTC 24 |
| Finished | Sep 18 07:52:09 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386259388 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.386259388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2348079168 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 836923805 ps |
| CPU time | 78.3 seconds |
| Started | Sep 18 07:52:01 AM UTC 24 |
| Finished | Sep 18 07:53:21 AM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348079168 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.2348079168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2693534578 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 291200314 ps |
| CPU time | 8.06 seconds |
| Started | Sep 18 07:52:07 AM UTC 24 |
| Finished | Sep 18 07:52:16 AM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2693534578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r om_ctrl_csr_mem_rw_with_rand_reset.2693534578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.162525377 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 262952969 ps |
| CPU time | 7.41 seconds |
| Started | Sep 18 07:52:05 AM UTC 24 |
| Finished | Sep 18 07:52:14 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162525377 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.162525377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3324751512 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 891611176 ps |
| CPU time | 45.49 seconds |
| Started | Sep 18 07:52:02 AM UTC 24 |
| Finished | Sep 18 07:52:49 AM UTC 24 |
| Peak memory | 222028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324751512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.3324751512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2056408070 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 955321879 ps |
| CPU time | 9.1 seconds |
| Started | Sep 18 07:52:05 AM UTC 24 |
| Finished | Sep 18 07:52:16 AM UTC 24 |
| Peak memory | 222188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056408070 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.2056408070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.938623930 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 263737004 ps |
| CPU time | 10 seconds |
| Started | Sep 18 07:52:04 AM UTC 24 |
| Finished | Sep 18 07:52:15 AM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938623930 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.938623930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4251948060 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 552613095 ps |
| CPU time | 39.67 seconds |
| Started | Sep 18 07:52:04 AM UTC 24 |
| Finished | Sep 18 07:52:45 AM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251948060 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.4251948060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3452513693 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 203255008 ps |
| CPU time | 7.76 seconds |
| Started | Sep 18 07:52:13 AM UTC 24 |
| Finished | Sep 18 07:52:22 AM UTC 24 |
| Peak memory | 229668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3452513693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r om_ctrl_csr_mem_rw_with_rand_reset.3452513693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.395133723 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 87446526 ps |
| CPU time | 6.47 seconds |
| Started | Sep 18 07:52:10 AM UTC 24 |
| Finished | Sep 18 07:52:17 AM UTC 24 |
| Peak memory | 228504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395133723 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.395133723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1096689377 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3280384192 ps |
| CPU time | 42.31 seconds |
| Started | Sep 18 07:52:07 AM UTC 24 |
| Finished | Sep 18 07:52:50 AM UTC 24 |
| Peak memory | 222292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096689377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1096689377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.113154124 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 89231675 ps |
| CPU time | 4.93 seconds |
| Started | Sep 18 07:52:11 AM UTC 24 |
| Finished | Sep 18 07:52:17 AM UTC 24 |
| Peak memory | 222136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113154124 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.113154124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1255190291 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 131852808 ps |
| CPU time | 8.79 seconds |
| Started | Sep 18 07:52:08 AM UTC 24 |
| Finished | Sep 18 07:52:17 AM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255190291 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1255190291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3994840879 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 139612814 ps |
| CPU time | 9.03 seconds |
| Started | Sep 18 07:52:16 AM UTC 24 |
| Finished | Sep 18 07:52:26 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3994840879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r om_ctrl_csr_mem_rw_with_rand_reset.3994840879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2932289267 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 517979622 ps |
| CPU time | 7.08 seconds |
| Started | Sep 18 07:52:16 AM UTC 24 |
| Finished | Sep 18 07:52:24 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932289267 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2932289267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1237748060 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2241392768 ps |
| CPU time | 29.63 seconds |
| Started | Sep 18 07:52:14 AM UTC 24 |
| Finished | Sep 18 07:52:45 AM UTC 24 |
| Peak memory | 222228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237748060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.1237748060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2443259914 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 314022805 ps |
| CPU time | 5.71 seconds |
| Started | Sep 18 07:52:16 AM UTC 24 |
| Finished | Sep 18 07:52:23 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443259914 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.2443259914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3224424637 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 962779370 ps |
| CPU time | 9.36 seconds |
| Started | Sep 18 07:52:14 AM UTC 24 |
| Finished | Sep 18 07:52:24 AM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224424637 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3224424637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2252158567 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 199961283 ps |
| CPU time | 43.6 seconds |
| Started | Sep 18 07:52:15 AM UTC 24 |
| Finished | Sep 18 07:53:00 AM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252158567 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.2252158567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1038102447 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 129829459 ps |
| CPU time | 6.7 seconds |
| Started | Sep 18 07:42:27 AM UTC 24 |
| Finished | Sep 18 07:42:35 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038102447 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1038102447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2023372852 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5545397447 ps |
| CPU time | 116.18 seconds |
| Started | Sep 18 07:42:16 AM UTC 24 |
| Finished | Sep 18 07:44:14 AM UTC 24 |
| Peak memory | 259800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023372852 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.2023372852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2614466781 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 256085400 ps |
| CPU time | 76.21 seconds |
| Started | Sep 18 07:42:27 AM UTC 24 |
| Finished | Sep 18 07:43:45 AM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614466781 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2614466781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3304626181 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 137135897 ps |
| CPU time | 9.73 seconds |
| Started | Sep 18 07:42:05 AM UTC 24 |
| Finished | Sep 18 07:42:15 AM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304626181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3304626181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1205827872 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 348494241 ps |
| CPU time | 6.05 seconds |
| Started | Sep 18 07:42:57 AM UTC 24 |
| Finished | Sep 18 07:43:04 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205827872 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1205827872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.978952662 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5225238035 ps |
| CPU time | 147.26 seconds |
| Started | Sep 18 07:42:35 AM UTC 24 |
| Finished | Sep 18 07:45:05 AM UTC 24 |
| Peak memory | 246580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978952662 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.978952662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.4004822455 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 334157237 ps |
| CPU time | 14.13 seconds |
| Started | Sep 18 07:42:39 AM UTC 24 |
| Finished | Sep 18 07:42:55 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004822455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4004822455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.280672633 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 191792526 ps |
| CPU time | 8.24 seconds |
| Started | Sep 18 07:42:35 AM UTC 24 |
| Finished | Sep 18 07:42:45 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280672633 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.280672633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.1878271718 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 93664648 ps |
| CPU time | 7.24 seconds |
| Started | Sep 18 07:42:30 AM UTC 24 |
| Finished | Sep 18 07:42:39 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878271718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1878271718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.4225769517 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 463574289 ps |
| CPU time | 11.66 seconds |
| Started | Sep 18 07:42:34 AM UTC 24 |
| Finished | Sep 18 07:42:47 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422576951 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.4225769517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1589178271 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9898692786 ps |
| CPU time | 314 seconds |
| Started | Sep 18 07:42:46 AM UTC 24 |
| Finished | Sep 18 07:48:04 AM UTC 24 |
| Peak memory | 235008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1589178271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1589178271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.754794693 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 87073094 ps |
| CPU time | 6.21 seconds |
| Started | Sep 18 07:46:11 AM UTC 24 |
| Finished | Sep 18 07:46:19 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754794693 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.754794693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.396501429 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 27979310805 ps |
| CPU time | 138.43 seconds |
| Started | Sep 18 07:46:07 AM UTC 24 |
| Finished | Sep 18 07:48:28 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396501429 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.396501429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2964214688 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 508409918 ps |
| CPU time | 16.17 seconds |
| Started | Sep 18 07:46:07 AM UTC 24 |
| Finished | Sep 18 07:46:24 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964214688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2964214688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2886026424 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3110948537 ps |
| CPU time | 9.7 seconds |
| Started | Sep 18 07:46:02 AM UTC 24 |
| Finished | Sep 18 07:46:13 AM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886026424 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2886026424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3778453043 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 201621439 ps |
| CPU time | 19.41 seconds |
| Started | Sep 18 07:46:01 AM UTC 24 |
| Finished | Sep 18 07:46:22 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377845304 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.3778453043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1052052150 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 10066353292 ps |
| CPU time | 228 seconds |
| Started | Sep 18 07:46:09 AM UTC 24 |
| Finished | Sep 18 07:50:01 AM UTC 24 |
| Peak memory | 247480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1052052150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1052052150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.22092562 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 348351717 ps |
| CPU time | 6.19 seconds |
| Started | Sep 18 07:46:20 AM UTC 24 |
| Finished | Sep 18 07:46:27 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22092562 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.22092562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1656334599 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 497925424 ps |
| CPU time | 16.46 seconds |
| Started | Sep 18 07:46:20 AM UTC 24 |
| Finished | Sep 18 07:46:38 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656334599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1656334599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3665832255 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 541212884 ps |
| CPU time | 8.97 seconds |
| Started | Sep 18 07:46:15 AM UTC 24 |
| Finished | Sep 18 07:46:25 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665832255 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3665832255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3002663707 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 309683024 ps |
| CPU time | 24.45 seconds |
| Started | Sep 18 07:46:13 AM UTC 24 |
| Finished | Sep 18 07:46:39 AM UTC 24 |
| Peak memory | 227732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300266370 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.3002663707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2416987677 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 11621601470 ps |
| CPU time | 168.78 seconds |
| Started | Sep 18 07:46:20 AM UTC 24 |
| Finished | Sep 18 07:49:11 AM UTC 24 |
| Peak memory | 247288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2416987677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2416987677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3991400041 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 250109647 ps |
| CPU time | 6.93 seconds |
| Started | Sep 18 07:46:30 AM UTC 24 |
| Finished | Sep 18 07:46:38 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991400041 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3991400041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2381311614 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 5290218164 ps |
| CPU time | 149.51 seconds |
| Started | Sep 18 07:46:25 AM UTC 24 |
| Finished | Sep 18 07:48:57 AM UTC 24 |
| Peak memory | 258884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381311614 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.2381311614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.323756837 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 387303030 ps |
| CPU time | 13.59 seconds |
| Started | Sep 18 07:46:28 AM UTC 24 |
| Finished | Sep 18 07:46:43 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323756837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.323756837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.896464900 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 231009119 ps |
| CPU time | 6.1 seconds |
| Started | Sep 18 07:46:25 AM UTC 24 |
| Finished | Sep 18 07:46:32 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896464900 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.896464900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3787741168 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 916071566 ps |
| CPU time | 14.71 seconds |
| Started | Sep 18 07:46:23 AM UTC 24 |
| Finished | Sep 18 07:46:39 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378774116 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.3787741168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4200369172 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8612191411 ps |
| CPU time | 103.49 seconds |
| Started | Sep 18 07:46:28 AM UTC 24 |
| Finished | Sep 18 07:48:14 AM UTC 24 |
| Peak memory | 235256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4200369172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.4200369172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3577687203 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 86378761 ps |
| CPU time | 6.03 seconds |
| Started | Sep 18 07:46:40 AM UTC 24 |
| Finished | Sep 18 07:46:47 AM UTC 24 |
| Peak memory | 223780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577687203 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3577687203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1959457921 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1715829899 ps |
| CPU time | 77.27 seconds |
| Started | Sep 18 07:46:38 AM UTC 24 |
| Finished | Sep 18 07:47:57 AM UTC 24 |
| Peak memory | 259608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959457921 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.1959457921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2178416540 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3124513104 ps |
| CPU time | 16.5 seconds |
| Started | Sep 18 07:46:38 AM UTC 24 |
| Finished | Sep 18 07:46:56 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178416540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2178416540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.850101129 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 462377617 ps |
| CPU time | 7.78 seconds |
| Started | Sep 18 07:46:36 AM UTC 24 |
| Finished | Sep 18 07:46:45 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850101129 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.850101129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3804162783 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 390338630 ps |
| CPU time | 23.68 seconds |
| Started | Sep 18 07:46:33 AM UTC 24 |
| Finished | Sep 18 07:46:58 AM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380416278 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.3804162783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3666247006 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4798454813 ps |
| CPU time | 35.13 seconds |
| Started | Sep 18 07:46:40 AM UTC 24 |
| Finished | Sep 18 07:47:16 AM UTC 24 |
| Peak memory | 233016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3666247006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3666247006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3258042614 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 378906500 ps |
| CPU time | 5.49 seconds |
| Started | Sep 18 07:46:53 AM UTC 24 |
| Finished | Sep 18 07:46:59 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258042614 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3258042614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2291683648 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1448736163 ps |
| CPU time | 74.88 seconds |
| Started | Sep 18 07:46:46 AM UTC 24 |
| Finished | Sep 18 07:48:02 AM UTC 24 |
| Peak memory | 259316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291683648 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.2291683648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2316155906 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 347912933 ps |
| CPU time | 12.72 seconds |
| Started | Sep 18 07:46:48 AM UTC 24 |
| Finished | Sep 18 07:47:02 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316155906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2316155906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.830186709 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2189383725 ps |
| CPU time | 6.96 seconds |
| Started | Sep 18 07:46:44 AM UTC 24 |
| Finished | Sep 18 07:46:52 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830186709 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.830186709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2074035777 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1100138538 ps |
| CPU time | 25.7 seconds |
| Started | Sep 18 07:46:43 AM UTC 24 |
| Finished | Sep 18 07:47:10 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207403577 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.2074035777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3911546077 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3236379645 ps |
| CPU time | 189.06 seconds |
| Started | Sep 18 07:46:48 AM UTC 24 |
| Finished | Sep 18 07:50:00 AM UTC 24 |
| Peak memory | 233144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3911546077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3911546077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2048833402 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 311763091 ps |
| CPU time | 6.06 seconds |
| Started | Sep 18 07:47:00 AM UTC 24 |
| Finished | Sep 18 07:47:07 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048833402 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2048833402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.844513460 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 996475821 ps |
| CPU time | 11.67 seconds |
| Started | Sep 18 07:47:00 AM UTC 24 |
| Finished | Sep 18 07:47:13 AM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844513460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.844513460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.2354504091 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 97084196 ps |
| CPU time | 8.63 seconds |
| Started | Sep 18 07:46:59 AM UTC 24 |
| Finished | Sep 18 07:47:09 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354504091 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2354504091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.1121950724 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 422141676 ps |
| CPU time | 18.1 seconds |
| Started | Sep 18 07:46:57 AM UTC 24 |
| Finished | Sep 18 07:47:16 AM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112195072 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.1121950724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3168995937 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1351091351 ps |
| CPU time | 65.77 seconds |
| Started | Sep 18 07:47:00 AM UTC 24 |
| Finished | Sep 18 07:48:08 AM UTC 24 |
| Peak memory | 232824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3168995937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3168995937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.70660511 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 131906296 ps |
| CPU time | 4.92 seconds |
| Started | Sep 18 07:47:11 AM UTC 24 |
| Finished | Sep 18 07:47:17 AM UTC 24 |
| Peak memory | 223784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70660511 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.70660511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.150515476 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1650371130 ps |
| CPU time | 141.71 seconds |
| Started | Sep 18 07:47:03 AM UTC 24 |
| Finished | Sep 18 07:49:28 AM UTC 24 |
| Peak memory | 259612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150515476 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.150515476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1600947669 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 177941327 ps |
| CPU time | 13.19 seconds |
| Started | Sep 18 07:47:09 AM UTC 24 |
| Finished | Sep 18 07:47:23 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600947669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1600947669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.349444941 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1400803310 ps |
| CPU time | 19.21 seconds |
| Started | Sep 18 07:47:02 AM UTC 24 |
| Finished | Sep 18 07:47:23 AM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349444941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.349444941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1540924933 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 10082143136 ps |
| CPU time | 189.6 seconds |
| Started | Sep 18 07:47:10 AM UTC 24 |
| Finished | Sep 18 07:50:22 AM UTC 24 |
| Peak memory | 235000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1540924933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1540924933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2612839931 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 556969016 ps |
| CPU time | 11.05 seconds |
| Started | Sep 18 07:47:17 AM UTC 24 |
| Finished | Sep 18 07:47:29 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612839931 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2612839931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1473118870 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 8050255680 ps |
| CPU time | 227.63 seconds |
| Started | Sep 18 07:47:16 AM UTC 24 |
| Finished | Sep 18 07:51:07 AM UTC 24 |
| Peak memory | 244612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473118870 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.1473118870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2051359879 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 220797333 ps |
| CPU time | 14.13 seconds |
| Started | Sep 18 07:47:17 AM UTC 24 |
| Finished | Sep 18 07:47:32 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051359879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2051359879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1257102915 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 98497896 ps |
| CPU time | 8.39 seconds |
| Started | Sep 18 07:47:14 AM UTC 24 |
| Finished | Sep 18 07:47:23 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257102915 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1257102915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2800755145 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 651999925 ps |
| CPU time | 11.39 seconds |
| Started | Sep 18 07:47:14 AM UTC 24 |
| Finished | Sep 18 07:47:26 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280075514 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.2800755145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2129027016 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 33040986738 ps |
| CPU time | 52.24 seconds |
| Started | Sep 18 07:47:17 AM UTC 24 |
| Finished | Sep 18 07:48:11 AM UTC 24 |
| Peak memory | 235000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2129027016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2129027016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3822354544 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 323686706 ps |
| CPU time | 6.17 seconds |
| Started | Sep 18 07:47:24 AM UTC 24 |
| Finished | Sep 18 07:47:32 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822354544 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3822354544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2394989160 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3352120696 ps |
| CPU time | 139.88 seconds |
| Started | Sep 18 07:47:23 AM UTC 24 |
| Finished | Sep 18 07:49:46 AM UTC 24 |
| Peak memory | 259764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394989160 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.2394989160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3682694439 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 250465442 ps |
| CPU time | 13.74 seconds |
| Started | Sep 18 07:47:23 AM UTC 24 |
| Finished | Sep 18 07:47:38 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682694439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3682694439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3715601628 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 98775190 ps |
| CPU time | 8.33 seconds |
| Started | Sep 18 07:47:21 AM UTC 24 |
| Finished | Sep 18 07:47:31 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715601628 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3715601628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3577258655 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1212580450 ps |
| CPU time | 12.52 seconds |
| Started | Sep 18 07:47:20 AM UTC 24 |
| Finished | Sep 18 07:47:34 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357725865 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.3577258655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2979446790 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 11621304592 ps |
| CPU time | 168.65 seconds |
| Started | Sep 18 07:47:24 AM UTC 24 |
| Finished | Sep 18 07:50:16 AM UTC 24 |
| Peak memory | 245496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2979446790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2979446790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3005964460 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 366449849 ps |
| CPU time | 7.18 seconds |
| Started | Sep 18 07:47:33 AM UTC 24 |
| Finished | Sep 18 07:47:41 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005964460 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3005964460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.186236814 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2427716683 ps |
| CPU time | 185.37 seconds |
| Started | Sep 18 07:47:30 AM UTC 24 |
| Finished | Sep 18 07:50:38 AM UTC 24 |
| Peak memory | 259740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186236814 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.186236814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1042793841 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 756512836 ps |
| CPU time | 14.29 seconds |
| Started | Sep 18 07:47:32 AM UTC 24 |
| Finished | Sep 18 07:47:47 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042793841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1042793841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.821891671 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 222697683 ps |
| CPU time | 5.55 seconds |
| Started | Sep 18 07:47:29 AM UTC 24 |
| Finished | Sep 18 07:47:35 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821891671 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.821891671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.4103755663 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 228349032 ps |
| CPU time | 21.15 seconds |
| Started | Sep 18 07:47:28 AM UTC 24 |
| Finished | Sep 18 07:47:50 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410375566 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.4103755663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2170383688 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 116250744 ps |
| CPU time | 7.99 seconds |
| Started | Sep 18 07:47:33 AM UTC 24 |
| Finished | Sep 18 07:47:42 AM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2170383688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2170383688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2849938256 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 169008444 ps |
| CPU time | 9.55 seconds |
| Started | Sep 18 07:43:25 AM UTC 24 |
| Finished | Sep 18 07:43:36 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849938256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2849938256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.715793024 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 419666932 ps |
| CPU time | 8.31 seconds |
| Started | Sep 18 07:43:16 AM UTC 24 |
| Finished | Sep 18 07:43:26 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715793024 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.715793024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3825364677 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 376673379 ps |
| CPU time | 150.91 seconds |
| Started | Sep 18 07:43:26 AM UTC 24 |
| Finished | Sep 18 07:46:00 AM UTC 24 |
| Peak memory | 256724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825364677 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3825364677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.362369916 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 138020181 ps |
| CPU time | 9.59 seconds |
| Started | Sep 18 07:43:05 AM UTC 24 |
| Finished | Sep 18 07:43:15 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362369916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.362369916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1840866302 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 695384363 ps |
| CPU time | 15.85 seconds |
| Started | Sep 18 07:43:07 AM UTC 24 |
| Finished | Sep 18 07:43:24 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184086630 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.1840866302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1558325170 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 85648658 ps |
| CPU time | 6.27 seconds |
| Started | Sep 18 07:47:42 AM UTC 24 |
| Finished | Sep 18 07:47:49 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558325170 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1558325170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.30603501 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 14399411710 ps |
| CPU time | 225.82 seconds |
| Started | Sep 18 07:47:39 AM UTC 24 |
| Finished | Sep 18 07:51:28 AM UTC 24 |
| Peak memory | 259728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30603501 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.30603501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.658093332 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 255581853 ps |
| CPU time | 15.98 seconds |
| Started | Sep 18 07:47:42 AM UTC 24 |
| Finished | Sep 18 07:47:59 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658093332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.658093332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2693979826 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 98078751 ps |
| CPU time | 7.8 seconds |
| Started | Sep 18 07:47:36 AM UTC 24 |
| Finished | Sep 18 07:47:45 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693979826 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2693979826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1930853744 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 226420666 ps |
| CPU time | 16.01 seconds |
| Started | Sep 18 07:47:35 AM UTC 24 |
| Finished | Sep 18 07:47:52 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193085374 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.1930853744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1383080639 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4054305758 ps |
| CPU time | 117 seconds |
| Started | Sep 18 07:47:42 AM UTC 24 |
| Finished | Sep 18 07:49:41 AM UTC 24 |
| Peak memory | 233144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1383080639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1383080639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.351289641 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 105166948 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 07:47:53 AM UTC 24 |
| Finished | Sep 18 07:47:59 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351289641 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.351289641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1952909552 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 8330832836 ps |
| CPU time | 83.74 seconds |
| Started | Sep 18 07:47:49 AM UTC 24 |
| Finished | Sep 18 07:49:15 AM UTC 24 |
| Peak memory | 247452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952909552 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.1952909552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1589451432 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 261573346 ps |
| CPU time | 14.76 seconds |
| Started | Sep 18 07:47:51 AM UTC 24 |
| Finished | Sep 18 07:48:07 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589451432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1589451432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3804549963 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 276776386 ps |
| CPU time | 9.03 seconds |
| Started | Sep 18 07:47:48 AM UTC 24 |
| Finished | Sep 18 07:47:58 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804549963 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3804549963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2241786741 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 425081130 ps |
| CPU time | 24.55 seconds |
| Started | Sep 18 07:47:45 AM UTC 24 |
| Finished | Sep 18 07:48:11 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224178674 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.2241786741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2287341741 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 7920591455 ps |
| CPU time | 145.17 seconds |
| Started | Sep 18 07:47:51 AM UTC 24 |
| Finished | Sep 18 07:50:19 AM UTC 24 |
| Peak memory | 232952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2287341741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2287341741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3982327504 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 333520497 ps |
| CPU time | 4.77 seconds |
| Started | Sep 18 07:48:03 AM UTC 24 |
| Finished | Sep 18 07:48:09 AM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982327504 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3982327504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1275393112 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 8387314422 ps |
| CPU time | 131.44 seconds |
| Started | Sep 18 07:48:00 AM UTC 24 |
| Finished | Sep 18 07:50:14 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275393112 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.1275393112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3684237864 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 262634606 ps |
| CPU time | 13.23 seconds |
| Started | Sep 18 07:48:00 AM UTC 24 |
| Finished | Sep 18 07:48:14 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684237864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3684237864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.998058923 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 96473243 ps |
| CPU time | 8.68 seconds |
| Started | Sep 18 07:47:59 AM UTC 24 |
| Finished | Sep 18 07:48:08 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998058923 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.998058923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2043946632 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 270723262 ps |
| CPU time | 9.57 seconds |
| Started | Sep 18 07:47:58 AM UTC 24 |
| Finished | Sep 18 07:48:08 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204394663 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.2043946632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2945302456 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 128185383 ps |
| CPU time | 5.3 seconds |
| Started | Sep 18 07:48:09 AM UTC 24 |
| Finished | Sep 18 07:48:16 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945302456 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2945302456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4269494841 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 6450975909 ps |
| CPU time | 123 seconds |
| Started | Sep 18 07:48:07 AM UTC 24 |
| Finished | Sep 18 07:50:12 AM UTC 24 |
| Peak memory | 259892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269494841 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.4269494841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1114223089 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 669401819 ps |
| CPU time | 14.49 seconds |
| Started | Sep 18 07:48:08 AM UTC 24 |
| Finished | Sep 18 07:48:24 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114223089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1114223089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3271216041 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 446881109 ps |
| CPU time | 8.04 seconds |
| Started | Sep 18 07:48:06 AM UTC 24 |
| Finished | Sep 18 07:48:15 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271216041 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3271216041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3494787563 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 437270349 ps |
| CPU time | 16.38 seconds |
| Started | Sep 18 07:48:05 AM UTC 24 |
| Finished | Sep 18 07:48:23 AM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349478756 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.3494787563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1946284836 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1104929191 ps |
| CPU time | 43.27 seconds |
| Started | Sep 18 07:48:08 AM UTC 24 |
| Finished | Sep 18 07:48:53 AM UTC 24 |
| Peak memory | 233016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1946284836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1946284836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1804977877 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 497954235 ps |
| CPU time | 5.81 seconds |
| Started | Sep 18 07:48:14 AM UTC 24 |
| Finished | Sep 18 07:48:21 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804977877 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1804977877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.745945618 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 11677122777 ps |
| CPU time | 141.57 seconds |
| Started | Sep 18 07:48:11 AM UTC 24 |
| Finished | Sep 18 07:50:35 AM UTC 24 |
| Peak memory | 225944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745945618 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.745945618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.4022973116 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1040194178 ps |
| CPU time | 16.37 seconds |
| Started | Sep 18 07:48:12 AM UTC 24 |
| Finished | Sep 18 07:48:29 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022973116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4022973116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1200517837 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 583119139 ps |
| CPU time | 7.14 seconds |
| Started | Sep 18 07:48:10 AM UTC 24 |
| Finished | Sep 18 07:48:18 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200517837 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1200517837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2227581238 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1669500846 ps |
| CPU time | 22.06 seconds |
| Started | Sep 18 07:48:09 AM UTC 24 |
| Finished | Sep 18 07:48:33 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222758123 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.2227581238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1967370409 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4229091488 ps |
| CPU time | 304.02 seconds |
| Started | Sep 18 07:48:12 AM UTC 24 |
| Finished | Sep 18 07:53:20 AM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1967370409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1967370409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2480238964 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 86849304 ps |
| CPU time | 4.85 seconds |
| Started | Sep 18 07:48:19 AM UTC 24 |
| Finished | Sep 18 07:48:25 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480238964 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2480238964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2238953575 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1753071007 ps |
| CPU time | 147.46 seconds |
| Started | Sep 18 07:48:16 AM UTC 24 |
| Finished | Sep 18 07:50:46 AM UTC 24 |
| Peak memory | 259836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238953575 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.2238953575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2459353551 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 618418660 ps |
| CPU time | 10.33 seconds |
| Started | Sep 18 07:48:17 AM UTC 24 |
| Finished | Sep 18 07:48:28 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459353551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2459353551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.4218443435 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 377726758 ps |
| CPU time | 5.96 seconds |
| Started | Sep 18 07:48:15 AM UTC 24 |
| Finished | Sep 18 07:48:22 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218443435 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4218443435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3319782800 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 119718102 ps |
| CPU time | 8.46 seconds |
| Started | Sep 18 07:48:15 AM UTC 24 |
| Finished | Sep 18 07:48:24 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331978280 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.3319782800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2221621428 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 131694878 ps |
| CPU time | 4.78 seconds |
| Started | Sep 18 07:48:26 AM UTC 24 |
| Finished | Sep 18 07:48:31 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221621428 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2221621428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2884349434 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2187769517 ps |
| CPU time | 111.34 seconds |
| Started | Sep 18 07:48:22 AM UTC 24 |
| Finished | Sep 18 07:50:16 AM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884349434 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.2884349434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1876450115 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 519116545 ps |
| CPU time | 13.91 seconds |
| Started | Sep 18 07:48:23 AM UTC 24 |
| Finished | Sep 18 07:48:38 AM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876450115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1876450115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3497052086 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 137239747 ps |
| CPU time | 8.6 seconds |
| Started | Sep 18 07:48:21 AM UTC 24 |
| Finished | Sep 18 07:48:31 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497052086 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3497052086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2422331167 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2012410283 ps |
| CPU time | 16.08 seconds |
| Started | Sep 18 07:48:20 AM UTC 24 |
| Finished | Sep 18 07:48:37 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242233116 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2422331167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1447035464 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 10976604396 ps |
| CPU time | 130.19 seconds |
| Started | Sep 18 07:48:24 AM UTC 24 |
| Finished | Sep 18 07:50:37 AM UTC 24 |
| Peak memory | 234996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1447035464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1447035464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.530570567 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 132162779 ps |
| CPU time | 7.29 seconds |
| Started | Sep 18 07:48:32 AM UTC 24 |
| Finished | Sep 18 07:48:40 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530570567 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.530570567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1594565197 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5462639691 ps |
| CPU time | 87.05 seconds |
| Started | Sep 18 07:48:29 AM UTC 24 |
| Finished | Sep 18 07:49:58 AM UTC 24 |
| Peak memory | 247120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594565197 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.1594565197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3927832400 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 712237674 ps |
| CPU time | 16.28 seconds |
| Started | Sep 18 07:48:30 AM UTC 24 |
| Finished | Sep 18 07:48:47 AM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927832400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3927832400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.755157710 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 516099304 ps |
| CPU time | 12.54 seconds |
| Started | Sep 18 07:48:29 AM UTC 24 |
| Finished | Sep 18 07:48:42 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755157710 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.755157710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.333975986 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 149792201 ps |
| CPU time | 8.67 seconds |
| Started | Sep 18 07:48:26 AM UTC 24 |
| Finished | Sep 18 07:48:35 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333975986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.333975986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4158340954 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 19392905740 ps |
| CPU time | 277.17 seconds |
| Started | Sep 18 07:48:32 AM UTC 24 |
| Finished | Sep 18 07:53:13 AM UTC 24 |
| Peak memory | 247240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4158340954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.rom_ctrl_stress_all_with_rand_reset.4158340954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.330466199 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 834617247 ps |
| CPU time | 6.12 seconds |
| Started | Sep 18 07:48:41 AM UTC 24 |
| Finished | Sep 18 07:48:49 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330466199 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.330466199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1031901617 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2501217664 ps |
| CPU time | 132.25 seconds |
| Started | Sep 18 07:48:37 AM UTC 24 |
| Finished | Sep 18 07:50:52 AM UTC 24 |
| Peak memory | 255060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031901617 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.1031901617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3280846948 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 977441202 ps |
| CPU time | 11.11 seconds |
| Started | Sep 18 07:48:38 AM UTC 24 |
| Finished | Sep 18 07:48:51 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280846948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3280846948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.823213489 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1498384858 ps |
| CPU time | 8.1 seconds |
| Started | Sep 18 07:48:36 AM UTC 24 |
| Finished | Sep 18 07:48:46 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823213489 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.823213489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1538583709 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 505315017 ps |
| CPU time | 13.73 seconds |
| Started | Sep 18 07:48:34 AM UTC 24 |
| Finished | Sep 18 07:48:49 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153858370 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.1538583709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1565108050 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3376456414 ps |
| CPU time | 134.28 seconds |
| Started | Sep 18 07:48:39 AM UTC 24 |
| Finished | Sep 18 07:50:56 AM UTC 24 |
| Peak memory | 234996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1565108050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1565108050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3841672026 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 272772926 ps |
| CPU time | 6.66 seconds |
| Started | Sep 18 07:48:51 AM UTC 24 |
| Finished | Sep 18 07:48:59 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841672026 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3841672026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3601048358 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3986236498 ps |
| CPU time | 90.51 seconds |
| Started | Sep 18 07:48:49 AM UTC 24 |
| Finished | Sep 18 07:50:21 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601048358 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.3601048358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1971382547 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 179112271 ps |
| CPU time | 11.96 seconds |
| Started | Sep 18 07:48:50 AM UTC 24 |
| Finished | Sep 18 07:49:03 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971382547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1971382547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3916723842 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 201287652 ps |
| CPU time | 8.24 seconds |
| Started | Sep 18 07:48:46 AM UTC 24 |
| Finished | Sep 18 07:48:56 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916723842 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3916723842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2664424523 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 319884265 ps |
| CPU time | 20.41 seconds |
| Started | Sep 18 07:48:43 AM UTC 24 |
| Finished | Sep 18 07:49:05 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266442452 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.2664424523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2930143005 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 16302977543 ps |
| CPU time | 177.57 seconds |
| Started | Sep 18 07:48:50 AM UTC 24 |
| Finished | Sep 18 07:51:50 AM UTC 24 |
| Peak memory | 247544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2930143005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2930143005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.3102439818 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 442887187 ps |
| CPU time | 7.14 seconds |
| Started | Sep 18 07:44:05 AM UTC 24 |
| Finished | Sep 18 07:44:13 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102439818 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3102439818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1896761743 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7893928910 ps |
| CPU time | 140.52 seconds |
| Started | Sep 18 07:43:56 AM UTC 24 |
| Finished | Sep 18 07:46:19 AM UTC 24 |
| Peak memory | 244488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896761743 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.1896761743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.4096002637 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 996067390 ps |
| CPU time | 16.32 seconds |
| Started | Sep 18 07:43:58 AM UTC 24 |
| Finished | Sep 18 07:44:15 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096002637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4096002637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1245022839 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 528071470 ps |
| CPU time | 8.73 seconds |
| Started | Sep 18 07:43:55 AM UTC 24 |
| Finished | Sep 18 07:44:04 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245022839 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1245022839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3809059204 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 643722360 ps |
| CPU time | 66.73 seconds |
| Started | Sep 18 07:44:04 AM UTC 24 |
| Finished | Sep 18 07:45:12 AM UTC 24 |
| Peak memory | 256728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809059204 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3809059204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3234282638 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 391297115 ps |
| CPU time | 8.08 seconds |
| Started | Sep 18 07:43:44 AM UTC 24 |
| Finished | Sep 18 07:43:54 AM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234282638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3234282638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1161252325 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 785551458 ps |
| CPU time | 16.94 seconds |
| Started | Sep 18 07:43:46 AM UTC 24 |
| Finished | Sep 18 07:44:04 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116125232 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.1161252325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1935913674 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12353550202 ps |
| CPU time | 132.92 seconds |
| Started | Sep 18 07:44:03 AM UTC 24 |
| Finished | Sep 18 07:46:18 AM UTC 24 |
| Peak memory | 235200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1935913674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1935913674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.3785944391 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 128302424 ps |
| CPU time | 7.12 seconds |
| Started | Sep 18 07:49:00 AM UTC 24 |
| Finished | Sep 18 07:49:08 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785944391 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3785944391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.726840157 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 29482659842 ps |
| CPU time | 147.35 seconds |
| Started | Sep 18 07:48:54 AM UTC 24 |
| Finished | Sep 18 07:51:24 AM UTC 24 |
| Peak memory | 254840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726840157 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.726840157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.281418888 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 670121261 ps |
| CPU time | 14.46 seconds |
| Started | Sep 18 07:48:57 AM UTC 24 |
| Finished | Sep 18 07:49:13 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281418888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.281418888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1980774513 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 293644577 ps |
| CPU time | 8.79 seconds |
| Started | Sep 18 07:48:53 AM UTC 24 |
| Finished | Sep 18 07:49:03 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980774513 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1980774513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2861213252 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 6863677294 ps |
| CPU time | 96.34 seconds |
| Started | Sep 18 07:48:58 AM UTC 24 |
| Finished | Sep 18 07:50:36 AM UTC 24 |
| Peak memory | 233144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2861213252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2861213252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1580744784 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 133324504 ps |
| CPU time | 7.06 seconds |
| Started | Sep 18 07:49:13 AM UTC 24 |
| Finished | Sep 18 07:49:21 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580744784 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1580744784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2984379495 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2223652711 ps |
| CPU time | 63.69 seconds |
| Started | Sep 18 07:49:03 AM UTC 24 |
| Finished | Sep 18 07:50:08 AM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984379495 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.2984379495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.353747886 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 254275217 ps |
| CPU time | 15.85 seconds |
| Started | Sep 18 07:49:05 AM UTC 24 |
| Finished | Sep 18 07:49:22 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353747886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.353747886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2721099871 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 338305562 ps |
| CPU time | 7.85 seconds |
| Started | Sep 18 07:49:03 AM UTC 24 |
| Finished | Sep 18 07:49:12 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721099871 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2721099871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2193468078 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3714661684 ps |
| CPU time | 30 seconds |
| Started | Sep 18 07:49:01 AM UTC 24 |
| Finished | Sep 18 07:49:32 AM UTC 24 |
| Peak memory | 227732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219346807 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.2193468078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1755137953 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 572272029 ps |
| CPU time | 7.18 seconds |
| Started | Sep 18 07:49:21 AM UTC 24 |
| Finished | Sep 18 07:49:29 AM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755137953 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1755137953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2151866801 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1691091872 ps |
| CPU time | 88.81 seconds |
| Started | Sep 18 07:49:14 AM UTC 24 |
| Finished | Sep 18 07:50:44 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151866801 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.2151866801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.4104430548 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 598111569 ps |
| CPU time | 13.69 seconds |
| Started | Sep 18 07:49:14 AM UTC 24 |
| Finished | Sep 18 07:49:28 AM UTC 24 |
| Peak memory | 223432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104430548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4104430548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2680816546 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 240728028 ps |
| CPU time | 8.15 seconds |
| Started | Sep 18 07:49:13 AM UTC 24 |
| Finished | Sep 18 07:49:22 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680816546 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2680816546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3054264748 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 284792828 ps |
| CPU time | 15.99 seconds |
| Started | Sep 18 07:49:13 AM UTC 24 |
| Finished | Sep 18 07:49:30 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305426474 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.3054264748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1089153601 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 22739778440 ps |
| CPU time | 205.13 seconds |
| Started | Sep 18 07:49:16 AM UTC 24 |
| Finished | Sep 18 07:52:44 AM UTC 24 |
| Peak memory | 237048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1089153601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1089153601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2348326112 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 220724554 ps |
| CPU time | 6.32 seconds |
| Started | Sep 18 07:49:29 AM UTC 24 |
| Finished | Sep 18 07:49:37 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348326112 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2348326112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2186779225 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10639407498 ps |
| CPU time | 148.81 seconds |
| Started | Sep 18 07:49:23 AM UTC 24 |
| Finished | Sep 18 07:51:54 AM UTC 24 |
| Peak memory | 258812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186779225 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.2186779225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1275439507 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 499857424 ps |
| CPU time | 16.19 seconds |
| Started | Sep 18 07:49:24 AM UTC 24 |
| Finished | Sep 18 07:49:42 AM UTC 24 |
| Peak memory | 223648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275439507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1275439507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.548327798 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 292911372 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 07:49:23 AM UTC 24 |
| Finished | Sep 18 07:49:33 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548327798 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.548327798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1481024141 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2707641543 ps |
| CPU time | 17.83 seconds |
| Started | Sep 18 07:49:23 AM UTC 24 |
| Finished | Sep 18 07:49:42 AM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148102414 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.1481024141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2546381760 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3753732590 ps |
| CPU time | 263.06 seconds |
| Started | Sep 18 07:49:28 AM UTC 24 |
| Finished | Sep 18 07:53:55 AM UTC 24 |
| Peak memory | 232952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2546381760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2546381760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.439003820 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 929747643 ps |
| CPU time | 5.96 seconds |
| Started | Sep 18 07:49:34 AM UTC 24 |
| Finished | Sep 18 07:49:41 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439003820 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.439003820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2234591553 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 9707245197 ps |
| CPU time | 109.27 seconds |
| Started | Sep 18 07:49:30 AM UTC 24 |
| Finished | Sep 18 07:51:22 AM UTC 24 |
| Peak memory | 259740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234591553 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.2234591553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2888846149 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 347901139 ps |
| CPU time | 10.56 seconds |
| Started | Sep 18 07:49:34 AM UTC 24 |
| Finished | Sep 18 07:49:45 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888846149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2888846149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.657539554 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1542532545 ps |
| CPU time | 6.59 seconds |
| Started | Sep 18 07:49:30 AM UTC 24 |
| Finished | Sep 18 07:49:38 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657539554 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.657539554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3427589005 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 765117284 ps |
| CPU time | 14.57 seconds |
| Started | Sep 18 07:49:30 AM UTC 24 |
| Finished | Sep 18 07:49:46 AM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342758900 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.3427589005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3215045526 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3466166282 ps |
| CPU time | 223.76 seconds |
| Started | Sep 18 07:49:34 AM UTC 24 |
| Finished | Sep 18 07:53:20 AM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3215045526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3215045526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3601380644 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 620728421 ps |
| CPU time | 7.16 seconds |
| Started | Sep 18 07:49:43 AM UTC 24 |
| Finished | Sep 18 07:49:51 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601380644 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3601380644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2396645671 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5190455090 ps |
| CPU time | 157.43 seconds |
| Started | Sep 18 07:49:41 AM UTC 24 |
| Finished | Sep 18 07:52:21 AM UTC 24 |
| Peak memory | 244564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396645671 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.2396645671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1304608916 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 520823004 ps |
| CPU time | 16.81 seconds |
| Started | Sep 18 07:49:42 AM UTC 24 |
| Finished | Sep 18 07:50:00 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304608916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1304608916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3721741853 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 98215136 ps |
| CPU time | 7.92 seconds |
| Started | Sep 18 07:49:39 AM UTC 24 |
| Finished | Sep 18 07:49:48 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721741853 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3721741853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.577592715 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1578605347 ps |
| CPU time | 14.66 seconds |
| Started | Sep 18 07:49:38 AM UTC 24 |
| Finished | Sep 18 07:49:53 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577592715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.577592715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2358043120 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3229691267 ps |
| CPU time | 57.78 seconds |
| Started | Sep 18 07:49:42 AM UTC 24 |
| Finished | Sep 18 07:50:41 AM UTC 24 |
| Peak memory | 232952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2358043120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2358043120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1513488494 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 541207457 ps |
| CPU time | 5.56 seconds |
| Started | Sep 18 07:49:52 AM UTC 24 |
| Finished | Sep 18 07:49:59 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513488494 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1513488494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3723404207 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1617086978 ps |
| CPU time | 108.76 seconds |
| Started | Sep 18 07:49:47 AM UTC 24 |
| Finished | Sep 18 07:51:38 AM UTC 24 |
| Peak memory | 259720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723404207 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.3723404207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3106518292 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 261878197 ps |
| CPU time | 13.01 seconds |
| Started | Sep 18 07:49:48 AM UTC 24 |
| Finished | Sep 18 07:50:02 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106518292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3106518292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3582686687 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 306453326 ps |
| CPU time | 9.75 seconds |
| Started | Sep 18 07:49:46 AM UTC 24 |
| Finished | Sep 18 07:49:57 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582686687 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3582686687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1291402009 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1048272452 ps |
| CPU time | 10 seconds |
| Started | Sep 18 07:49:46 AM UTC 24 |
| Finished | Sep 18 07:49:57 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129140200 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.1291402009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2576414214 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1319726535 ps |
| CPU time | 46.42 seconds |
| Started | Sep 18 07:49:49 AM UTC 24 |
| Finished | Sep 18 07:50:37 AM UTC 24 |
| Peak memory | 230776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2576414214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2576414214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3451007630 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 88244440 ps |
| CPU time | 4.9 seconds |
| Started | Sep 18 07:50:01 AM UTC 24 |
| Finished | Sep 18 07:50:07 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451007630 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3451007630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2451266693 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2753553160 ps |
| CPU time | 166.89 seconds |
| Started | Sep 18 07:49:58 AM UTC 24 |
| Finished | Sep 18 07:52:47 AM UTC 24 |
| Peak memory | 259828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451266693 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.2451266693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1781190400 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1187052524 ps |
| CPU time | 16.13 seconds |
| Started | Sep 18 07:49:59 AM UTC 24 |
| Finished | Sep 18 07:50:16 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781190400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1781190400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.304372369 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 552018657 ps |
| CPU time | 8.77 seconds |
| Started | Sep 18 07:49:58 AM UTC 24 |
| Finished | Sep 18 07:50:07 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304372369 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.304372369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3032360842 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 709324046 ps |
| CPU time | 18.41 seconds |
| Started | Sep 18 07:49:55 AM UTC 24 |
| Finished | Sep 18 07:50:14 AM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303236084 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.3032360842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3013102710 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 18802591086 ps |
| CPU time | 83.55 seconds |
| Started | Sep 18 07:50:00 AM UTC 24 |
| Finished | Sep 18 07:51:25 AM UTC 24 |
| Peak memory | 235064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3013102710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3013102710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1213753669 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 518075356 ps |
| CPU time | 5.38 seconds |
| Started | Sep 18 07:50:08 AM UTC 24 |
| Finished | Sep 18 07:50:15 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213753669 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1213753669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2969607880 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 8587853456 ps |
| CPU time | 170.86 seconds |
| Started | Sep 18 07:50:03 AM UTC 24 |
| Finished | Sep 18 07:52:57 AM UTC 24 |
| Peak memory | 259720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969607880 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.2969607880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2823242423 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1032123998 ps |
| CPU time | 10.16 seconds |
| Started | Sep 18 07:50:04 AM UTC 24 |
| Finished | Sep 18 07:50:15 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823242423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2823242423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1201922759 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 103022291 ps |
| CPU time | 8.67 seconds |
| Started | Sep 18 07:50:02 AM UTC 24 |
| Finished | Sep 18 07:50:12 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201922759 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1201922759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3489742607 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 599552766 ps |
| CPU time | 9.95 seconds |
| Started | Sep 18 07:50:01 AM UTC 24 |
| Finished | Sep 18 07:50:12 AM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348974260 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.3489742607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1756989947 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 7919976048 ps |
| CPU time | 237.07 seconds |
| Started | Sep 18 07:50:07 AM UTC 24 |
| Finished | Sep 18 07:54:08 AM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1756989947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1756989947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2358058995 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 517172568 ps |
| CPU time | 5.19 seconds |
| Started | Sep 18 07:50:15 AM UTC 24 |
| Finished | Sep 18 07:50:21 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358058995 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2358058995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1155071459 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2824211187 ps |
| CPU time | 127.11 seconds |
| Started | Sep 18 07:50:12 AM UTC 24 |
| Finished | Sep 18 07:52:22 AM UTC 24 |
| Peak memory | 259740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155071459 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.1155071459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2907508052 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1661910805 ps |
| CPU time | 23.36 seconds |
| Started | Sep 18 07:50:12 AM UTC 24 |
| Finished | Sep 18 07:50:37 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907508052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2907508052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3989876678 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 193037180 ps |
| CPU time | 6.73 seconds |
| Started | Sep 18 07:50:09 AM UTC 24 |
| Finished | Sep 18 07:50:17 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989876678 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3989876678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1878027287 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 209006213 ps |
| CPU time | 13.47 seconds |
| Started | Sep 18 07:50:08 AM UTC 24 |
| Finished | Sep 18 07:50:23 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187802728 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.1878027287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3287891890 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1934111234 ps |
| CPU time | 41.99 seconds |
| Started | Sep 18 07:50:14 AM UTC 24 |
| Finished | Sep 18 07:50:57 AM UTC 24 |
| Peak memory | 232824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3287891890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3287891890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1752617249 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 133731024 ps |
| CPU time | 7.01 seconds |
| Started | Sep 18 07:44:26 AM UTC 24 |
| Finished | Sep 18 07:44:34 AM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752617249 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1752617249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.877181630 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8718035050 ps |
| CPU time | 128.84 seconds |
| Started | Sep 18 07:44:16 AM UTC 24 |
| Finished | Sep 18 07:46:28 AM UTC 24 |
| Peak memory | 259816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877181630 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.877181630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4115561042 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 173413791 ps |
| CPU time | 9.59 seconds |
| Started | Sep 18 07:44:23 AM UTC 24 |
| Finished | Sep 18 07:44:34 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115561042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4115561042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3807630928 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 139100040 ps |
| CPU time | 9.22 seconds |
| Started | Sep 18 07:44:15 AM UTC 24 |
| Finished | Sep 18 07:44:25 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807630928 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3807630928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.114286068 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 869510732 ps |
| CPU time | 112.32 seconds |
| Started | Sep 18 07:44:24 AM UTC 24 |
| Finished | Sep 18 07:46:19 AM UTC 24 |
| Peak memory | 258616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114286068 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.114286068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.2587829760 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 95360169 ps |
| CPU time | 7.28 seconds |
| Started | Sep 18 07:44:14 AM UTC 24 |
| Finished | Sep 18 07:44:22 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587829760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2587829760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.964008146 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1041444352 ps |
| CPU time | 26.97 seconds |
| Started | Sep 18 07:44:15 AM UTC 24 |
| Finished | Sep 18 07:44:43 AM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964008146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.964008146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.569109128 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 4231174899 ps |
| CPU time | 333.59 seconds |
| Started | Sep 18 07:44:24 AM UTC 24 |
| Finished | Sep 18 07:50:03 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=569109128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.rom_ctrl_stress_all_with_rand_reset.569109128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1841543276 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 498337893 ps |
| CPU time | 7.33 seconds |
| Started | Sep 18 07:50:17 AM UTC 24 |
| Finished | Sep 18 07:50:25 AM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841543276 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1841543276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4139860250 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4692601220 ps |
| CPU time | 129.46 seconds |
| Started | Sep 18 07:50:16 AM UTC 24 |
| Finished | Sep 18 07:52:27 AM UTC 24 |
| Peak memory | 244520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139860250 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.4139860250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.3099981681 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1036287161 ps |
| CPU time | 11.7 seconds |
| Started | Sep 18 07:50:17 AM UTC 24 |
| Finished | Sep 18 07:50:30 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099981681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3099981681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2620796037 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 97504366 ps |
| CPU time | 5.37 seconds |
| Started | Sep 18 07:50:16 AM UTC 24 |
| Finished | Sep 18 07:50:22 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620796037 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2620796037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3241859974 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 370450134 ps |
| CPU time | 18.16 seconds |
| Started | Sep 18 07:50:15 AM UTC 24 |
| Finished | Sep 18 07:50:34 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324185997 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.3241859974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1278951454 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4194666905 ps |
| CPU time | 91.88 seconds |
| Started | Sep 18 07:50:17 AM UTC 24 |
| Finished | Sep 18 07:51:51 AM UTC 24 |
| Peak memory | 243192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1278951454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1278951454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3886570106 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 438323590 ps |
| CPU time | 5.16 seconds |
| Started | Sep 18 07:50:23 AM UTC 24 |
| Finished | Sep 18 07:50:29 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886570106 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3886570106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1653933683 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 7338670831 ps |
| CPU time | 62.74 seconds |
| Started | Sep 18 07:50:21 AM UTC 24 |
| Finished | Sep 18 07:51:25 AM UTC 24 |
| Peak memory | 247068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653933683 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.1653933683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1013580599 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 173891785 ps |
| CPU time | 9.8 seconds |
| Started | Sep 18 07:50:22 AM UTC 24 |
| Finished | Sep 18 07:50:33 AM UTC 24 |
| Peak memory | 223840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013580599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1013580599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1508283172 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 99685015 ps |
| CPU time | 7.17 seconds |
| Started | Sep 18 07:50:19 AM UTC 24 |
| Finished | Sep 18 07:50:27 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508283172 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1508283172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3177029636 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1206192734 ps |
| CPU time | 22.6 seconds |
| Started | Sep 18 07:50:18 AM UTC 24 |
| Finished | Sep 18 07:50:42 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317702963 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.3177029636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3542318841 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5227321982 ps |
| CPU time | 88.99 seconds |
| Started | Sep 18 07:50:23 AM UTC 24 |
| Finished | Sep 18 07:51:54 AM UTC 24 |
| Peak memory | 235000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3542318841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3542318841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.52852212 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 132323599 ps |
| CPU time | 5.11 seconds |
| Started | Sep 18 07:50:34 AM UTC 24 |
| Finished | Sep 18 07:50:40 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52852212 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.52852212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3898411504 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 13980482151 ps |
| CPU time | 178.12 seconds |
| Started | Sep 18 07:50:29 AM UTC 24 |
| Finished | Sep 18 07:53:29 AM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898411504 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.3898411504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3500822073 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 172312215 ps |
| CPU time | 12.52 seconds |
| Started | Sep 18 07:50:31 AM UTC 24 |
| Finished | Sep 18 07:50:44 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500822073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3500822073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1924639095 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 135888891 ps |
| CPU time | 9.05 seconds |
| Started | Sep 18 07:50:26 AM UTC 24 |
| Finished | Sep 18 07:50:36 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924639095 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1924639095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.566465187 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 742298203 ps |
| CPU time | 11.55 seconds |
| Started | Sep 18 07:50:23 AM UTC 24 |
| Finished | Sep 18 07:50:36 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566465187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.566465187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.493410515 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1148815721 ps |
| CPU time | 44.22 seconds |
| Started | Sep 18 07:50:31 AM UTC 24 |
| Finished | Sep 18 07:51:16 AM UTC 24 |
| Peak memory | 230780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=493410515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 42.rom_ctrl_stress_all_with_rand_reset.493410515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1014795751 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 234426183 ps |
| CPU time | 6.21 seconds |
| Started | Sep 18 07:50:38 AM UTC 24 |
| Finished | Sep 18 07:50:45 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014795751 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1014795751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1898719139 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3013872237 ps |
| CPU time | 167 seconds |
| Started | Sep 18 07:50:37 AM UTC 24 |
| Finished | Sep 18 07:53:27 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898719139 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.1898719139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3682238821 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1390927187 ps |
| CPU time | 14.12 seconds |
| Started | Sep 18 07:50:37 AM UTC 24 |
| Finished | Sep 18 07:50:52 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682238821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3682238821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1005716068 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 521281237 ps |
| CPU time | 9.07 seconds |
| Started | Sep 18 07:50:36 AM UTC 24 |
| Finished | Sep 18 07:50:46 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005716068 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1005716068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.489908459 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 584282117 ps |
| CPU time | 25.09 seconds |
| Started | Sep 18 07:50:35 AM UTC 24 |
| Finished | Sep 18 07:51:01 AM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489908459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.489908459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.72483311 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 15911851347 ps |
| CPU time | 162.88 seconds |
| Started | Sep 18 07:50:37 AM UTC 24 |
| Finished | Sep 18 07:53:22 AM UTC 24 |
| Peak memory | 234992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=72483311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.72483311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1468492179 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 428235247 ps |
| CPU time | 6.81 seconds |
| Started | Sep 18 07:50:42 AM UTC 24 |
| Finished | Sep 18 07:50:51 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468492179 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1468492179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3115862538 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 35486187741 ps |
| CPU time | 178.4 seconds |
| Started | Sep 18 07:50:39 AM UTC 24 |
| Finished | Sep 18 07:53:40 AM UTC 24 |
| Peak memory | 259812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115862538 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.3115862538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1499358054 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 168832474 ps |
| CPU time | 11.19 seconds |
| Started | Sep 18 07:50:40 AM UTC 24 |
| Finished | Sep 18 07:50:53 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499358054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1499358054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.601634762 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 433165193 ps |
| CPU time | 7.82 seconds |
| Started | Sep 18 07:50:38 AM UTC 24 |
| Finished | Sep 18 07:50:47 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601634762 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.601634762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1580185399 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1349689902 ps |
| CPU time | 30.35 seconds |
| Started | Sep 18 07:50:38 AM UTC 24 |
| Finished | Sep 18 07:51:10 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158018539 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.1580185399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.969291843 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5635429660 ps |
| CPU time | 165.92 seconds |
| Started | Sep 18 07:50:42 AM UTC 24 |
| Finished | Sep 18 07:53:31 AM UTC 24 |
| Peak memory | 235004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=969291843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 44.rom_ctrl_stress_all_with_rand_reset.969291843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3041994125 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 490486928 ps |
| CPU time | 6.11 seconds |
| Started | Sep 18 07:50:47 AM UTC 24 |
| Finished | Sep 18 07:50:54 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041994125 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3041994125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1385890238 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 18696523110 ps |
| CPU time | 154.31 seconds |
| Started | Sep 18 07:50:46 AM UTC 24 |
| Finished | Sep 18 07:53:22 AM UTC 24 |
| Peak memory | 247368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385890238 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.1385890238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1166264735 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 874650790 ps |
| CPU time | 10.44 seconds |
| Started | Sep 18 07:50:47 AM UTC 24 |
| Finished | Sep 18 07:50:58 AM UTC 24 |
| Peak memory | 223648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166264735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1166264735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3123079619 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 276950029 ps |
| CPU time | 8.83 seconds |
| Started | Sep 18 07:50:46 AM UTC 24 |
| Finished | Sep 18 07:50:56 AM UTC 24 |
| Peak memory | 223768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123079619 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3123079619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.490088910 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 838874457 ps |
| CPU time | 22.41 seconds |
| Started | Sep 18 07:50:46 AM UTC 24 |
| Finished | Sep 18 07:51:09 AM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490088910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.490088910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.202215116 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1288815501 ps |
| CPU time | 23.93 seconds |
| Started | Sep 18 07:50:47 AM UTC 24 |
| Finished | Sep 18 07:51:12 AM UTC 24 |
| Peak memory | 230780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=202215116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 45.rom_ctrl_stress_all_with_rand_reset.202215116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1615223891 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 259920533 ps |
| CPU time | 7.16 seconds |
| Started | Sep 18 07:50:53 AM UTC 24 |
| Finished | Sep 18 07:51:01 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615223891 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1615223891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2209536994 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2443288530 ps |
| CPU time | 111.54 seconds |
| Started | Sep 18 07:50:52 AM UTC 24 |
| Finished | Sep 18 07:52:46 AM UTC 24 |
| Peak memory | 259584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209536994 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.2209536994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.525308514 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 175980461 ps |
| CPU time | 10.22 seconds |
| Started | Sep 18 07:50:53 AM UTC 24 |
| Finished | Sep 18 07:51:05 AM UTC 24 |
| Peak memory | 223836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525308514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.525308514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3764134640 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 98109239 ps |
| CPU time | 8.28 seconds |
| Started | Sep 18 07:50:48 AM UTC 24 |
| Finished | Sep 18 07:50:58 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764134640 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3764134640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3720585299 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 521572573 ps |
| CPU time | 8.65 seconds |
| Started | Sep 18 07:50:48 AM UTC 24 |
| Finished | Sep 18 07:50:58 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372058529 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.3720585299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4086222934 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 18400526959 ps |
| CPU time | 157.69 seconds |
| Started | Sep 18 07:50:53 AM UTC 24 |
| Finished | Sep 18 07:53:33 AM UTC 24 |
| Peak memory | 243192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4086222934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4086222934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3154476251 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 516740226 ps |
| CPU time | 7.09 seconds |
| Started | Sep 18 07:50:59 AM UTC 24 |
| Finished | Sep 18 07:51:07 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154476251 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3154476251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.959628700 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 8044336293 ps |
| CPU time | 111.67 seconds |
| Started | Sep 18 07:50:57 AM UTC 24 |
| Finished | Sep 18 07:52:51 AM UTC 24 |
| Peak memory | 259740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959628700 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.959628700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3323173380 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1666557500 ps |
| CPU time | 10.17 seconds |
| Started | Sep 18 07:50:57 AM UTC 24 |
| Finished | Sep 18 07:51:09 AM UTC 24 |
| Peak memory | 223648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323173380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3323173380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1803773093 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 603806865 ps |
| CPU time | 5.7 seconds |
| Started | Sep 18 07:50:56 AM UTC 24 |
| Finished | Sep 18 07:51:03 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803773093 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1803773093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3652725679 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 299436411 ps |
| CPU time | 24.42 seconds |
| Started | Sep 18 07:50:54 AM UTC 24 |
| Finished | Sep 18 07:51:20 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365272567 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.3652725679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.291743344 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 9317438750 ps |
| CPU time | 285.35 seconds |
| Started | Sep 18 07:50:58 AM UTC 24 |
| Finished | Sep 18 07:55:48 AM UTC 24 |
| Peak memory | 235004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=291743344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 47.rom_ctrl_stress_all_with_rand_reset.291743344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3043451470 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 333913413 ps |
| CPU time | 6.09 seconds |
| Started | Sep 18 07:51:06 AM UTC 24 |
| Finished | Sep 18 07:51:13 AM UTC 24 |
| Peak memory | 223780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043451470 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3043451470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1998074214 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3782698970 ps |
| CPU time | 81.76 seconds |
| Started | Sep 18 07:51:03 AM UTC 24 |
| Finished | Sep 18 07:52:26 AM UTC 24 |
| Peak memory | 246444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998074214 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.1998074214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1960161399 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 996895817 ps |
| CPU time | 16.86 seconds |
| Started | Sep 18 07:51:04 AM UTC 24 |
| Finished | Sep 18 07:51:22 AM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960161399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1960161399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1637701778 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 167640499 ps |
| CPU time | 9.13 seconds |
| Started | Sep 18 07:51:02 AM UTC 24 |
| Finished | Sep 18 07:51:12 AM UTC 24 |
| Peak memory | 223768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637701778 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1637701778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1146348940 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 219049388 ps |
| CPU time | 14.02 seconds |
| Started | Sep 18 07:51:00 AM UTC 24 |
| Finished | Sep 18 07:51:15 AM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114634894 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.1146348940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1088900813 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 19685438327 ps |
| CPU time | 308.3 seconds |
| Started | Sep 18 07:51:05 AM UTC 24 |
| Finished | Sep 18 07:56:17 AM UTC 24 |
| Peak memory | 245240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1088900813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1088900813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.765284028 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 127719885 ps |
| CPU time | 6.96 seconds |
| Started | Sep 18 07:51:12 AM UTC 24 |
| Finished | Sep 18 07:51:20 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765284028 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.765284028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1265793941 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 911878774 ps |
| CPU time | 64.43 seconds |
| Started | Sep 18 07:51:09 AM UTC 24 |
| Finished | Sep 18 07:52:15 AM UTC 24 |
| Peak memory | 259144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265793941 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.1265793941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.4250261840 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1104348408 ps |
| CPU time | 11.01 seconds |
| Started | Sep 18 07:51:10 AM UTC 24 |
| Finished | Sep 18 07:51:22 AM UTC 24 |
| Peak memory | 223756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250261840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4250261840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2660714598 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1282187649 ps |
| CPU time | 8.05 seconds |
| Started | Sep 18 07:51:08 AM UTC 24 |
| Finished | Sep 18 07:51:18 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660714598 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2660714598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.981407034 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1133820358 ps |
| CPU time | 22.81 seconds |
| Started | Sep 18 07:51:08 AM UTC 24 |
| Finished | Sep 18 07:51:32 AM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981407034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.981407034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2908104364 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4236811656 ps |
| CPU time | 142.94 seconds |
| Started | Sep 18 07:51:10 AM UTC 24 |
| Finished | Sep 18 07:53:36 AM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2908104364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2908104364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3257499131 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 521496214 ps |
| CPU time | 7.17 seconds |
| Started | Sep 18 07:44:45 AM UTC 24 |
| Finished | Sep 18 07:44:53 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257499131 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3257499131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2549259531 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 8119910584 ps |
| CPU time | 128.95 seconds |
| Started | Sep 18 07:44:36 AM UTC 24 |
| Finished | Sep 18 07:46:47 AM UTC 24 |
| Peak memory | 254996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549259531 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.2549259531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1843843409 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 398352311 ps |
| CPU time | 8.46 seconds |
| Started | Sep 18 07:44:35 AM UTC 24 |
| Finished | Sep 18 07:44:44 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843843409 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1843843409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3468103732 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 102994014 ps |
| CPU time | 8.26 seconds |
| Started | Sep 18 07:44:30 AM UTC 24 |
| Finished | Sep 18 07:44:39 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468103732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3468103732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.959428917 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 408497194 ps |
| CPU time | 14.57 seconds |
| Started | Sep 18 07:44:34 AM UTC 24 |
| Finished | Sep 18 07:44:49 AM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959428917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.959428917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3910246897 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 171786507 ps |
| CPU time | 6.11 seconds |
| Started | Sep 18 07:45:05 AM UTC 24 |
| Finished | Sep 18 07:45:13 AM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910246897 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3910246897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3134537180 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 10169841649 ps |
| CPU time | 121.39 seconds |
| Started | Sep 18 07:44:59 AM UTC 24 |
| Finished | Sep 18 07:47:03 AM UTC 24 |
| Peak memory | 259884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134537180 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.3134537180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3556133677 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 178518000 ps |
| CPU time | 14.23 seconds |
| Started | Sep 18 07:45:03 AM UTC 24 |
| Finished | Sep 18 07:45:19 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556133677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3556133677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.150151756 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 272640989 ps |
| CPU time | 5.98 seconds |
| Started | Sep 18 07:44:57 AM UTC 24 |
| Finished | Sep 18 07:45:04 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150151756 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.150151756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.558385354 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 94840623 ps |
| CPU time | 7.75 seconds |
| Started | Sep 18 07:44:50 AM UTC 24 |
| Finished | Sep 18 07:44:59 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558385354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.558385354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3206308520 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1287379849 ps |
| CPU time | 24.16 seconds |
| Started | Sep 18 07:44:54 AM UTC 24 |
| Finished | Sep 18 07:45:19 AM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320630852 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.3206308520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.698453766 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3291809814 ps |
| CPU time | 220.72 seconds |
| Started | Sep 18 07:45:05 AM UTC 24 |
| Finished | Sep 18 07:48:50 AM UTC 24 |
| Peak memory | 235008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=698453766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 6.rom_ctrl_stress_all_with_rand_reset.698453766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2557243835 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 132218288 ps |
| CPU time | 7.23 seconds |
| Started | Sep 18 07:45:26 AM UTC 24 |
| Finished | Sep 18 07:45:34 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557243835 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2557243835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4197553387 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 9031338226 ps |
| CPU time | 177.04 seconds |
| Started | Sep 18 07:45:20 AM UTC 24 |
| Finished | Sep 18 07:48:20 AM UTC 24 |
| Peak memory | 259748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197553387 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.4197553387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1879212327 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 256994055 ps |
| CPU time | 11.31 seconds |
| Started | Sep 18 07:45:20 AM UTC 24 |
| Finished | Sep 18 07:45:32 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879212327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1879212327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1540896506 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 535898010 ps |
| CPU time | 12.84 seconds |
| Started | Sep 18 07:45:14 AM UTC 24 |
| Finished | Sep 18 07:45:28 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540896506 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1540896506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3983430725 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 126552517 ps |
| CPU time | 7.96 seconds |
| Started | Sep 18 07:45:13 AM UTC 24 |
| Finished | Sep 18 07:45:22 AM UTC 24 |
| Peak memory | 223720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983430725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3983430725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1967531922 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 416733329 ps |
| CPU time | 11.34 seconds |
| Started | Sep 18 07:45:13 AM UTC 24 |
| Finished | Sep 18 07:45:25 AM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196753192 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.1967531922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1070432083 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1469067417 ps |
| CPU time | 49.07 seconds |
| Started | Sep 18 07:45:23 AM UTC 24 |
| Finished | Sep 18 07:46:13 AM UTC 24 |
| Peak memory | 230784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1070432083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1070432083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3567351384 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 171982817 ps |
| CPU time | 5.97 seconds |
| Started | Sep 18 07:45:39 AM UTC 24 |
| Finished | Sep 18 07:45:46 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567351384 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3567351384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2850945976 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 7059877545 ps |
| CPU time | 215.76 seconds |
| Started | Sep 18 07:45:33 AM UTC 24 |
| Finished | Sep 18 07:49:12 AM UTC 24 |
| Peak memory | 259744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850945976 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.2850945976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3963429526 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 260710843 ps |
| CPU time | 15.64 seconds |
| Started | Sep 18 07:45:35 AM UTC 24 |
| Finished | Sep 18 07:45:52 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963429526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3963429526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2550147055 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 155648656 ps |
| CPU time | 7.62 seconds |
| Started | Sep 18 07:45:32 AM UTC 24 |
| Finished | Sep 18 07:45:41 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550147055 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2550147055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1522123837 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 140983942 ps |
| CPU time | 9.48 seconds |
| Started | Sep 18 07:45:28 AM UTC 24 |
| Finished | Sep 18 07:45:39 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522123837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1522123837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3853167270 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 312294212 ps |
| CPU time | 22.13 seconds |
| Started | Sep 18 07:45:29 AM UTC 24 |
| Finished | Sep 18 07:45:53 AM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385316727 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.3853167270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3095835755 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3471667095 ps |
| CPU time | 219.24 seconds |
| Started | Sep 18 07:45:39 AM UTC 24 |
| Finished | Sep 18 07:49:22 AM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3095835755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3095835755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.394512607 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 521377536 ps |
| CPU time | 5.04 seconds |
| Started | Sep 18 07:46:00 AM UTC 24 |
| Finished | Sep 18 07:46:06 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394512607 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.394512607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1157997134 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3819448743 ps |
| CPU time | 132.96 seconds |
| Started | Sep 18 07:45:52 AM UTC 24 |
| Finished | Sep 18 07:48:07 AM UTC 24 |
| Peak memory | 231164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157997134 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.1157997134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2282053944 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 251769307 ps |
| CPU time | 16.45 seconds |
| Started | Sep 18 07:45:53 AM UTC 24 |
| Finished | Sep 18 07:46:11 AM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282053944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2282053944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.100705046 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 563916139 ps |
| CPU time | 8.72 seconds |
| Started | Sep 18 07:45:52 AM UTC 24 |
| Finished | Sep 18 07:46:01 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100705046 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.100705046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1878671170 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 98709638 ps |
| CPU time | 8.14 seconds |
| Started | Sep 18 07:45:42 AM UTC 24 |
| Finished | Sep 18 07:45:51 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878671170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1878671170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3451513014 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 314421399 ps |
| CPU time | 19.33 seconds |
| Started | Sep 18 07:45:48 AM UTC 24 |
| Finished | Sep 18 07:46:08 AM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345151301 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.3451513014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.341239227 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4595510454 ps |
| CPU time | 39.88 seconds |
| Started | Sep 18 07:45:54 AM UTC 24 |
| Finished | Sep 18 07:46:35 AM UTC 24 |
| Peak memory | 232944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=341239227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 9.rom_ctrl_stress_all_with_rand_reset.341239227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest |
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