| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.49 | 96.77 | 91.99 | 97.67 | 100.00 | 98.19 | 98.06 | 99.77 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 65.12 | 65.12 | 92.31 | 92.31 | 70.37 | 70.37 | 56.45 | 56.45 | 40.00 | 40.00 | 89.49 | 89.49 | 93.88 | 93.88 | 13.35 | 13.35 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.117936043 |
| 81.85 | 16.73 | 95.78 | 3.47 | 79.92 | 9.55 | 81.97 | 25.52 | 40.00 | 0.00 | 92.03 | 2.54 | 95.67 | 1.79 | 87.59 | 74.24 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.755814957 |
| 89.61 | 7.76 | 95.91 | 0.12 | 82.44 | 2.53 | 92.28 | 10.30 | 80.00 | 40.00 | 92.75 | 0.72 | 95.82 | 0.15 | 88.06 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2794150632 |
| 93.38 | 3.77 | 96.65 | 0.74 | 87.78 | 5.34 | 93.38 | 1.10 | 93.33 | 13.33 | 96.38 | 3.62 | 96.42 | 0.60 | 89.70 | 1.64 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.226842072 |
| 94.38 | 1.01 | 96.65 | 0.00 | 88.06 | 0.28 | 93.47 | 0.10 | 100.00 | 6.67 | 96.38 | 0.00 | 96.42 | 0.00 | 89.70 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1166870571 |
| 95.34 | 0.96 | 96.77 | 0.12 | 90.45 | 2.39 | 96.10 | 2.62 | 100.00 | 0.00 | 97.46 | 1.09 | 96.42 | 0.00 | 90.16 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.448533675 |
| 96.24 | 0.90 | 96.77 | 0.00 | 90.87 | 0.42 | 96.10 | 0.00 | 100.00 | 0.00 | 97.46 | 0.00 | 96.42 | 0.00 | 96.02 | 5.85 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1064575560 |
| 96.48 | 0.25 | 96.77 | 0.00 | 91.15 | 0.28 | 97.20 | 1.10 | 100.00 | 0.00 | 97.83 | 0.36 | 96.42 | 0.00 | 96.02 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3509274124 |
| 96.67 | 0.19 | 96.77 | 0.00 | 91.29 | 0.14 | 97.20 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 97.61 | 1.19 | 96.02 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.403168622 |
| 96.81 | 0.13 | 96.77 | 0.00 | 91.29 | 0.00 | 97.20 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 97.61 | 0.00 | 96.96 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2140764504 |
| 96.92 | 0.11 | 96.77 | 0.00 | 91.43 | 0.14 | 97.25 | 0.05 | 100.00 | 0.00 | 98.19 | 0.36 | 97.61 | 0.00 | 97.19 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3995440008 |
| 97.03 | 0.11 | 96.77 | 0.00 | 91.99 | 0.56 | 97.47 | 0.23 | 100.00 | 0.00 | 98.19 | 0.00 | 97.61 | 0.00 | 97.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3546216436 |
| 97.13 | 0.10 | 96.77 | 0.00 | 91.99 | 0.00 | 97.47 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.61 | 0.00 | 97.89 | 0.70 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3473028852 |
| 97.20 | 0.07 | 96.77 | 0.00 | 91.99 | 0.00 | 97.47 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.61 | 0.00 | 98.36 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3783539766 |
| 97.27 | 0.07 | 96.77 | 0.00 | 91.99 | 0.00 | 97.47 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.61 | 0.00 | 98.83 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1961321000 |
| 97.33 | 0.06 | 96.77 | 0.00 | 91.99 | 0.00 | 97.53 | 0.05 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.15 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1452291024 |
| 97.38 | 0.05 | 96.77 | 0.00 | 91.99 | 0.00 | 97.67 | 0.15 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 99.30 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3085721720 |
| 97.42 | 0.03 | 96.77 | 0.00 | 91.99 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 99.53 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.328324712 |
| 97.45 | 0.03 | 96.77 | 0.00 | 91.99 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 99.77 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1804427635 |
| 97.47 | 0.02 | 96.77 | 0.00 | 91.99 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.91 | 0.15 | 99.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.135937504 |
| 97.49 | 0.02 | 96.77 | 0.00 | 91.99 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 98.06 | 0.15 | 99.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1546911774 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2313049636 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1277783683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3096730044 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3523755000 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2840720363 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3047199240 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.382359949 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3736545879 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2920635374 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1538156936 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1615726184 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1530505722 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2258424473 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.241609570 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3637561764 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3603677689 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1972620099 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2127672659 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2277980926 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2337351706 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3499423701 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.683485746 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2051104785 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1995706986 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.195110993 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3304015038 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1289866286 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3944480766 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3968174887 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4253897681 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2256135048 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.577212566 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1552766792 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1709346633 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.263730606 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2997205430 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2047872925 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.105433296 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1983858185 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1978016735 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3547458324 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3225756771 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2216264483 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4223806066 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.361157684 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4234832833 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2962151908 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2137234544 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1255544008 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.228130556 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.180562177 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.585419341 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1287318962 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3811708716 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1346603106 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4046491836 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3999796060 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2018178099 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3716371338 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4150318337 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3996133960 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1608348816 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3621050402 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.372001339 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.712347860 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3954371038 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1617732279 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3138448137 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4105728414 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3527197376 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.147873782 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1868139071 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1515596506 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3446004105 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2604277986 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3917228368 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4081003640 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2636263752 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2616823612 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3958510788 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.100832023 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4006206661 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2408021742 |
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| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1278951454 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3886570106 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1653933683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1013580599 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1508283172 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3177029636 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3542318841 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.52852212 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3898411504 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3500822073 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1924639095 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.566465187 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.493410515 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1014795751 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1898719139 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3682238821 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1005716068 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.489908459 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.72483311 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1468492179 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3115862538 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1499358054 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.601634762 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1580185399 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.969291843 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3041994125 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1385890238 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1166264735 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3123079619 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.490088910 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.202215116 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1615223891 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2209536994 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.525308514 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3764134640 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3720585299 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4086222934 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3154476251 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.959628700 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3323173380 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1803773093 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3652725679 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.291743344 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3043451470 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1998074214 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1960161399 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1637701778 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1146348940 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1088900813 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.765284028 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1265793941 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.4250261840 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2660714598 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.981407034 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2908104364 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3257499131 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2549259531 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1843843409 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3468103732 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.959428917 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3910246897 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3134537180 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3556133677 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.150151756 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.558385354 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3206308520 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.698453766 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2557243835 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4197553387 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1879212327 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1540896506 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3983430725 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1967531922 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1070432083 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3567351384 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2850945976 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3963429526 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2550147055 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1522123837 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3853167270 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3095835755 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.394512607 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1157997134 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2282053944 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.100705046 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1878671170 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3451513014 |
| /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.341239227 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3304626181 | Sep 18 07:42:05 AM UTC 24 | Sep 18 07:42:15 AM UTC 24 | 137135897 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1452291024 | Sep 18 07:42:07 AM UTC 24 | Sep 18 07:42:16 AM UTC 24 | 96045362 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.117936043 | Sep 18 07:42:06 AM UTC 24 | Sep 18 07:42:27 AM UTC 24 | 1069645549 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3509274124 | Sep 18 07:42:17 AM UTC 24 | Sep 18 07:42:34 AM UTC 24 | 250977622 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1038102447 | Sep 18 07:42:27 AM UTC 24 | Sep 18 07:42:35 AM UTC 24 | 129829459 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.1878271718 | Sep 18 07:42:30 AM UTC 24 | Sep 18 07:42:39 AM UTC 24 | 93664648 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.280672633 | Sep 18 07:42:35 AM UTC 24 | Sep 18 07:42:45 AM UTC 24 | 191792526 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.4225769517 | Sep 18 07:42:34 AM UTC 24 | Sep 18 07:42:47 AM UTC 24 | 463574289 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.4004822455 | Sep 18 07:42:39 AM UTC 24 | Sep 18 07:42:55 AM UTC 24 | 334157237 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1205827872 | Sep 18 07:42:57 AM UTC 24 | Sep 18 07:43:04 AM UTC 24 | 348494241 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.362369916 | Sep 18 07:43:05 AM UTC 24 | Sep 18 07:43:15 AM UTC 24 | 138020181 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1840866302 | Sep 18 07:43:07 AM UTC 24 | Sep 18 07:43:24 AM UTC 24 | 695384363 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.715793024 | Sep 18 07:43:16 AM UTC 24 | Sep 18 07:43:26 AM UTC 24 | 419666932 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2849938256 | Sep 18 07:43:25 AM UTC 24 | Sep 18 07:43:36 AM UTC 24 | 169008444 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3546216436 | Sep 18 07:43:36 AM UTC 24 | Sep 18 07:43:44 AM UTC 24 | 168264669 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2614466781 | Sep 18 07:42:27 AM UTC 24 | Sep 18 07:43:45 AM UTC 24 | 256085400 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3234282638 | Sep 18 07:43:44 AM UTC 24 | Sep 18 07:43:54 AM UTC 24 | 391297115 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.448533675 | Sep 18 07:43:26 AM UTC 24 | Sep 18 07:44:02 AM UTC 24 | 992757167 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1161252325 | Sep 18 07:43:46 AM UTC 24 | Sep 18 07:44:04 AM UTC 24 | 785551458 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1245022839 | Sep 18 07:43:55 AM UTC 24 | Sep 18 07:44:04 AM UTC 24 | 528071470 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.3102439818 | Sep 18 07:44:05 AM UTC 24 | Sep 18 07:44:13 AM UTC 24 | 442887187 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.226842072 | Sep 18 07:42:48 AM UTC 24 | Sep 18 07:44:14 AM UTC 24 | 724147519 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2023372852 | Sep 18 07:42:16 AM UTC 24 | Sep 18 07:44:14 AM UTC 24 | 5545397447 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.4096002637 | Sep 18 07:43:58 AM UTC 24 | Sep 18 07:44:15 AM UTC 24 | 996067390 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.2587829760 | Sep 18 07:44:14 AM UTC 24 | Sep 18 07:44:22 AM UTC 24 | 95360169 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3807630928 | Sep 18 07:44:15 AM UTC 24 | Sep 18 07:44:25 AM UTC 24 | 139100040 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4115561042 | Sep 18 07:44:23 AM UTC 24 | Sep 18 07:44:34 AM UTC 24 | 173413791 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1752617249 | Sep 18 07:44:26 AM UTC 24 | Sep 18 07:44:34 AM UTC 24 | 133731024 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3468103732 | Sep 18 07:44:30 AM UTC 24 | Sep 18 07:44:39 AM UTC 24 | 102994014 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.964008146 | Sep 18 07:44:15 AM UTC 24 | Sep 18 07:44:43 AM UTC 24 | 1041444352 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1843843409 | Sep 18 07:44:35 AM UTC 24 | Sep 18 07:44:44 AM UTC 24 | 398352311 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.959428917 | Sep 18 07:44:34 AM UTC 24 | Sep 18 07:44:49 AM UTC 24 | 408497194 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3257499131 | Sep 18 07:44:45 AM UTC 24 | Sep 18 07:44:53 AM UTC 24 | 521496214 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.558385354 | Sep 18 07:44:50 AM UTC 24 | Sep 18 07:44:59 AM UTC 24 | 94840623 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3995440008 | Sep 18 07:44:40 AM UTC 24 | Sep 18 07:45:02 AM UTC 24 | 3942206549 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.150151756 | Sep 18 07:44:57 AM UTC 24 | Sep 18 07:45:04 AM UTC 24 | 272640989 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.978952662 | Sep 18 07:42:35 AM UTC 24 | Sep 18 07:45:05 AM UTC 24 | 5225238035 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3809059204 | Sep 18 07:44:04 AM UTC 24 | Sep 18 07:45:12 AM UTC 24 | 643722360 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3910246897 | Sep 18 07:45:05 AM UTC 24 | Sep 18 07:45:13 AM UTC 24 | 171786507 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3556133677 | Sep 18 07:45:03 AM UTC 24 | Sep 18 07:45:19 AM UTC 24 | 178518000 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3206308520 | Sep 18 07:44:54 AM UTC 24 | Sep 18 07:45:19 AM UTC 24 | 1287379849 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3983430725 | Sep 18 07:45:13 AM UTC 24 | Sep 18 07:45:22 AM UTC 24 | 126552517 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1967531922 | Sep 18 07:45:13 AM UTC 24 | Sep 18 07:45:25 AM UTC 24 | 416733329 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1540896506 | Sep 18 07:45:14 AM UTC 24 | Sep 18 07:45:28 AM UTC 24 | 535898010 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.755814957 | Sep 18 07:42:19 AM UTC 24 | Sep 18 07:45:31 AM UTC 24 | 8679250492 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1879212327 | Sep 18 07:45:20 AM UTC 24 | Sep 18 07:45:32 AM UTC 24 | 256994055 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2557243835 | Sep 18 07:45:26 AM UTC 24 | Sep 18 07:45:34 AM UTC 24 | 132218288 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1522123837 | Sep 18 07:45:28 AM UTC 24 | Sep 18 07:45:39 AM UTC 24 | 140983942 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2550147055 | Sep 18 07:45:32 AM UTC 24 | Sep 18 07:45:41 AM UTC 24 | 155648656 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3567351384 | Sep 18 07:45:39 AM UTC 24 | Sep 18 07:45:46 AM UTC 24 | 171982817 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1878671170 | Sep 18 07:45:42 AM UTC 24 | Sep 18 07:45:51 AM UTC 24 | 98709638 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3963429526 | Sep 18 07:45:35 AM UTC 24 | Sep 18 07:45:52 AM UTC 24 | 260710843 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3853167270 | Sep 18 07:45:29 AM UTC 24 | Sep 18 07:45:53 AM UTC 24 | 312294212 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2794150632 | Sep 18 07:43:24 AM UTC 24 | Sep 18 07:45:59 AM UTC 24 | 12166674301 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3825364677 | Sep 18 07:43:26 AM UTC 24 | Sep 18 07:46:00 AM UTC 24 | 376673379 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.100705046 | Sep 18 07:45:52 AM UTC 24 | Sep 18 07:46:01 AM UTC 24 | 563916139 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.394512607 | Sep 18 07:46:00 AM UTC 24 | Sep 18 07:46:06 AM UTC 24 | 521377536 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3451513014 | Sep 18 07:45:48 AM UTC 24 | Sep 18 07:46:08 AM UTC 24 | 314421399 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2282053944 | Sep 18 07:45:53 AM UTC 24 | Sep 18 07:46:11 AM UTC 24 | 251769307 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2886026424 | Sep 18 07:46:02 AM UTC 24 | Sep 18 07:46:13 AM UTC 24 | 3110948537 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1070432083 | Sep 18 07:45:23 AM UTC 24 | Sep 18 07:46:13 AM UTC 24 | 1469067417 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1935913674 | Sep 18 07:44:03 AM UTC 24 | Sep 18 07:46:18 AM UTC 24 | 12353550202 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1896761743 | Sep 18 07:43:56 AM UTC 24 | Sep 18 07:46:19 AM UTC 24 | 7893928910 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.754794693 | Sep 18 07:46:11 AM UTC 24 | Sep 18 07:46:19 AM UTC 24 | 87073094 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.114286068 | Sep 18 07:44:24 AM UTC 24 | Sep 18 07:46:19 AM UTC 24 | 869510732 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3778453043 | Sep 18 07:46:01 AM UTC 24 | Sep 18 07:46:22 AM UTC 24 | 201621439 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2964214688 | Sep 18 07:46:07 AM UTC 24 | Sep 18 07:46:24 AM UTC 24 | 508409918 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3665832255 | Sep 18 07:46:15 AM UTC 24 | Sep 18 07:46:25 AM UTC 24 | 541212884 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.22092562 | Sep 18 07:46:20 AM UTC 24 | Sep 18 07:46:27 AM UTC 24 | 348351717 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.877181630 | Sep 18 07:44:16 AM UTC 24 | Sep 18 07:46:28 AM UTC 24 | 8718035050 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.896464900 | Sep 18 07:46:25 AM UTC 24 | Sep 18 07:46:32 AM UTC 24 | 231009119 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.341239227 | Sep 18 07:45:54 AM UTC 24 | Sep 18 07:46:35 AM UTC 24 | 4595510454 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1656334599 | Sep 18 07:46:20 AM UTC 24 | Sep 18 07:46:38 AM UTC 24 | 497925424 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3991400041 | Sep 18 07:46:30 AM UTC 24 | Sep 18 07:46:38 AM UTC 24 | 250109647 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3787741168 | Sep 18 07:46:23 AM UTC 24 | Sep 18 07:46:39 AM UTC 24 | 916071566 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3002663707 | Sep 18 07:46:13 AM UTC 24 | Sep 18 07:46:39 AM UTC 24 | 309683024 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.323756837 | Sep 18 07:46:28 AM UTC 24 | Sep 18 07:46:43 AM UTC 24 | 387303030 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.850101129 | Sep 18 07:46:36 AM UTC 24 | Sep 18 07:46:45 AM UTC 24 | 462377617 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3577687203 | Sep 18 07:46:40 AM UTC 24 | Sep 18 07:46:47 AM UTC 24 | 86378761 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2549259531 | Sep 18 07:44:36 AM UTC 24 | Sep 18 07:46:47 AM UTC 24 | 8119910584 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.830186709 | Sep 18 07:46:44 AM UTC 24 | Sep 18 07:46:52 AM UTC 24 | 2189383725 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2178416540 | Sep 18 07:46:38 AM UTC 24 | Sep 18 07:46:56 AM UTC 24 | 3124513104 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3804162783 | Sep 18 07:46:33 AM UTC 24 | Sep 18 07:46:58 AM UTC 24 | 390338630 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3258042614 | Sep 18 07:46:53 AM UTC 24 | Sep 18 07:46:59 AM UTC 24 | 378906500 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2316155906 | Sep 18 07:46:48 AM UTC 24 | Sep 18 07:47:02 AM UTC 24 | 347912933 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3134537180 | Sep 18 07:44:59 AM UTC 24 | Sep 18 07:47:03 AM UTC 24 | 10169841649 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2048833402 | Sep 18 07:47:00 AM UTC 24 | Sep 18 07:47:07 AM UTC 24 | 311763091 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.2354504091 | Sep 18 07:46:59 AM UTC 24 | Sep 18 07:47:09 AM UTC 24 | 97084196 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2074035777 | Sep 18 07:46:43 AM UTC 24 | Sep 18 07:47:10 AM UTC 24 | 1100138538 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1546911774 | Sep 18 07:47:02 AM UTC 24 | Sep 18 07:47:13 AM UTC 24 | 381631244 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.844513460 | Sep 18 07:47:00 AM UTC 24 | Sep 18 07:47:13 AM UTC 24 | 996475821 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3666247006 | Sep 18 07:46:40 AM UTC 24 | Sep 18 07:47:16 AM UTC 24 | 4798454813 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.1121950724 | Sep 18 07:46:57 AM UTC 24 | Sep 18 07:47:16 AM UTC 24 | 422141676 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.70660511 | Sep 18 07:47:11 AM UTC 24 | Sep 18 07:47:17 AM UTC 24 | 131906296 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.349444941 | Sep 18 07:47:02 AM UTC 24 | Sep 18 07:47:23 AM UTC 24 | 1400803310 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1600947669 | Sep 18 07:47:09 AM UTC 24 | Sep 18 07:47:23 AM UTC 24 | 177941327 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1257102915 | Sep 18 07:47:14 AM UTC 24 | Sep 18 07:47:23 AM UTC 24 | 98497896 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2800755145 | Sep 18 07:47:14 AM UTC 24 | Sep 18 07:47:26 AM UTC 24 | 651999925 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2612839931 | Sep 18 07:47:17 AM UTC 24 | Sep 18 07:47:29 AM UTC 24 | 556969016 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3715601628 | Sep 18 07:47:21 AM UTC 24 | Sep 18 07:47:31 AM UTC 24 | 98775190 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3822354544 | Sep 18 07:47:24 AM UTC 24 | Sep 18 07:47:32 AM UTC 24 | 323686706 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2051359879 | Sep 18 07:47:17 AM UTC 24 | Sep 18 07:47:32 AM UTC 24 | 220797333 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3577258655 | Sep 18 07:47:20 AM UTC 24 | Sep 18 07:47:34 AM UTC 24 | 1212580450 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.821891671 | Sep 18 07:47:29 AM UTC 24 | Sep 18 07:47:35 AM UTC 24 | 222697683 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3682694439 | Sep 18 07:47:23 AM UTC 24 | Sep 18 07:47:38 AM UTC 24 | 250465442 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3005964460 | Sep 18 07:47:33 AM UTC 24 | Sep 18 07:47:41 AM UTC 24 | 366449849 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2170383688 | Sep 18 07:47:33 AM UTC 24 | Sep 18 07:47:42 AM UTC 24 | 116250744 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2693979826 | Sep 18 07:47:36 AM UTC 24 | Sep 18 07:47:45 AM UTC 24 | 98078751 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1042793841 | Sep 18 07:47:32 AM UTC 24 | Sep 18 07:47:47 AM UTC 24 | 756512836 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1558325170 | Sep 18 07:47:42 AM UTC 24 | Sep 18 07:47:49 AM UTC 24 | 85648658 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.4103755663 | Sep 18 07:47:28 AM UTC 24 | Sep 18 07:47:50 AM UTC 24 | 228349032 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1930853744 | Sep 18 07:47:35 AM UTC 24 | Sep 18 07:47:52 AM UTC 24 | 226420666 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1959457921 | Sep 18 07:46:38 AM UTC 24 | Sep 18 07:47:57 AM UTC 24 | 1715829899 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3804549963 | Sep 18 07:47:48 AM UTC 24 | Sep 18 07:47:58 AM UTC 24 | 276776386 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.658093332 | Sep 18 07:47:42 AM UTC 24 | Sep 18 07:47:59 AM UTC 24 | 255581853 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.351289641 | Sep 18 07:47:53 AM UTC 24 | Sep 18 07:47:59 AM UTC 24 | 105166948 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2291683648 | Sep 18 07:46:46 AM UTC 24 | Sep 18 07:48:02 AM UTC 24 | 1448736163 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1589178271 | Sep 18 07:42:46 AM UTC 24 | Sep 18 07:48:04 AM UTC 24 | 9898692786 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1589451432 | Sep 18 07:47:51 AM UTC 24 | Sep 18 07:48:07 AM UTC 24 | 261573346 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1157997134 | Sep 18 07:45:52 AM UTC 24 | Sep 18 07:48:07 AM UTC 24 | 3819448743 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3168995937 | Sep 18 07:47:00 AM UTC 24 | Sep 18 07:48:08 AM UTC 24 | 1351091351 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2043946632 | Sep 18 07:47:58 AM UTC 24 | Sep 18 07:48:08 AM UTC 24 | 270723262 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.998058923 | Sep 18 07:47:59 AM UTC 24 | Sep 18 07:48:08 AM UTC 24 | 96473243 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3982327504 | Sep 18 07:48:03 AM UTC 24 | Sep 18 07:48:09 AM UTC 24 | 333520497 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1166870571 | Sep 18 07:46:19 AM UTC 24 | Sep 18 07:48:10 AM UTC 24 | 6554920575 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2129027016 | Sep 18 07:47:17 AM UTC 24 | Sep 18 07:48:11 AM UTC 24 | 33040986738 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2241786741 | Sep 18 07:47:45 AM UTC 24 | Sep 18 07:48:11 AM UTC 24 | 425081130 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4200369172 | Sep 18 07:46:28 AM UTC 24 | Sep 18 07:48:14 AM UTC 24 | 8612191411 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3684237864 | Sep 18 07:48:00 AM UTC 24 | Sep 18 07:48:14 AM UTC 24 | 262634606 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3271216041 | Sep 18 07:48:06 AM UTC 24 | Sep 18 07:48:15 AM UTC 24 | 446881109 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2945302456 | Sep 18 07:48:09 AM UTC 24 | Sep 18 07:48:16 AM UTC 24 | 128185383 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1200517837 | Sep 18 07:48:10 AM UTC 24 | Sep 18 07:48:18 AM UTC 24 | 583119139 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4197553387 | Sep 18 07:45:20 AM UTC 24 | Sep 18 07:48:20 AM UTC 24 | 9031338226 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.1804977877 | Sep 18 07:48:14 AM UTC 24 | Sep 18 07:48:21 AM UTC 24 | 497954235 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.4218443435 | Sep 18 07:48:15 AM UTC 24 | Sep 18 07:48:22 AM UTC 24 | 377726758 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3494787563 | Sep 18 07:48:05 AM UTC 24 | Sep 18 07:48:23 AM UTC 24 | 437270349 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1114223089 | Sep 18 07:48:08 AM UTC 24 | Sep 18 07:48:24 AM UTC 24 | 669401819 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3319782800 | Sep 18 07:48:15 AM UTC 24 | Sep 18 07:48:24 AM UTC 24 | 119718102 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2480238964 | Sep 18 07:48:19 AM UTC 24 | Sep 18 07:48:25 AM UTC 24 | 86849304 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.396501429 | Sep 18 07:46:07 AM UTC 24 | Sep 18 07:48:28 AM UTC 24 | 27979310805 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2459353551 | Sep 18 07:48:17 AM UTC 24 | Sep 18 07:48:28 AM UTC 24 | 618418660 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.4022973116 | Sep 18 07:48:12 AM UTC 24 | Sep 18 07:48:29 AM UTC 24 | 1040194178 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3497052086 | Sep 18 07:48:21 AM UTC 24 | Sep 18 07:48:31 AM UTC 24 | 137239747 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2221621428 | Sep 18 07:48:26 AM UTC 24 | Sep 18 07:48:31 AM UTC 24 | 131694878 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2227581238 | Sep 18 07:48:09 AM UTC 24 | Sep 18 07:48:33 AM UTC 24 | 1669500846 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.333975986 | Sep 18 07:48:26 AM UTC 24 | Sep 18 07:48:35 AM UTC 24 | 149792201 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1804427635 | Sep 18 07:46:59 AM UTC 24 | Sep 18 07:48:36 AM UTC 24 | 1601906476 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2422331167 | Sep 18 07:48:20 AM UTC 24 | Sep 18 07:48:37 AM UTC 24 | 2012410283 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3280846948 | Sep 18 07:48:38 AM UTC 24 | Sep 18 07:48:51 AM UTC 24 | 977441202 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1876450115 | Sep 18 07:48:23 AM UTC 24 | Sep 18 07:48:38 AM UTC 24 | 519116545 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.530570567 | Sep 18 07:48:32 AM UTC 24 | Sep 18 07:48:40 AM UTC 24 | 132162779 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.755157710 | Sep 18 07:48:29 AM UTC 24 | Sep 18 07:48:42 AM UTC 24 | 516099304 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.823213489 | Sep 18 07:48:36 AM UTC 24 | Sep 18 07:48:46 AM UTC 24 | 1498384858 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3927832400 | Sep 18 07:48:30 AM UTC 24 | Sep 18 07:48:47 AM UTC 24 | 712237674 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1538583709 | Sep 18 07:48:34 AM UTC 24 | Sep 18 07:48:49 AM UTC 24 | 505315017 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.330466199 | Sep 18 07:48:41 AM UTC 24 | Sep 18 07:48:49 AM UTC 24 | 834617247 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.698453766 | Sep 18 07:45:05 AM UTC 24 | Sep 18 07:48:50 AM UTC 24 | 3291809814 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1946284836 | Sep 18 07:48:08 AM UTC 24 | Sep 18 07:48:53 AM UTC 24 | 1104929191 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.3916723842 | Sep 18 07:48:46 AM UTC 24 | Sep 18 07:48:56 AM UTC 24 | 201287652 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2381311614 | Sep 18 07:46:25 AM UTC 24 | Sep 18 07:48:57 AM UTC 24 | 5290218164 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3841672026 | Sep 18 07:48:51 AM UTC 24 | Sep 18 07:48:59 AM UTC 24 | 272772926 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3085721720 | Sep 18 07:44:44 AM UTC 24 | Sep 18 07:49:01 AM UTC 24 | 7037642052 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1971382547 | Sep 18 07:48:50 AM UTC 24 | Sep 18 07:49:03 AM UTC 24 | 179112271 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1980774513 | Sep 18 07:48:53 AM UTC 24 | Sep 18 07:49:03 AM UTC 24 | 293644577 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2664424523 | Sep 18 07:48:43 AM UTC 24 | Sep 18 07:49:05 AM UTC 24 | 319884265 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.3785944391 | Sep 18 07:49:00 AM UTC 24 | Sep 18 07:49:08 AM UTC 24 | 128302424 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2416987677 | Sep 18 07:46:20 AM UTC 24 | Sep 18 07:49:11 AM UTC 24 | 11621601470 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2721099871 | Sep 18 07:49:03 AM UTC 24 | Sep 18 07:49:12 AM UTC 24 | 338305562 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3473028852 | Sep 18 07:48:52 AM UTC 24 | Sep 18 07:49:12 AM UTC 24 | 1002742872 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2850945976 | Sep 18 07:45:33 AM UTC 24 | Sep 18 07:49:12 AM UTC 24 | 7059877545 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.281418888 | Sep 18 07:48:57 AM UTC 24 | Sep 18 07:49:13 AM UTC 24 | 670121261 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1952909552 | Sep 18 07:47:49 AM UTC 24 | Sep 18 07:49:15 AM UTC 24 | 8330832836 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1580744784 | Sep 18 07:49:13 AM UTC 24 | Sep 18 07:49:21 AM UTC 24 | 133324504 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2680816546 | Sep 18 07:49:13 AM UTC 24 | Sep 18 07:49:22 AM UTC 24 | 240728028 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3095835755 | Sep 18 07:45:39 AM UTC 24 | Sep 18 07:49:22 AM UTC 24 | 3471667095 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.353747886 | Sep 18 07:49:05 AM UTC 24 | Sep 18 07:49:22 AM UTC 24 | 254275217 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.150515476 | Sep 18 07:47:03 AM UTC 24 | Sep 18 07:49:28 AM UTC 24 | 1650371130 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.4104430548 | Sep 18 07:49:14 AM UTC 24 | Sep 18 07:49:28 AM UTC 24 | 598111569 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1755137953 | Sep 18 07:49:21 AM UTC 24 | Sep 18 07:49:29 AM UTC 24 | 572272029 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3054264748 | Sep 18 07:49:13 AM UTC 24 | Sep 18 07:49:30 AM UTC 24 | 284792828 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2193468078 | Sep 18 07:49:01 AM UTC 24 | Sep 18 07:49:32 AM UTC 24 | 3714661684 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.548327798 | Sep 18 07:49:23 AM UTC 24 | Sep 18 07:49:33 AM UTC 24 | 292911372 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2348326112 | Sep 18 07:49:29 AM UTC 24 | Sep 18 07:49:37 AM UTC 24 | 220724554 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.657539554 | Sep 18 07:49:30 AM UTC 24 | Sep 18 07:49:38 AM UTC 24 | 1542532545 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.439003820 | Sep 18 07:49:34 AM UTC 24 | Sep 18 07:49:41 AM UTC 24 | 929747643 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1383080639 | Sep 18 07:47:42 AM UTC 24 | Sep 18 07:49:41 AM UTC 24 | 4054305758 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1275439507 | Sep 18 07:49:24 AM UTC 24 | Sep 18 07:49:42 AM UTC 24 | 499857424 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1481024141 | Sep 18 07:49:23 AM UTC 24 | Sep 18 07:49:42 AM UTC 24 | 2707641543 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2888846149 | Sep 18 07:49:34 AM UTC 24 | Sep 18 07:49:45 AM UTC 24 | 347901139 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2394989160 | Sep 18 07:47:23 AM UTC 24 | Sep 18 07:49:46 AM UTC 24 | 3352120696 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3427589005 | Sep 18 07:49:30 AM UTC 24 | Sep 18 07:49:46 AM UTC 24 | 765117284 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3721741853 | Sep 18 07:49:39 AM UTC 24 | Sep 18 07:49:48 AM UTC 24 | 98215136 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.3601380644 | Sep 18 07:49:43 AM UTC 24 | Sep 18 07:49:51 AM UTC 24 | 620728421 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.577592715 | Sep 18 07:49:38 AM UTC 24 | Sep 18 07:49:53 AM UTC 24 | 1578605347 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3582686687 | Sep 18 07:49:46 AM UTC 24 | Sep 18 07:49:57 AM UTC 24 | 306453326 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1291402009 | Sep 18 07:49:46 AM UTC 24 | Sep 18 07:49:57 AM UTC 24 | 1048272452 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1594565197 | Sep 18 07:48:29 AM UTC 24 | Sep 18 07:49:58 AM UTC 24 | 5462639691 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1513488494 | Sep 18 07:49:52 AM UTC 24 | Sep 18 07:49:59 AM UTC 24 | 541207457 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3911546077 | Sep 18 07:46:48 AM UTC 24 | Sep 18 07:50:00 AM UTC 24 | 3236379645 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1304608916 | Sep 18 07:49:42 AM UTC 24 | Sep 18 07:50:00 AM UTC 24 | 520823004 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1052052150 | Sep 18 07:46:09 AM UTC 24 | Sep 18 07:50:01 AM UTC 24 | 10066353292 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3106518292 | Sep 18 07:49:48 AM UTC 24 | Sep 18 07:50:02 AM UTC 24 | 261878197 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.569109128 | Sep 18 07:44:24 AM UTC 24 | Sep 18 07:50:03 AM UTC 24 | 4231174899 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3451007630 | Sep 18 07:50:01 AM UTC 24 | Sep 18 07:50:07 AM UTC 24 | 88244440 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.304372369 | Sep 18 07:49:58 AM UTC 24 | Sep 18 07:50:07 AM UTC 24 | 552018657 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2984379495 | Sep 18 07:49:03 AM UTC 24 | Sep 18 07:50:08 AM UTC 24 | 2223652711 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1201922759 | Sep 18 07:50:02 AM UTC 24 | Sep 18 07:50:12 AM UTC 24 | 103022291 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3489742607 | Sep 18 07:50:01 AM UTC 24 | Sep 18 07:50:12 AM UTC 24 | 599552766 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4269494841 | Sep 18 07:48:07 AM UTC 24 | Sep 18 07:50:12 AM UTC 24 | 6450975909 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1275393112 | Sep 18 07:48:00 AM UTC 24 | Sep 18 07:50:14 AM UTC 24 | 8387314422 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3032360842 | Sep 18 07:49:55 AM UTC 24 | Sep 18 07:50:14 AM UTC 24 | 709324046 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1213753669 | Sep 18 07:50:08 AM UTC 24 | Sep 18 07:50:15 AM UTC 24 | 518075356 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2823242423 | Sep 18 07:50:04 AM UTC 24 | Sep 18 07:50:15 AM UTC 24 | 1032123998 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2884349434 | Sep 18 07:48:22 AM UTC 24 | Sep 18 07:50:16 AM UTC 24 | 2187769517 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2979446790 | Sep 18 07:47:24 AM UTC 24 | Sep 18 07:50:16 AM UTC 24 | 11621304592 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1781190400 | Sep 18 07:49:59 AM UTC 24 | Sep 18 07:50:16 AM UTC 24 | 1187052524 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3989876678 | Sep 18 07:50:09 AM UTC 24 | Sep 18 07:50:17 AM UTC 24 | 193037180 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2287341741 | Sep 18 07:47:51 AM UTC 24 | Sep 18 07:50:19 AM UTC 24 | 7920591455 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2358058995 | Sep 18 07:50:15 AM UTC 24 | Sep 18 07:50:21 AM UTC 24 | 517172568 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3601048358 | Sep 18 07:48:49 AM UTC 24 | Sep 18 07:50:21 AM UTC 24 | 3986236498 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2620796037 | Sep 18 07:50:16 AM UTC 24 | Sep 18 07:50:22 AM UTC 24 | 97504366 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1540924933 | Sep 18 07:47:10 AM UTC 24 | Sep 18 07:50:22 AM UTC 24 | 10082143136 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.1878027287 | Sep 18 07:50:08 AM UTC 24 | Sep 18 07:50:23 AM UTC 24 | 209006213 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1841543276 | Sep 18 07:50:17 AM UTC 24 | Sep 18 07:50:25 AM UTC 24 | 498337893 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1508283172 | Sep 18 07:50:19 AM UTC 24 | Sep 18 07:50:27 AM UTC 24 | 99685015 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3886570106 | Sep 18 07:50:23 AM UTC 24 | Sep 18 07:50:29 AM UTC 24 | 438323590 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.3099981681 | Sep 18 07:50:17 AM UTC 24 | Sep 18 07:50:30 AM UTC 24 | 1036287161 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1013580599 | Sep 18 07:50:22 AM UTC 24 | Sep 18 07:50:33 AM UTC 24 | 173891785 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3241859974 | Sep 18 07:50:15 AM UTC 24 | Sep 18 07:50:34 AM UTC 24 | 370450134 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.745945618 | Sep 18 07:48:11 AM UTC 24 | Sep 18 07:50:35 AM UTC 24 | 11677122777 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.566465187 | Sep 18 07:50:23 AM UTC 24 | Sep 18 07:50:36 AM UTC 24 | 742298203 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2861213252 | Sep 18 07:48:58 AM UTC 24 | Sep 18 07:50:36 AM UTC 24 | 6863677294 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1924639095 | Sep 18 07:50:26 AM UTC 24 | Sep 18 07:50:36 AM UTC 24 | 135888891 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2907508052 | Sep 18 07:50:12 AM UTC 24 | Sep 18 07:50:37 AM UTC 24 | 1661910805 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1447035464 | Sep 18 07:48:24 AM UTC 24 | Sep 18 07:50:37 AM UTC 24 | 10976604396 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2576414214 | Sep 18 07:49:49 AM UTC 24 | Sep 18 07:50:37 AM UTC 24 | 1319726535 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.186236814 | Sep 18 07:47:30 AM UTC 24 | Sep 18 07:50:38 AM UTC 24 | 2427716683 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.52852212 | Sep 18 07:50:34 AM UTC 24 | Sep 18 07:50:40 AM UTC 24 | 132323599 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2358043120 | Sep 18 07:49:42 AM UTC 24 | Sep 18 07:50:41 AM UTC 24 | 3229691267 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3177029636 | Sep 18 07:50:18 AM UTC 24 | Sep 18 07:50:42 AM UTC 24 | 1206192734 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3500822073 | Sep 18 07:50:31 AM UTC 24 | Sep 18 07:50:44 AM UTC 24 | 172312215 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2151866801 | Sep 18 07:49:14 AM UTC 24 | Sep 18 07:50:44 AM UTC 24 | 1691091872 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1014795751 | Sep 18 07:50:38 AM UTC 24 | Sep 18 07:50:45 AM UTC 24 | 234426183 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1005716068 | Sep 18 07:50:36 AM UTC 24 | Sep 18 07:50:46 AM UTC 24 | 521281237 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2238953575 | Sep 18 07:48:16 AM UTC 24 | Sep 18 07:50:46 AM UTC 24 | 1753071007 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.601634762 | Sep 18 07:50:38 AM UTC 24 | Sep 18 07:50:47 AM UTC 24 | 433165193 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1468492179 | Sep 18 07:50:42 AM UTC 24 | Sep 18 07:50:51 AM UTC 24 | 428235247 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3682238821 | Sep 18 07:50:37 AM UTC 24 | Sep 18 07:50:52 AM UTC 24 | 1390927187 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1031901617 | Sep 18 07:48:37 AM UTC 24 | Sep 18 07:50:52 AM UTC 24 | 2501217664 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_17/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1499358054 | Sep 18 07:50:40 AM UTC 24 | Sep 18 07:50:53 AM UTC 24 | 168832474 ps |
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