Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

564750

1

T4

275

T5

172

T6

85

full_word

353798

1

T4

41

T5

17

T6

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	918238	1			T4	316		T5	189		T6	89
auto[TlIntgErrCmd]	120	1			T70	3		T71	7		T72	5
auto[TlIntgErrData]	93	1			T70	5		T71	7		T72	2
auto[TlIntgErrBoth]	97	1			T70	2		T71	6		T72	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167682

1

T4

316

T5

189

T6

89

auto[1]

750866

1

T14

2457

T15

5792

T16

10086

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	82344	1			T4	275		T5	172		T6	85
auto[TlIntgErrNone]	partial	auto[1]	482111	1			T14	1498		T15	4093		T16	6758
auto[TlIntgErrNone]	full_word	auto[0]	85202	1			T4	41		T5	17		T6	4
auto[TlIntgErrNone]	full_word	auto[1]	268581	1			T14	959		T15	1699		T16	3328
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T70	2		T71	1		T72	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T70	1		T71	5		T72	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T110	1		T111	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T71	1		T112	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T70	5		T71	2		T72	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T71	5		T72	1		T114	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T115	3		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T71	1		T72	1		T116	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T70	1		T71	5		T72	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T70	1		T117	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T118	1		T119	1		T117	2