Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

541849

1

T2

26

T3

314

T4

42

full_word

327291

1

T2

3

T3

33

T4

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	868800	1			T2	29		T3	347		T4	49
auto[TlIntgErrCmd]	107	1			T72	3		T73	3		T74	3
auto[TlIntgErrData]	116	1			T72	5		T73	2		T74	2
auto[TlIntgErrBoth]	117	1			T72	2		T73	5		T74	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156092

1

T2

29

T3

347

T4

49

auto[1]

713048

1

T12

4599

T13

6523

T14

2391

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	77084	1			T2	26		T3	314		T4	42
auto[TlIntgErrNone]	partial	auto[1]	464450	1			T12	3121		T13	4470		T14	1674
auto[TlIntgErrNone]	full_word	auto[0]	78860	1			T2	3		T3	33		T4	7
auto[TlIntgErrNone]	full_word	auto[1]	248406	1			T12	1478		T13	2053		T14	717
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T74	1		T130	1		T133	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T72	2		T73	3		T74	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T130	1		T139	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T72	1		T137	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T72	3		T73	2		T74	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T72	1		T130	2		T132	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T132	1		T138	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T72	1		T132	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T72	2		T73	2		T74	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T73	3		T74	3		T130	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T140	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T130	1		T134	1		T136	1