Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
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Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_kmac_cg 100.00 1 100 1 64 64




Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_kmac_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group Instance rom_ctrl_kmac_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_kmac_done 3 0 3 100.00 100 1 1 0
cp_kmac_ready 4 0 4 100.00 100 1 1 0


Summary for Variable cp_kmac_done

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_kmac_done

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
kmac_first 482 1 T1 1 T3 1 T7 2
same_cycle 11 1 T51 1 T13 1 T52 1
rom_first 1149 1 T2 1 T4 1 T5 1



Summary for Variable cp_kmac_ready

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_kmac_ready

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
stall_repeat 3711222 1 T4 1980 T5 2036 T8 2084
stall_long 247617 1 T46 8842 T49 8971 T12 17464
stall_1 3333862 1 T4 4016 T5 4070 T8 4127
zero_delay_5 7821144 1 T1 8180 T2 8180 T3 8180