Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64
tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

---

Group Instance : tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[0]]	0	0			-	-		-	-		-	-
auto[1]	935883	0			T2	44		T3	374		T4	23

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	935657	1			T2	44		T3	374		T4	23
values[1]	35	1			T67	1		T68	4		T117	1
values[2]	1	1			T118	1		-	-		-	-
values[3]	106	1			T66	5		T67	6		T68	4

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	935653	1			T2	44		T3	374		T4	23
values[1]	27	1			T66	1		T67	1		T68	2
values[2]	7	1			T68	1		T119	1		T120	2
values[3]	116	1			T66	4		T67	9		T68	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	935543	1			T2	44		T3	374		T4	23
auto[TlIntgErrCmd]	110	1			T66	2		T67	8		T68	5
auto[TlIntgErrData]	114	1			T66	2		T67	6		T68	9
auto[TlIntgErrBoth]	116	1			T66	6		T67	6		T68	6

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	783707	0			T1	11		T2	16		T4	16

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	783474	1			T1	11		T2	16		T4	16
values[1]	30	1			T66	2		T67	1		T68	3
values[2]	3	1			T119	1		T121	1		T122	1
values[3]	118	1			T66	4		T67	7		T68	8

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	783488	1			T1	11		T2	16		T4	16
values[1]	24	1			T117	1		T123	5		T124	1
values[2]	7	1			T125	1		T118	1		T126	1
values[3]	104	1			T66	2		T67	7		T68	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	783367	1			T1	11		T2	16		T4	16
auto[TlIntgErrCmd]	121	1			T66	5		T67	8		T68	9
auto[TlIntgErrData]	107	1			T66	1		T67	9		T68	5
auto[TlIntgErrBoth]	112	1			T66	4		T67	3		T68	6