Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

575731

1

T2

41

T3

341

T4

23

full_word

360152

1

T2

3

T3

33

T5

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	935543	1			T2	44		T3	374		T4	23
auto[TlIntgErrCmd]	110	1			T66	2		T67	8		T68	5
auto[TlIntgErrData]	114	1			T66	2		T67	6		T68	9
auto[TlIntgErrBoth]	116	1			T66	6		T67	6		T68	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171067

1

T2

44

T3

374

T4

23

auto[1]

764816

1

T15

9937

T16

10850

T17

20818

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	83718	1			T2	41		T3	341		T4	23
auto[TlIntgErrNone]	partial	auto[1]	491701	1			T15	5978		T16	7124		T17	13046
auto[TlIntgErrNone]	full_word	auto[0]	87189	1			T2	3		T3	33		T5	13
auto[TlIntgErrNone]	full_word	auto[1]	272935	1			T15	3959		T16	3726		T17	7772
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T67	3		T68	1		T119	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T66	2		T67	5		T68	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T68	1		T127	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T117	1		T125	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T66	1		T67	4		T68	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T66	1		T67	1		T68	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T68	1		T123	1		T124	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T67	1		T68	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T67	3		T68	2		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T66	5		T67	3		T68	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T124	1		T129	2		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T66	1		T68	1		T124	1