Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

559918

1

T1

42

T3

120

T4

274

full_word

350276

1

T1

3

T3

12

T4

30

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	909894	1			T1	45		T3	132		T4	304
auto[TlIntgErrCmd]	86	1			T72	3		T73	3		T74	4
auto[TlIntgErrData]	108	1			T72	2		T73	3		T74	3
auto[TlIntgErrBoth]	106	1			T72	5		T73	4		T74	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162021

1

T1

45

T3

132

T4

304

auto[1]

748173

1

T13

9222

T14

16172

T15

13644

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	77582	1			T1	42		T3	120		T4	274
auto[TlIntgErrNone]	partial	auto[1]	482069	1			T13	5958		T14	10307		T15	9274
auto[TlIntgErrNone]	full_word	auto[0]	84292	1			T1	3		T3	12		T4	30
auto[TlIntgErrNone]	full_word	auto[1]	265951	1			T13	3264		T14	5865		T15	4370
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T72	1		T74	2		T139	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T72	2		T73	3		T74	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T144	1		T138	1		T142	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T145	1		T138	1		T142	2
auto[TlIntgErrData]	partial	auto[0]	59	1			T72	2		T74	2		T139	4
auto[TlIntgErrData]	partial	auto[1]	37	1			T73	2		T74	1		T139	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T73	1		T136	1		T141	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T145	1		T144	1		T143	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T72	3		T139	1		T136	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T72	2		T73	4		T74	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T136	2		T143	2		T146	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T146	1		T147	1		T148	1