Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

578369

1

T1

267

T2

34

T3

20

full_word

354734

1

T1

29

T2

4

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	932783	1			T1	296		T2	38		T3	21
auto[TlIntgErrCmd]	110	1			T74	6		T75	4		T76	6
auto[TlIntgErrData]	110	1			T74	1		T75	5		T76	5
auto[TlIntgErrBoth]	100	1			T74	3		T75	1		T76	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167876

1

T1

296

T2

38

T3

21

auto[1]

765227

1

T12

11776

T13

12458

T14

15863

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	82247	1			T1	267		T2	34		T3	20
auto[TlIntgErrNone]	partial	auto[1]	495835	1			T12	7784		T13	7786		T14	10278
auto[TlIntgErrNone]	full_word	auto[0]	85492	1			T1	29		T2	4		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	269209	1			T12	3992		T13	4672		T14	5585
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T75	2		T76	3		T124	4
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T74	6		T75	2		T76	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T124	1		T127	1		T131	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T124	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T74	1		T75	1		T76	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T75	4		T76	2		T124	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T132	1		T130	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T124	1		T127	1		T133	2
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T74	1		T76	2		T124	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T75	1		T76	6		T124	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T74	1		T127	1		T135	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T74	1		T76	1		T132	2