Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 59675 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1802919 1 T1 3 T2 30 T3 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 474665 1 T1 42 T2 301 T3 75
values[0x0] 681829 1 T11 22943 T12 19618 T13 15943
values[0x1] 706100 1 T11 23876 T12 20696 T13 16476



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 32062 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1830532 1 T1 27 T2 184 T3 44



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 7021 1 T8 1 T19 1 T14 1
valid_sources[0x01] 8257 1 T20 1 T85 1 T144 3
valid_sources[0x02] 5503 1 T19 1 T143 4 T145 3
valid_sources[0x03] 6499 1 T19 1 T34 1 T38 3
valid_sources[0x04] 6695 1 T34 1 T85 1 T86 3
valid_sources[0x05] 7271 1 T1 1 T3 1 T20 2
valid_sources[0x06] 6341 1 T3 1 T20 1 T68 2
valid_sources[0x07] 8958 1 T83 1 T34 1 T145 1
valid_sources[0x08] 7940 1 T83 1 T38 1 T85 1
valid_sources[0x09] 7602 1 T18 74 T20 1 T34 1
valid_sources[0x0a] 6977 1 T3 1 T145 6 T144 2
valid_sources[0x0b] 6673 1 T34 2 T145 4 T86 1
valid_sources[0x0c] 8532 1 T20 2 T83 1 T34 1
valid_sources[0x0d] 8032 1 T3 2 T20 1 T34 2
valid_sources[0x0e] 7286 1 T15 1 T34 1 T146 1
valid_sources[0x0f] 7465 1 T3 1 T68 6 T83 1
valid_sources[0x10] 9335 1 T20 1 T145 2 T144 2
valid_sources[0x11] 9451 1 T1 1 T14 2 T34 1
valid_sources[0x12] 9267 1 T8 6 T20 1 T15 1
valid_sources[0x13] 7865 1 T6 2 T19 1 T14 3
valid_sources[0x14] 6681 1 T1 1 T14 1 T20 3
valid_sources[0x15] 7382 1 T20 2 T34 1 T145 1
valid_sources[0x16] 7733 1 T3 1 T20 2 T31 4
valid_sources[0x17] 5580 1 T3 1 T34 1 T145 4
valid_sources[0x18] 7699 1 T1 1 T34 1 T145 1
valid_sources[0x19] 6845 1 T1 1 T17 17 T34 1
valid_sources[0x1a] 7270 1 T20 3 T34 2 T145 2
valid_sources[0x1b] 8689 1 T20 2 T15 12 T38 2
valid_sources[0x1c] 7667 1 T34 1 T145 1 T147 1
valid_sources[0x1d] 6898 1 T3 1 T20 1 T15 4
valid_sources[0x1e] 6291 1 T3 1 T34 2 T31 1
valid_sources[0x1f] 6696 1 T1 1 T20 2 T145 1
valid_sources[0x20] 6311 1 T20 2 T145 2 T86 2
valid_sources[0x21] 6717 1 T19 2 T68 4 T83 1
valid_sources[0x22] 7664 1 T124 21 T34 1 T38 2
valid_sources[0x23] 8155 1 T2 20 T20 2 T38 1
valid_sources[0x24] 6024 1 T83 1 T34 1 T145 1
valid_sources[0x25] 7024 1 T3 2 T34 1 T145 1
valid_sources[0x26] 7898 1 T3 1 T8 9 T145 1
valid_sources[0x27] 6602 1 T19 1 T20 3 T15 3
valid_sources[0x28] 5910 1 T20 1 T34 1 T31 9
valid_sources[0x29] 7145 1 T20 3 T15 3 T34 3
valid_sources[0x2a] 7456 1 T3 2 T83 1 T34 2
valid_sources[0x2b] 7811 1 T20 3 T145 2 T85 1
valid_sources[0x2c] 6312 1 T20 1 T83 1 T38 2
valid_sources[0x2d] 8187 1 T18 13 T34 1 T145 2
valid_sources[0x2e] 9467 1 T67 18 T145 1 T144 5
valid_sources[0x2f] 8132 1 T1 1 T14 3 T34 1
valid_sources[0x30] 8385 1 T3 1 T20 1 T67 19
valid_sources[0x31] 7116 1 T1 1 T19 2 T34 1
valid_sources[0x32] 7139 1 T1 1 T15 2 T145 1
valid_sources[0x33] 6726 1 T20 1 T34 1 T36 11
valid_sources[0x34] 7518 1 T1 1 T3 1 T34 2
valid_sources[0x35] 7389 1 T20 1 T146 1 T148 1
valid_sources[0x36] 9055 1 T8 1 T20 1 T34 1
valid_sources[0x37] 7896 1 T2 67 T3 2 T20 2
valid_sources[0x38] 5968 1 T19 1 T14 1 T34 2
valid_sources[0x39] 6877 1 T20 4 T34 1 T145 1
valid_sources[0x3a] 7268 1 T1 1 T68 10 T34 1
valid_sources[0x3b] 7069 1 T3 1 T19 2 T20 2
valid_sources[0x3c] 7105 1 T20 1 T38 1 T145 2
valid_sources[0x3d] 6629 1 T34 1 T145 2 T144 1
valid_sources[0x3e] 6479 1 T1 1 T19 1 T43 8
valid_sources[0x3f] 6925 1 T3 1 T6 8 T8 2
valid_sources[0x40] 7522 1 T34 1 T145 1 T146 1
valid_sources[0x41] 6763 1 T3 2 T20 4 T83 2
valid_sources[0x42] 7290 1 T68 1 T15 12 T125 20
valid_sources[0x43] 6456 1 T3 1 T34 1 T144 1
valid_sources[0x44] 6540 1 T20 1 T34 3 T38 2
valid_sources[0x45] 6633 1 T20 1 T85 1 T144 4
valid_sources[0x46] 6991 1 T8 4 T145 3 T85 1
valid_sources[0x47] 6021 1 T20 3 T34 3 T31 1
valid_sources[0x48] 6738 1 T14 3 T20 1 T145 2
valid_sources[0x49] 8642 1 T144 4 T147 2 T149 3
valid_sources[0x4a] 7695 1 T6 12 T124 14 T34 1
valid_sources[0x4b] 7328 1 T20 1 T34 2 T84 5
valid_sources[0x4c] 9694 1 T1 1 T38 1 T145 3
valid_sources[0x4d] 7053 1 T20 1 T34 2 T145 1
valid_sources[0x4e] 8556 1 T20 1 T15 1 T83 1
valid_sources[0x4f] 7567 1 T20 4 T38 2 T145 4
valid_sources[0x50] 10156 1 T18 55 T20 2 T15 8
valid_sources[0x51] 5404 1 T1 1 T20 4 T34 3
valid_sources[0x52] 9524 1 T8 7 T15 1 T34 1
valid_sources[0x53] 8222 1 T34 3 T38 2 T145 3
valid_sources[0x54] 7148 1 T3 1 T20 1 T34 1
valid_sources[0x55] 7739 1 T20 4 T34 2 T38 4
valid_sources[0x56] 6601 1 T20 1 T34 1 T145 3
valid_sources[0x57] 6000 1 T19 2 T20 3 T145 2
valid_sources[0x58] 6899 1 T20 1 T83 1 T85 1
valid_sources[0x59] 7835 1 T1 1 T3 1 T145 2
valid_sources[0x5a] 7264 1 T1 1 T20 1 T38 2
valid_sources[0x5b] 7264 1 T3 2 T8 8 T34 1
valid_sources[0x5c] 5846 1 T18 60 T34 1 T145 2
valid_sources[0x5d] 6518 1 T1 2 T18 33 T19 6
valid_sources[0x5e] 8727 1 T3 1 T18 19 T20 1
valid_sources[0x5f] 6335 1 T1 2 T20 1 T34 1
valid_sources[0x60] 7339 1 T14 2 T20 2 T34 2
valid_sources[0x61] 7133 1 T8 1 T20 2 T34 1
valid_sources[0x62] 7924 1 T8 9 T19 2 T20 3
valid_sources[0x63] 8000 1 T20 2 T124 49 T38 1
valid_sources[0x64] 6328 1 T3 2 T19 3 T14 1
valid_sources[0x65] 8102 1 T3 1 T19 1 T34 1
valid_sources[0x66] 6527 1 T3 1 T20 2 T145 2
valid_sources[0x67] 6631 1 T20 3 T34 1 T31 4
valid_sources[0x68] 6857 1 T145 1 T43 8 T146 2
valid_sources[0x69] 7674 1 T14 3 T20 2 T15 2
valid_sources[0x6a] 7878 1 T1 1 T34 1 T38 2
valid_sources[0x6b] 7639 1 T17 18 T18 22 T20 1
valid_sources[0x6c] 6765 1 T6 1 T34 3 T144 2
valid_sources[0x6d] 6777 1 T34 1 T146 1 T147 2
valid_sources[0x6e] 7242 1 T18 33 T20 1 T34 1
valid_sources[0x6f] 8392 1 T20 1 T145 1 T144 1
valid_sources[0x70] 6164 1 T3 1 T83 1 T34 1
valid_sources[0x71] 6498 1 T1 1 T19 5 T68 1
valid_sources[0x72] 8079 1 T20 2 T31 4 T145 1
valid_sources[0x73] 7560 1 T145 1 T84 1 T144 1
valid_sources[0x74] 7954 1 T3 3 T34 1 T38 1
valid_sources[0x75] 6177 1 T20 1 T34 1 T38 1
valid_sources[0x76] 7537 1 T1 1 T3 3 T15 8
valid_sources[0x77] 6511 1 T2 22 T34 2 T143 1
valid_sources[0x78] 6225 1 T1 1 T20 1 T34 2
valid_sources[0x79] 7162 1 T18 18 T34 1 T145 3
valid_sources[0x7a] 5757 1 T3 2 T20 4 T38 4
valid_sources[0x7b] 7277 1 T3 2 T20 2 T34 1
valid_sources[0x7c] 7934 1 T6 2 T144 1 T86 1
valid_sources[0x7d] 6984 1 T20 2 T83 1 T34 1
valid_sources[0x7e] 7000 1 T34 1 T38 3 T31 2
valid_sources[0x7f] 7955 1 T20 2 T34 1 T38 1
valid_sources[0x80] 5588 1 T2 39 T14 2 T20 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 452575 1 T1 3 T2 30 T3 8
values[0x0] all_enables biggest_size 675823 1 T11 22752 T12 19417 T13 15791
values[0x1] all_enables biggest_size 674521 1 T11 22844 T12 19757 T13 15717


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 131949 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1394641 1 T1 7 T3 17 T4 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 376864 1 T1 16 T3 32 T5 1
values[0x0] 533631 1 T4 4 T10 6 T28 4
values[0x1] 616095 1 T4 1 T10 2 T28 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 58155 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1468435 1 T1 12 T3 17 T4 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 6114 1 T31 1 T43 2 T150 1
valid_sources[0x01] 5493 1 T151 6 T11 181 T12 162
valid_sources[0x02] 6532 1 T152 5 T42 1 T153 1
valid_sources[0x03] 6137 1 T31 1 T154 1 T155 1
valid_sources[0x04] 6255 1 T31 2 T86 1 T154 1
valid_sources[0x05] 5453 1 T30 1 T86 1 T41 1
valid_sources[0x06] 6625 1 T3 3 T22 1 T156 1
valid_sources[0x07] 6298 1 T15 5 T42 1 T157 1
valid_sources[0x08] 6033 1 T15 2 T47 3 T158 17
valid_sources[0x09] 6674 1 T31 1 T21 24 T86 1
valid_sources[0x0a] 6714 1 T159 1 T160 1 T161 1
valid_sources[0x0b] 6499 1 T86 2 T162 1 T11 245
valid_sources[0x0c] 6586 1 T163 1 T164 1 T111 1
valid_sources[0x0d] 5063 1 T157 1 T165 2 T105 1
valid_sources[0x0e] 4544 1 T166 7 T154 1 T155 1
valid_sources[0x0f] 4960 1 T66 1 T84 1 T157 1
valid_sources[0x10] 6488 1 T86 1 T167 4 T41 1
valid_sources[0x11] 6122 1 T31 1 T86 1 T42 2
valid_sources[0x12] 5852 1 T28 1 T86 1 T41 1
valid_sources[0x13] 6024 1 T110 1 T151 1 T11 218
valid_sources[0x14] 6182 1 T25 1 T168 1 T166 1
valid_sources[0x15] 5854 1 T25 1 T86 1 T159 1
valid_sources[0x16] 5807 1 T169 1 T157 1 T11 157
valid_sources[0x17] 5732 1 T31 2 T86 1 T33 1
valid_sources[0x18] 5901 1 T31 2 T22 1 T170 1
valid_sources[0x19] 5738 1 T6 4 T22 1 T43 6
valid_sources[0x1a] 5937 1 T171 1 T43 3 T157 1
valid_sources[0x1b] 6357 1 T10 2 T68 2 T172 2
valid_sources[0x1c] 7311 1 T23 1 T168 1 T173 1
valid_sources[0x1d] 5022 1 T42 1 T174 4 T156 3
valid_sources[0x1e] 6018 1 T150 1 T42 1 T47 1
valid_sources[0x1f] 6278 1 T153 1 T114 1 T175 1
valid_sources[0x20] 6019 1 T157 1 T176 13 T175 1
valid_sources[0x21] 5634 1 T66 2 T169 1 T157 1
valid_sources[0x22] 6037 1 T86 1 T177 10 T160 1
valid_sources[0x23] 6612 1 T31 1 T169 1 T178 1
valid_sources[0x24] 5762 1 T157 1 T153 1 T11 180
valid_sources[0x25] 5563 1 T114 1 T11 217 T12 136
valid_sources[0x26] 5754 1 T83 1 T150 4 T11 152
valid_sources[0x27] 6189 1 T31 1 T179 1 T180 1
valid_sources[0x28] 5807 1 T66 1 T86 1 T181 32
valid_sources[0x29] 4992 1 T182 1 T183 1 T164 1
valid_sources[0x2a] 6375 1 T86 1 T32 1 T160 2
valid_sources[0x2b] 6350 1 T43 5 T41 1 T165 1
valid_sources[0x2c] 6014 1 T6 2 T66 1 T162 2
valid_sources[0x2d] 7102 1 T86 1 T184 1 T110 2
valid_sources[0x2e] 6344 1 T185 1 T186 1 T187 2
valid_sources[0x2f] 6197 1 T83 1 T26 1 T180 1
valid_sources[0x30] 5913 1 T1 4 T86 2 T23 3
valid_sources[0x31] 5163 1 T6 4 T86 1 T180 1
valid_sources[0x32] 5674 1 T159 2 T114 1 T160 1
valid_sources[0x33] 5693 1 T185 1 T182 1 T188 64
valid_sources[0x34] 5471 1 T86 1 T32 2 T189 1
valid_sources[0x35] 6198 1 T182 1 T156 2 T190 3
valid_sources[0x36] 6049 1 T152 5 T47 2 T153 1
valid_sources[0x37] 5782 1 T31 3 T41 1 T180 3
valid_sources[0x38] 6218 1 T15 3 T86 1 T182 1
valid_sources[0x39] 5883 1 T45 1 T157 3 T156 2
valid_sources[0x3a] 5618 1 T3 1 T157 2 T46 1
valid_sources[0x3b] 5644 1 T15 2 T36 2 T152 6
valid_sources[0x3c] 5935 1 T4 5 T41 2 T191 2
valid_sources[0x3d] 5640 1 T169 2 T187 1 T110 1
valid_sources[0x3e] 5970 1 T31 1 T86 2 T153 1
valid_sources[0x3f] 6564 1 T31 1 T183 1 T189 1
valid_sources[0x40] 6168 1 T43 1 T168 1 T154 1
valid_sources[0x41] 5701 1 T3 1 T84 1 T192 2
valid_sources[0x42] 6836 1 T66 1 T15 1 T31 1
valid_sources[0x43] 5983 1 T23 10 T105 1 T160 1
valid_sources[0x44] 4956 1 T26 1 T87 64 T186 1
valid_sources[0x45] 5787 1 T179 1 T193 5 T183 2
valid_sources[0x46] 7454 1 T3 1 T36 3 T86 1
valid_sources[0x47] 5881 1 T66 1 T15 1 T47 1
valid_sources[0x48] 6464 1 T179 1 T47 3 T154 1
valid_sources[0x49] 6062 1 T3 1 T84 1 T86 2
valid_sources[0x4a] 6204 1 T6 2 T84 2 T41 1
valid_sources[0x4b] 6038 1 T83 1 T32 1 T157 1
valid_sources[0x4c] 6122 1 T3 3 T31 1 T153 1
valid_sources[0x4d] 5697 1 T15 3 T24 2 T43 1
valid_sources[0x4e] 5769 1 T32 1 T182 1 T47 2
valid_sources[0x4f] 6779 1 T152 5 T153 2 T194 1
valid_sources[0x50] 6006 1 T42 1 T190 1 T162 1
valid_sources[0x51] 6101 1 T83 2 T150 3 T157 1
valid_sources[0x52] 6761 1 T66 1 T86 1 T43 4
valid_sources[0x53] 5079 1 T66 1 T32 1 T153 1
valid_sources[0x54] 6207 1 T174 1 T157 2 T155 1
valid_sources[0x55] 6801 1 T3 1 T31 1 T192 1
valid_sources[0x56] 7296 1 T83 1 T31 1 T169 1
valid_sources[0x57] 5309 1 T68 1 T83 2 T41 2
valid_sources[0x58] 6410 1 T3 1 T43 4 T186 3
valid_sources[0x59] 5680 1 T169 2 T153 1 T183 1
valid_sources[0x5a] 5776 1 T3 1 T180 1 T154 2
valid_sources[0x5b] 5660 1 T5 1 T31 1 T180 1
valid_sources[0x5c] 6115 1 T66 1 T31 3 T44 1
valid_sources[0x5d] 6365 1 T185 1 T183 1 T110 1
valid_sources[0x5e] 6422 1 T26 1 T185 1 T180 1
valid_sources[0x5f] 6131 1 T195 10 T11 184 T12 438
valid_sources[0x60] 6813 1 T28 3 T150 2 T153 1
valid_sources[0x61] 6441 1 T114 1 T196 2 T162 2
valid_sources[0x62] 6308 1 T156 1 T151 3 T160 2
valid_sources[0x63] 5421 1 T66 1 T182 1 T164 1
valid_sources[0x64] 6882 1 T3 1 T197 1 T180 1
valid_sources[0x65] 5907 1 T25 2 T31 1 T86 1
valid_sources[0x66] 5728 1 T83 1 T41 1 T191 2
valid_sources[0x67] 5206 1 T1 2 T26 2 T31 2
valid_sources[0x68] 4776 1 T179 1 T162 1 T11 232
valid_sources[0x69] 5358 1 T47 4 T111 1 T162 1
valid_sources[0x6a] 6457 1 T106 1 T11 219 T12 702
valid_sources[0x6b] 5062 1 T66 1 T157 1 T198 1
valid_sources[0x6c] 6342 1 T31 1 T84 2 T199 1
valid_sources[0x6d] 5719 1 T33 2 T153 1 T200 1
valid_sources[0x6e] 5895 1 T74 3 T200 1 T164 2
valid_sources[0x6f] 5434 1 T31 1 T86 2 T168 1
valid_sources[0x70] 5968 1 T185 2 T153 1 T106 1
valid_sources[0x71] 5556 1 T22 2 T200 1 T155 1
valid_sources[0x72] 5420 1 T66 1 T183 3 T201 7
valid_sources[0x73] 5437 1 T153 1 T202 1 T162 1
valid_sources[0x74] 5785 1 T10 1 T72 1 T41 1
valid_sources[0x75] 6332 1 T28 1 T42 1 T153 1
valid_sources[0x76] 6953 1 T31 2 T183 3 T162 1
valid_sources[0x77] 6155 1 T10 1 T173 2 T172 3
valid_sources[0x78] 6032 1 T10 1 T15 4 T84 1
valid_sources[0x79] 6321 1 T15 1 T24 2 T86 1
valid_sources[0x7a] 6437 1 T26 3 T167 1 T154 1
valid_sources[0x7b] 5380 1 T16 1 T84 2 T152 7
valid_sources[0x7c] 5216 1 T14 16 T67 48 T31 1
valid_sources[0x7d] 5795 1 T41 1 T42 1 T153 1
valid_sources[0x7e] 5833 1 T10 1 T15 1 T32 3
valid_sources[0x7f] 6864 1 T33 4 T153 1 T156 2
valid_sources[0x80] 5693 1 T143 5 T41 1 T165 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 350419 1 T1 7 T3 17 T6 7
values[0x0] all_enables biggest_size 522850 1 T4 1 T10 3 T66 5
values[0x1] all_enables biggest_size 521372 1 T10 1 T28 1 T35 1