Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3358343

1

T1

39

T2

271

T3

67

full_word

2110745

1

T1

3

T2

30

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5468808	1			T1	42		T2	301		T3	75
auto[TlIntgErrCmd]	89	1			T63	4		T64	3		T65	3
auto[TlIntgErrData]	95	1			T63	7		T64	3		T65	3
auto[TlIntgErrBoth]	96	1			T63	9		T64	4		T65	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

848701

1

T1

42

T2

301

T3

75

auto[1]

4620387

1

T11

154429

T12

135644

T13

112047

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	351188	1			T1	39		T2	271		T3	67
auto[TlIntgErrNone]	partial	auto[1]	3006895	1			T11	100075		T12	88792		T13	73988
auto[TlIntgErrNone]	full_word	auto[0]	497397	1			T1	3		T2	30		T3	8
auto[TlIntgErrNone]	full_word	auto[1]	1613328	1			T11	54354		T12	46852		T13	38059
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T63	3		T65	1		T133	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T63	1		T64	2		T65	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T64	1		T135	1		T139	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T129	1		T130	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T63	3		T64	1		T65	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T63	4		T64	2		T65	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T138	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T140	1		T141	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T63	4		T64	2		T65	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T63	5		T64	2		T65	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T129	1		T135	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T65	2		T129	1		T142	1