ROM_CTRL/64KB Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.469m	59.822ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	39.910s	10.482ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	30.840s	13.964ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	33.200s	17.107ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.810s	4.193ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	30.560s	4.470ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	30.840s	13.964ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.810s	4.193ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	30.510s	15.047ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	24.960s	58.646ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.020s	8.974ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.838m	35.986ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.169m	117.116ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	32.670s	4.343ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	33.790s	3.599ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	33.790s	3.599ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	39.910s	10.482ms	5	5	100.00
		rom_ctrl_csr_rw	30.840s	13.964ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.810s	4.193ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.230s	28.342ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	39.910s	10.482ms	5	5	100.00
		rom_ctrl_csr_rw	30.840s	13.964ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.810s	4.193ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.230s	28.342ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.032m	23.138ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.868m	1.905ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.933m	33.840ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.868m	1.905ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.868m	1.905ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.868m	1.905ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.469m	59.822ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.469m	59.822ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.469m	59.822ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.933m	33.840ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
		rom_ctrl_kmac_err_chk	1.169m	117.116ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	20.273m	248.742ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.032m	23.138ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.868m	1.905ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.675h	45.613ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			452	500	90.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	4	66.67
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.50	96.97	93.01	97.88	100.00	98.37	97.88	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 32 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.39873957794121243589432461210626768338033508342953566068727398445721966231847
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107398949 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 107398949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.rom_ctrl_stress_all_with_rand_reset.47930609031028582441603717077214681904322332230211936339838104162534585042749
      Line 306, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7938700248 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7938700248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 30 more failures.

• Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 7 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.88326551140187678257966296426069430030351247204993755891481220536879300564952
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:ae251a95-6d71-411b-8709-6955e2830ee0
      

    • 4.rom_ctrl_stress_all_with_rand_reset.1207144411055900165839370117962361578402652962703530475081003370199003397933
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:1d08f08a-68a8-407d-a26a-8d0c823fea61
      

    • ... and 5 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

    • 3.rom_ctrl_stress_all_with_rand_reset.74782816061067175150239304968393787123251714264215615333994581766788012425935
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10011845558 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb356cbe7
        UVM_INFO @ 10011845558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.rom_ctrl_stress_all_with_rand_reset.3550647037440481890524253211237849752678277642145596578639924330152082441469
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10003871442 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe206595
        UVM_INFO @ 10003871442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 4.rom_ctrl_corrupt_sig_fatal_chk.84912915462555395400831875819666543697506481518977061697364128643111827388919
      Line 280, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 40354983859 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 40354983859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 16.rom_ctrl_kmac_err_chk.74099481587868463100685485151970181196655238858441676499725161170346995656108
      Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest/run.log

        UVM_ERROR @ 6594731064 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 6594731064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test rom_ctrl_smoke has 1 failures.

    • 16.rom_ctrl_smoke.36458444858786702617719415247598674813780770033063891290261645498931858388802
      Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_smoke/latest/run.log

        UVM_FATAL @ 40013159030 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa620833f
        UVM_INFO @ 40013159030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_stress_all has 1 failures.

    • 22.rom_ctrl_stress_all.104516107978565273937006982249087956719431276781866785758842640953835554689157
      Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 40022393377 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xccc7ed21
        UVM_INFO @ 40022393377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 41.rom_ctrl_corrupt_sig_fatal_chk.104170477343510435475235610856459393128116094648726500743718403430720909193227
      Line 305, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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