Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1525517

1

T2

187

T3

81

T6

53

full_word

970680

1

T2

11

T3

8

T5

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2495937	1			T2	198		T3	89		T5	2
auto[TlIntgErrCmd]	86	1			T50	1		T52	4		T53	6
auto[TlIntgErrData]	84	1			T50	3		T52	3		T53	8
auto[TlIntgErrBoth]	90	1			T50	6		T52	3		T53	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

404418

1

T2

198

T3

89

T5

2

auto[1]

2091779

1

T7

242549

T13

89642

T18

380269

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	174530	1			T2	187		T3	81		T6	53
auto[TlIntgErrNone]	partial	auto[1]	1350744	1			T7	158386		T13	58898		T18	242521
auto[TlIntgErrNone]	full_word	auto[0]	229781	1			T2	11		T3	8		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	740882	1			T7	84163		T13	30744		T18	137748
auto[TlIntgErrCmd]	partial	auto[0]	28	1			T52	1		T53	3		T103	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T50	1		T52	2		T53	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T104	1		T109	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T52	1		T102	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T50	2		T52	2		T53	3
auto[TlIntgErrData]	partial	auto[1]	36	1			T50	1		T52	1		T53	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T110	1		T105	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T102	1		T108	1		T111	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T50	2		T52	1		T53	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T50	3		T52	2		T53	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T50	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T53	1		T112	1		T113	1