Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1767254

1

T2

213

T5

76

T6

57

full_word

1141676

1

T2

28

T5

14

T6

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2908640	1			T2	241		T5	90		T6	63
auto[TlIntgErrCmd]	97	1			T64	6		T65	4		T66	5
auto[TlIntgErrData]	100	1			T64	8		T65	4		T66	5
auto[TlIntgErrBoth]	93	1			T64	6		T65	2		T66	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

471080

1

T2

241

T5

90

T6

63

auto[1]

2437850

1

T12

181106

T18

308785

T19

104619

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	200673	1			T2	213		T5	76		T6	57
auto[TlIntgErrNone]	partial	auto[1]	1566312	1			T12	116332		T18	198233		T19	69703
auto[TlIntgErrNone]	full_word	auto[0]	270285	1			T2	28		T5	14		T6	6
auto[TlIntgErrNone]	full_word	auto[1]	871370	1			T12	64774		T18	110552		T19	34916
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T64	2		T118	1		T119	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T64	2		T65	3		T66	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T119	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T64	2		T65	1		T66	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T64	3		T65	4		T66	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T64	5		T66	3		T119	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T118	1		T121	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T122	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T64	3		T66	3		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T64	3		T65	2		T66	7
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T118	1		T122	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T122	2		T121	1		T129	1