Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

470122

1

T1

6

T2

20

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143253	1			T1	6		T2	219		T6	3
values[0x0]	177276	1			T17	11981		T18	8291		T19	35626
values[0x1]	183694	1			T17	12159		T18	8674		T19	36806

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16625	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

487598

1

T1

6

T2

134

T6

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1976	1			T13	2		T137	1		T49	6
valid_sources[0x01]	1656	1			T10	14		T137	1		T49	1
valid_sources[0x02]	1451	1			T137	3		T138	1		T139	3
valid_sources[0x03]	1696	1			T8	1		T137	1		T138	1
valid_sources[0x04]	1872	1			T20	1		T89	1		T14	1
valid_sources[0x05]	1721	1			T89	2		T137	1		T138	3
valid_sources[0x06]	1348	1			T12	23		T13	4		T137	1
valid_sources[0x07]	3191	1			T12	7		T13	1		T137	2
valid_sources[0x08]	2048	1			T137	2		T138	2		T139	2
valid_sources[0x09]	1256	1			T137	1		T49	1		T140	1
valid_sources[0x0a]	1532	1			T21	8		T137	1		T138	2
valid_sources[0x0b]	1863	1			T22	1		T123	14		T89	1
valid_sources[0x0c]	2266	1			T141	2		T137	1		T139	1
valid_sources[0x0d]	1934	1			T8	1		T20	1		T13	4
valid_sources[0x0e]	1440	1			T2	7		T8	1		T137	1
valid_sources[0x0f]	2615	1			T137	2		T139	2		T45	1
valid_sources[0x10]	2528	1			T142	9		T143	1		T17	128
valid_sources[0x11]	1644	1			T89	1		T137	2		T138	1
valid_sources[0x12]	1602	1			T90	4		T137	1		T138	2
valid_sources[0x13]	1394	1			T66	1		T89	2		T137	1
valid_sources[0x14]	1304	1			T20	2		T137	1		T49	1
valid_sources[0x15]	1228	1			T122	58		T138	2		T49	1
valid_sources[0x16]	2245	1			T141	1		T137	1		T49	1
valid_sources[0x17]	2213	1			T8	2		T66	1		T137	2
valid_sources[0x18]	2084	1			T20	1		T13	2		T66	1
valid_sources[0x19]	2390	1			T9	4		T138	1		T139	2
valid_sources[0x1a]	2516	1			T122	13		T89	3		T144	4
valid_sources[0x1b]	1557	1			T22	2		T141	4		T138	2
valid_sources[0x1c]	2122	1			T2	5		T13	2		T66	1
valid_sources[0x1d]	1399	1			T2	5		T138	2		T49	2
valid_sources[0x1e]	2133	1			T1	1		T8	1		T13	1
valid_sources[0x1f]	2624	1			T20	1		T123	2		T89	4
valid_sources[0x20]	1866	1			T66	1		T89	2		T139	1
valid_sources[0x21]	1497	1			T8	4		T66	1		T49	1
valid_sources[0x22]	1635	1			T145	15		T89	5		T14	1
valid_sources[0x23]	2406	1			T13	1		T137	1		T140	1
valid_sources[0x24]	1302	1			T8	3		T89	3		T137	1
valid_sources[0x25]	1649	1			T141	1		T137	2		T138	2
valid_sources[0x26]	1730	1			T2	24		T8	5		T10	31
valid_sources[0x27]	2256	1			T20	2		T89	2		T141	4
valid_sources[0x28]	1506	1			T89	1		T141	3		T139	5
valid_sources[0x29]	1530	1			T20	1		T138	3		T49	1
valid_sources[0x2a]	1296	1			T20	1		T89	6		T137	1
valid_sources[0x2b]	1679	1			T66	1		T137	1		T138	2
valid_sources[0x2c]	1956	1			T123	5		T13	1		T137	1
valid_sources[0x2d]	2421	1			T9	1		T123	1		T139	2
valid_sources[0x2e]	2300	1			T22	1		T137	2		T138	2
valid_sources[0x2f]	3101	1			T21	7		T122	19		T137	2
valid_sources[0x30]	1337	1			T21	3		T123	1		T13	2
valid_sources[0x31]	1532	1			T2	12		T8	2		T90	1
valid_sources[0x32]	1563	1			T8	2		T137	2		T49	1
valid_sources[0x33]	1931	1			T2	5		T20	1		T66	1
valid_sources[0x34]	1736	1			T2	5		T20	1		T137	1
valid_sources[0x35]	2136	1			T8	2		T66	1		T137	2
valid_sources[0x36]	2775	1			T20	2		T89	3		T138	2
valid_sources[0x37]	2718	1			T8	3		T138	1		T49	2
valid_sources[0x38]	1600	1			T139	1		T146	1		T147	2
valid_sources[0x39]	3217	1			T8	4		T21	1		T49	1
valid_sources[0x3a]	2592	1			T40	1		T123	2		T14	3
valid_sources[0x3b]	1914	1			T8	1		T13	1		T49	2
valid_sources[0x3c]	2017	1			T8	2		T20	1		T13	1
valid_sources[0x3d]	1294	1			T20	1		T123	2		T141	2
valid_sources[0x3e]	2307	1			T8	2		T9	2		T13	7
valid_sources[0x3f]	2282	1			T14	3		T49	5		T146	1
valid_sources[0x40]	2314	1			T8	3		T21	9		T49	1
valid_sources[0x41]	2040	1			T2	8		T21	4		T13	1
valid_sources[0x42]	1372	1			T49	2		T140	1		T91	2
valid_sources[0x43]	1784	1			T8	2		T90	1		T141	2
valid_sources[0x44]	1802	1			T14	2		T137	2		T138	1
valid_sources[0x45]	2043	1			T9	1		T20	2		T15	1
valid_sources[0x46]	2972	1			T139	1		T43	5		T93	1
valid_sources[0x47]	1282	1			T123	2		T66	1		T138	2
valid_sources[0x48]	1736	1			T137	2		T138	2		T49	4
valid_sources[0x49]	1790	1			T8	1		T137	1		T42	3
valid_sources[0x4a]	1684	1			T2	4		T8	1		T13	1
valid_sources[0x4b]	1506	1			T2	3		T137	2		T138	1
valid_sources[0x4c]	1963	1			T14	2		T137	1		T49	1
valid_sources[0x4d]	1777	1			T90	1		T137	2		T139	3
valid_sources[0x4e]	2567	1			T20	1		T137	1		T138	2
valid_sources[0x4f]	2562	1			T8	3		T12	5		T14	1
valid_sources[0x50]	1832	1			T8	1		T21	1		T89	3
valid_sources[0x51]	2597	1			T137	2		T49	2		T91	1
valid_sources[0x52]	1674	1			T13	1		T139	2		T49	2
valid_sources[0x53]	1425	1			T8	3		T22	8		T137	2
valid_sources[0x54]	2987	1			T2	8		T20	1		T22	1
valid_sources[0x55]	1817	1			T138	2		T139	2		T92	1
valid_sources[0x56]	2321	1			T2	25		T66	1		T139	4
valid_sources[0x57]	2011	1			T137	2		T139	6		T49	4
valid_sources[0x58]	1778	1			T8	1		T20	3		T138	1
valid_sources[0x59]	1497	1			T8	4		T21	4		T13	2
valid_sources[0x5a]	1379	1			T8	4		T9	1		T123	1
valid_sources[0x5b]	1568	1			T123	1		T89	1		T137	1
valid_sources[0x5c]	1533	1			T66	1		T14	1		T137	1
valid_sources[0x5d]	1681	1			T13	1		T66	1		T137	1
valid_sources[0x5e]	1762	1			T2	1		T123	1		T89	4
valid_sources[0x5f]	2104	1			T2	10		T139	1		T148	33
valid_sources[0x60]	1322	1			T14	3		T139	4		T49	1
valid_sources[0x61]	1815	1			T21	2		T137	1		T138	1
valid_sources[0x62]	2509	1			T8	5		T9	1		T13	1
valid_sources[0x63]	2000	1			T8	2		T20	3		T21	5
valid_sources[0x64]	1326	1			T22	1		T12	7		T89	1
valid_sources[0x65]	1311	1			T138	2		T139	2		T49	2
valid_sources[0x66]	1749	1			T8	2		T13	1		T90	2
valid_sources[0x67]	2483	1			T8	4		T20	1		T41	2
valid_sources[0x68]	1487	1			T139	2		T144	6		T91	1
valid_sources[0x69]	2022	1			T89	1		T137	2		T138	1
valid_sources[0x6a]	1841	1			T90	1		T138	3		T49	1
valid_sources[0x6b]	1341	1			T141	2		T137	1		T49	3
valid_sources[0x6c]	2504	1			T2	8		T20	1		T66	1
valid_sources[0x6d]	1407	1			T8	1		T89	1		T14	4
valid_sources[0x6e]	1483	1			T22	1		T138	2		T91	1
valid_sources[0x6f]	2584	1			T9	2		T66	1		T149	41
valid_sources[0x70]	2306	1			T10	60		T22	4		T66	1
valid_sources[0x71]	1422	1			T22	2		T89	1		T90	2
valid_sources[0x72]	1384	1			T13	4		T66	1		T89	6
valid_sources[0x73]	1442	1			T2	8		T90	1		T49	1
valid_sources[0x74]	1641	1			T138	3		T139	2		T91	1
valid_sources[0x75]	2868	1			T12	2		T13	2		T137	1
valid_sources[0x76]	2399	1			T66	1		T89	2		T137	1
valid_sources[0x77]	1995	1			T2	1		T8	1		T138	2
valid_sources[0x78]	1557	1			T139	3		T91	1		T17	135
valid_sources[0x79]	1833	1			T13	1		T138	1		T49	1
valid_sources[0x7a]	1320	1			T22	1		T90	1		T137	1
valid_sources[0x7b]	2467	1			T90	2		T138	1		T139	2
valid_sources[0x7c]	1744	1			T89	2		T137	1		T150	1
valid_sources[0x7d]	1934	1			T2	1		T137	1		T150	1
valid_sources[0x7e]	2683	1			T2	5		T8	1		T20	1
valid_sources[0x7f]	2309	1			T123	5		T90	2		T137	1
valid_sources[0x80]	1497	1			T2	1		T8	2		T9	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

119116

1

T1

6

T2

20

T6

3

values[0x0]

all_enables

biggest_size

175661

1

T17

11881

T18

8247

T19

35297

values[0x1]

all_enables

biggest_size

175345

1

T17

11672

T18

8331

T19

35101

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

383847

1

T1

6

T2

43

T4

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	109896	1			T1	15		T2	96		T3	1
values[0x0]	146303	1			T5	3		T7	5		T26	2
values[0x1]	169112	1			T7	1		T70	5		T71	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20202	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

405109

1

T1

7

T2

57

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1773	1			T8	2		T17	97		T57	1
valid_sources[0x01]	1556	1			T20	1		T11	1		T151	1
valid_sources[0x02]	1596	1			T8	1		T15	3		T90	1
valid_sources[0x03]	1712	1			T2	4		T13	1		T66	32
valid_sources[0x04]	1731	1			T10	96		T145	1		T17	83
valid_sources[0x05]	1637	1			T12	1		T13	2		T140	1
valid_sources[0x06]	1565	1			T20	2		T16	1		T144	1
valid_sources[0x07]	1530	1			T17	76		T63	1		T64	1
valid_sources[0x08]	1819	1			T11	1		T40	28		T26	1
valid_sources[0x09]	1600	1			T123	7		T93	1		T152	3
valid_sources[0x0a]	1800	1			T8	1		T123	1		T145	1
valid_sources[0x0b]	1801	1			T43	1		T140	1		T92	1
valid_sources[0x0c]	1652	1			T73	9		T151	1		T153	1
valid_sources[0x0d]	1578	1			T8	1		T154	5		T17	117
valid_sources[0x0e]	1776	1			T1	1		T2	1		T8	2
valid_sources[0x0f]	1717	1			T1	1		T8	1		T11	1
valid_sources[0x10]	1644	1			T8	1		T145	2		T144	2
valid_sources[0x11]	1628	1			T155	2		T143	3		T152	1
valid_sources[0x12]	1660	1			T15	1		T150	1		T153	1
valid_sources[0x13]	1740	1			T75	4		T43	1		T152	2
valid_sources[0x14]	1925	1			T8	1		T93	2		T150	1
valid_sources[0x15]	1839	1			T93	1		T17	124		T18	98
valid_sources[0x16]	1734	1			T2	1		T11	2		T145	1
valid_sources[0x17]	1632	1			T4	2		T123	1		T145	1
valid_sources[0x18]	1639	1			T20	1		T39	1		T26	1
valid_sources[0x19]	1749	1			T4	1		T8	1		T145	1
valid_sources[0x1a]	1601	1			T149	7		T17	120		T110	23
valid_sources[0x1b]	1570	1			T90	1		T17	84		T63	1
valid_sources[0x1c]	1846	1			T13	1		T156	18		T152	3
valid_sources[0x1d]	1641	1			T4	1		T145	1		T144	1
valid_sources[0x1e]	1514	1			T39	2		T75	5		T149	2
valid_sources[0x1f]	1677	1			T157	1		T152	1		T158	1
valid_sources[0x20]	1610	1			T157	1		T150	1		T152	2
valid_sources[0x21]	1576	1			T2	5		T123	1		T144	2
valid_sources[0x22]	1563	1			T145	1		T89	2		T149	1
valid_sources[0x23]	1637	1			T8	1		T92	1		T17	154
valid_sources[0x24]	1608	1			T1	1		T8	2		T149	4
valid_sources[0x25]	1990	1			T8	2		T20	3		T15	1
valid_sources[0x26]	1650	1			T1	1		T8	1		T93	1
valid_sources[0x27]	1781	1			T2	7		T21	1		T144	1
valid_sources[0x28]	1740	1			T4	1		T123	2		T13	1
valid_sources[0x29]	1897	1			T136	1		T92	1		T150	1
valid_sources[0x2a]	1720	1			T2	1		T144	1		T17	116
valid_sources[0x2b]	1745	1			T8	1		T39	1		T12	5
valid_sources[0x2c]	1611	1			T2	1		T21	1		T39	2
valid_sources[0x2d]	1814	1			T2	6		T4	2		T11	1
valid_sources[0x2e]	1801	1			T11	1		T12	8		T15	2
valid_sources[0x2f]	1866	1			T4	1		T21	1		T12	2
valid_sources[0x30]	1595	1			T20	1		T17	88		T159	1
valid_sources[0x31]	1513	1			T144	1		T146	3		T17	110
valid_sources[0x32]	1565	1			T1	1		T21	1		T140	3
valid_sources[0x33]	1579	1			T21	1		T144	1		T150	1
valid_sources[0x34]	1623	1			T17	130		T107	1		T112	1
valid_sources[0x35]	1596	1			T2	1		T11	1		T72	1
valid_sources[0x36]	1527	1			T1	1		T20	2		T13	1
valid_sources[0x37]	1584	1			T123	1		T89	2		T93	1
valid_sources[0x38]	1675	1			T144	1		T92	1		T160	2
valid_sources[0x39]	1828	1			T4	1		T8	1		T39	3
valid_sources[0x3a]	1663	1			T75	3		T158	1		T17	118
valid_sources[0x3b]	1576	1			T11	1		T43	1		T17	143
valid_sources[0x3c]	1603	1			T8	1		T161	1		T90	2
valid_sources[0x3d]	1911	1			T2	4		T74	1		T17	128
valid_sources[0x3e]	1840	1			T8	1		T9	11		T15	1
valid_sources[0x3f]	1737	1			T1	1		T8	1		T20	3
valid_sources[0x40]	1697	1			T21	1		T92	1		T152	1
valid_sources[0x41]	1578	1			T71	1		T89	4		T151	3
valid_sources[0x42]	1498	1			T4	2		T20	3		T21	1
valid_sources[0x43]	1703	1			T15	1		T92	1		T17	108
valid_sources[0x44]	1521	1			T8	1		T11	1		T17	76
valid_sources[0x45]	1462	1			T11	1		T143	3		T17	75
valid_sources[0x46]	1635	1			T8	1		T149	1		T150	1
valid_sources[0x47]	1660	1			T71	1		T43	2		T140	1
valid_sources[0x48]	1717	1			T4	1		T123	1		T145	1
valid_sources[0x49]	1617	1			T8	1		T15	1		T144	1
valid_sources[0x4a]	1550	1			T4	2		T39	2		T89	2
valid_sources[0x4b]	1820	1			T162	23		T158	1		T17	119
valid_sources[0x4c]	1651	1			T90	1		T155	1		T17	122
valid_sources[0x4d]	1660	1			T146	1		T152	1		T17	118
valid_sources[0x4e]	1664	1			T8	1		T15	1		T13	1
valid_sources[0x4f]	1545	1			T39	1		T163	1		T149	2
valid_sources[0x50]	1612	1			T2	1		T158	1		T17	127
valid_sources[0x51]	1533	1			T2	4		T155	1		T17	85
valid_sources[0x52]	1604	1			T70	1		T43	4		T17	111
valid_sources[0x53]	1615	1			T15	1		T144	1		T93	1
valid_sources[0x54]	1592	1			T6	1		T145	1		T152	2
valid_sources[0x55]	1470	1			T8	1		T20	1		T150	1
valid_sources[0x56]	1831	1			T21	1		T158	1		T17	109
valid_sources[0x57]	1821	1			T1	1		T8	1		T90	1
valid_sources[0x58]	1587	1			T21	1		T11	1		T93	1
valid_sources[0x59]	1481	1			T8	1		T20	1		T164	1
valid_sources[0x5a]	1678	1			T4	1		T21	1		T145	1
valid_sources[0x5b]	1630	1			T4	1		T8	1		T140	1
valid_sources[0x5c]	1715	1			T146	7		T17	84		T57	2
valid_sources[0x5d]	1777	1			T2	1		T144	1		T17	116
valid_sources[0x5e]	1620	1			T4	4		T140	1		T93	1
valid_sources[0x5f]	1527	1			T70	1		T144	1		T150	1
valid_sources[0x60]	1548	1			T8	1		T21	1		T123	3
valid_sources[0x61]	1687	1			T4	1		T71	1		T143	2
valid_sources[0x62]	1718	1			T8	1		T154	3		T160	1
valid_sources[0x63]	1661	1			T72	1		T41	36		T145	1
valid_sources[0x64]	1547	1			T11	1		T145	1		T93	2
valid_sources[0x65]	1570	1			T1	1		T93	1		T150	1
valid_sources[0x66]	1638	1			T158	1		T17	135		T64	2
valid_sources[0x67]	1647	1			T8	1		T145	1		T151	2
valid_sources[0x68]	1578	1			T4	2		T71	1		T17	106
valid_sources[0x69]	1710	1			T13	2		T145	1		T140	1
valid_sources[0x6a]	1638	1			T8	1		T21	1		T145	1
valid_sources[0x6b]	1592	1			T136	1		T153	1		T17	88
valid_sources[0x6c]	1626	1			T8	1		T152	1		T165	1
valid_sources[0x6d]	1639	1			T8	1		T70	1		T90	1
valid_sources[0x6e]	1870	1			T2	1		T146	1		T152	1
valid_sources[0x6f]	1682	1			T20	1		T144	1		T166	3
valid_sources[0x70]	1547	1			T2	1		T20	1		T152	1
valid_sources[0x71]	1832	1			T89	3		T144	1		T160	4
valid_sources[0x72]	1517	1			T70	1		T145	2		T144	1
valid_sources[0x73]	1645	1			T70	1		T90	1		T144	1
valid_sources[0x74]	1820	1			T21	1		T43	1		T17	117
valid_sources[0x75]	2115	1			T152	4		T17	107		T64	1
valid_sources[0x76]	1591	1			T2	5		T21	1		T93	2
valid_sources[0x77]	1673	1			T136	1		T91	64		T45	6
valid_sources[0x78]	1576	1			T152	3		T158	1		T17	116
valid_sources[0x79]	1504	1			T8	1		T92	1		T45	2
valid_sources[0x7a]	1757	1			T123	2		T45	1		T166	3
valid_sources[0x7b]	1640	1			T4	1		T149	2		T144	1
valid_sources[0x7c]	1597	1			T145	1		T144	2		T158	1
valid_sources[0x7d]	1670	1			T8	1		T90	1		T167	3
valid_sources[0x7e]	1477	1			T21	1		T45	7		T17	68
valid_sources[0x7f]	1611	1			T15	1		T144	3		T140	1
valid_sources[0x80]	1641	1			T166	1		T17	153		T64	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97644

1

T1

6

T2

43

T4

18

values[0x0]

all_enables

biggest_size

143038

1

T5

1

T7

4

T26

1

values[0x1]

all_enables

biggest_size

143165

1

T70

1

T71

1

T75

3