Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

893115

1

T2

199

T8

124

T9

62

full_word

550346

1

T1

4

T2

20

T6

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1443181	1			T1	4		T2	219		T6	2
auto[TlIntgErrCmd]	93	1			T54	7		T55	3		T56	2
auto[TlIntgErrData]	104	1			T54	5		T55	3		T56	4
auto[TlIntgErrBoth]	83	1			T54	8		T55	4		T56	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241475

1

T1

4

T2

219

T6

2

auto[1]

1201986

1

T17

79094

T18

53157

T19

243019

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	110671	1			T2	199		T8	124		T9	62
auto[TlIntgErrNone]	partial	auto[1]	782189	1			T17	50944		T18	33615		T19	158897
auto[TlIntgErrNone]	full_word	auto[0]	130682	1			T1	4		T2	20		T6	2
auto[TlIntgErrNone]	full_word	auto[1]	419639	1			T17	28150		T18	19542		T19	84122
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T54	2		T55	3		T56	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T54	5		T56	1		T80	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T130	1		T131	1		T132	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T125	2		T130	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T54	3		T55	1		T80	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T55	2		T56	2		T80	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T80	1		T127	2		T133	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T54	2		T56	2		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T54	5		T55	1		T56	2
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T54	3		T55	3		T56	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T128	1		T135	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T80	1		-	-		-	-