Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30842 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 289949 1 T2 23 T3 6 T4 6



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 99246 1 T2 233 T3 6 T4 6
values[0x0] 109077 1 T17 31938 T18 28501 T19 14795
values[0x1] 112468 1 T17 32505 T18 29461 T19 15387



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 14471 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 306320 1 T2 138 T3 6 T4 6



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 949 1 T8 2 T13 1 T137 1
valid_sources[0x01] 1145 1 T6 2 T8 2 T137 1
valid_sources[0x02] 1410 1 T8 1 T13 6 T65 1
valid_sources[0x03] 1647 1 T6 3 T8 3 T88 2
valid_sources[0x04] 1062 1 T6 1 T8 2 T23 1
valid_sources[0x05] 1093 1 T23 1 T138 1 T89 3
valid_sources[0x06] 1205 1 T2 11 T65 1 T89 2
valid_sources[0x07] 1413 1 T8 9 T65 2 T138 1
valid_sources[0x08] 1105 1 T8 2 T20 1 T122 4
valid_sources[0x09] 1527 1 T8 3 T20 2 T13 2
valid_sources[0x0a] 944 1 T8 2 T65 3 T139 2
valid_sources[0x0b] 1691 1 T6 1 T23 1 T73 6
valid_sources[0x0c] 1693 1 T2 16 T8 1 T9 1
valid_sources[0x0d] 985 1 T6 2 T22 3 T64 15
valid_sources[0x0e] 1591 1 T8 2 T140 20 T141 4
valid_sources[0x0f] 997 1 T8 1 T88 1 T65 1
valid_sources[0x10] 981 1 T8 1 T88 1 T65 2
valid_sources[0x11] 909 1 T6 1 T8 1 T88 1
valid_sources[0x12] 1125 1 T2 33 T8 2 T23 1
valid_sources[0x13] 1872 1 T3 6 T23 2 T122 3
valid_sources[0x14] 1025 1 T142 7 T88 1 T65 1
valid_sources[0x15] 1279 1 T8 1 T142 1 T13 1
valid_sources[0x16] 1107 1 T8 1 T88 1 T137 1
valid_sources[0x17] 1622 1 T6 1 T8 2 T142 1
valid_sources[0x18] 933 1 T7 1 T8 1 T20 1
valid_sources[0x19] 1241 1 T6 1 T88 1 T65 1
valid_sources[0x1a] 1976 1 T8 3 T88 1 T137 1
valid_sources[0x1b] 1069 1 T8 1 T73 1 T88 1
valid_sources[0x1c] 1016 1 T4 6 T8 1 T23 1
valid_sources[0x1d] 983 1 T142 3 T65 2 T89 1
valid_sources[0x1e] 903 1 T8 2 T13 1 T88 1
valid_sources[0x1f] 1234 1 T6 1 T8 3 T20 2
valid_sources[0x20] 887 1 T8 3 T20 1 T140 10
valid_sources[0x21] 1223 1 T6 1 T8 3 T88 1
valid_sources[0x22] 1869 1 T6 1 T8 2 T39 2
valid_sources[0x23] 985 1 T8 1 T22 1 T137 1
valid_sources[0x24] 981 1 T20 1 T13 1 T88 1
valid_sources[0x25] 2404 1 T6 1 T20 1 T88 1
valid_sources[0x26] 1273 1 T6 3 T20 1 T137 1
valid_sources[0x27] 1005 1 T6 1 T8 2 T73 6
valid_sources[0x28] 1036 1 T8 2 T138 1 T141 1
valid_sources[0x29] 1026 1 T143 5 T144 3 T141 1
valid_sources[0x2a] 1261 1 T20 1 T23 2 T88 1
valid_sources[0x2b] 1073 1 T6 1 T8 2 T23 1
valid_sources[0x2c] 1235 1 T6 1 T23 1 T21 1
valid_sources[0x2d] 833 1 T6 1 T8 1 T23 1
valid_sources[0x2e] 1234 1 T6 2 T8 1 T10 2
valid_sources[0x2f] 1253 1 T6 1 T8 3 T22 1
valid_sources[0x30] 1817 1 T65 3 T143 4 T89 1
valid_sources[0x31] 943 1 T8 1 T73 1 T22 4
valid_sources[0x32] 839 1 T6 1 T7 1 T8 3
valid_sources[0x33] 1550 1 T88 3 T139 5 T89 2
valid_sources[0x34] 1328 1 T8 1 T21 8 T22 1
valid_sources[0x35] 1135 1 T8 2 T89 2 T145 1
valid_sources[0x36] 1340 1 T6 2 T88 2 T65 2
valid_sources[0x37] 899 1 T6 3 T8 1 T137 1
valid_sources[0x38] 973 1 T6 2 T8 1 T142 4
valid_sources[0x39] 1622 1 T8 4 T65 2 T137 2
valid_sources[0x3a] 1324 1 T6 1 T8 1 T23 1
valid_sources[0x3b] 1018 1 T6 1 T8 3 T13 1
valid_sources[0x3c] 1141 1 T8 2 T20 1 T65 1
valid_sources[0x3d] 1283 1 T8 3 T88 1 T65 2
valid_sources[0x3e] 924 1 T88 1 T65 1 T137 1
valid_sources[0x3f] 1440 1 T8 3 T23 2 T138 1
valid_sources[0x40] 1159 1 T6 1 T8 1 T23 4
valid_sources[0x41] 985 1 T8 3 T136 1 T139 6
valid_sources[0x42] 1249 1 T137 2 T89 1 T144 1
valid_sources[0x43] 975 1 T2 1 T8 1 T13 1
valid_sources[0x44] 1099 1 T73 1 T146 4 T138 1
valid_sources[0x45] 1865 1 T8 1 T142 1 T13 1
valid_sources[0x46] 1602 1 T8 1 T23 1 T22 2
valid_sources[0x47] 942 1 T6 1 T8 2 T13 2
valid_sources[0x48] 1054 1 T6 1 T8 2 T65 1
valid_sources[0x49] 944 1 T8 1 T65 2 T146 1
valid_sources[0x4a] 1349 1 T8 2 T23 1 T73 1
valid_sources[0x4b] 939 1 T2 4 T6 1 T8 1
valid_sources[0x4c] 913 1 T6 1 T8 3 T88 1
valid_sources[0x4d] 2078 1 T6 1 T8 5 T23 2
valid_sources[0x4e] 1538 1 T8 2 T65 1 T137 2
valid_sources[0x4f] 1481 1 T6 1 T8 1 T20 1
valid_sources[0x50] 1632 1 T142 1 T32 2 T36 1
valid_sources[0x51] 1875 1 T6 1 T8 2 T65 3
valid_sources[0x52] 893 1 T6 1 T88 1 T65 1
valid_sources[0x53] 983 1 T142 1 T13 1 T65 2
valid_sources[0x54] 1565 1 T8 1 T10 1 T73 4
valid_sources[0x55] 1124 1 T13 4 T140 26 T65 1
valid_sources[0x56] 974 1 T8 1 T20 1 T88 1
valid_sources[0x57] 960 1 T8 1 T65 3 T137 1
valid_sources[0x58] 872 1 T8 2 T142 1 T88 2
valid_sources[0x59] 941 1 T6 2 T22 3 T88 2
valid_sources[0x5a] 1082 1 T6 1 T8 1 T88 2
valid_sources[0x5b] 1111 1 T6 1 T8 2 T20 1
valid_sources[0x5c] 999 1 T8 4 T23 3 T142 4
valid_sources[0x5d] 1908 1 T20 1 T23 1 T89 2
valid_sources[0x5e] 958 1 T6 2 T8 1 T13 2
valid_sources[0x5f] 1526 1 T8 1 T12 14 T65 1
valid_sources[0x60] 927 1 T6 1 T7 1 T8 1
valid_sources[0x61] 920 1 T8 1 T65 2 T137 1
valid_sources[0x62] 1019 1 T6 2 T20 1 T137 2
valid_sources[0x63] 1051 1 T8 3 T73 2 T14 1
valid_sources[0x64] 1206 1 T8 4 T13 1 T88 2
valid_sources[0x65] 1859 1 T8 2 T23 2 T142 2
valid_sources[0x66] 1185 1 T6 2 T142 1 T13 7
valid_sources[0x67] 936 1 T6 2 T13 3 T88 1
valid_sources[0x68] 1446 1 T8 2 T21 3 T142 1
valid_sources[0x69] 943 1 T8 1 T138 1 T139 2
valid_sources[0x6a] 1015 1 T8 1 T23 1 T13 2
valid_sources[0x6b] 880 1 T23 1 T22 3 T138 1
valid_sources[0x6c] 1149 1 T2 20 T8 1 T73 2
valid_sources[0x6d] 1478 1 T6 1 T8 1 T42 6
valid_sources[0x6e] 1391 1 T6 1 T8 1 T142 3
valid_sources[0x6f] 2046 1 T8 1 T23 1 T13 1
valid_sources[0x70] 1070 1 T6 2 T139 18 T147 1
valid_sources[0x71] 848 1 T20 1 T73 5 T88 1
valid_sources[0x72] 1670 1 T2 12 T8 1 T20 2
valid_sources[0x73] 1506 1 T6 1 T8 1 T73 6
valid_sources[0x74] 909 1 T6 1 T8 2 T137 2
valid_sources[0x75] 1000 1 T6 1 T22 4 T65 2
valid_sources[0x76] 1356 1 T8 4 T20 1 T137 5
valid_sources[0x77] 942 1 T65 1 T138 1 T139 7
valid_sources[0x78] 1540 1 T8 1 T13 1 T137 1
valid_sources[0x79] 947 1 T6 2 T122 10 T13 1
valid_sources[0x7a] 982 1 T22 14 T12 22 T65 1
valid_sources[0x7b] 974 1 T8 4 T73 13 T122 2
valid_sources[0x7c] 913 1 T6 1 T8 2 T21 19
valid_sources[0x7d] 981 1 T6 1 T8 1 T20 1
valid_sources[0x7e] 1074 1 T6 1 T8 1 T23 1
valid_sources[0x7f] 1030 1 T8 3 T20 1 T13 1
valid_sources[0x80] 904 1 T6 3 T8 2 T65 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 74584 1 T2 23 T3 6 T4 6
values[0x0] all_enables biggest_size 108065 1 T17 31637 T18 28241 T19 14648
values[0x1] all_enables biggest_size 107300 1 T17 31048 T18 28078 T19 14674


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 28746 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 240243 1 T2 44 T3 11 T4 14



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 71493 1 T1 1 T2 96 T3 27
values[0x0] 92169 1 T15 4 T27 2 T28 5
values[0x1] 105327 1 T15 2 T27 3 T28 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 15061 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 253928 1 T2 54 T3 13 T4 19



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1100 1 T10 1 T142 1 T41 1
valid_sources[0x01] 1090 1 T3 3 T27 1 T89 2
valid_sources[0x02] 1115 1 T24 1 T17 287 T148 1
valid_sources[0x03] 1039 1 T2 3 T3 2 T64 1
valid_sources[0x04] 981 1 T142 1 T139 2 T89 1
valid_sources[0x05] 1076 1 T64 1 T41 1 T67 1
valid_sources[0x06] 1073 1 T2 4 T12 1 T89 2
valid_sources[0x07] 1041 1 T2 1 T89 1 T149 1
valid_sources[0x08] 983 1 T3 2 T21 1 T91 1
valid_sources[0x09] 987 1 T2 1 T22 13 T91 1
valid_sources[0x0a] 1001 1 T6 1 T89 3 T24 2
valid_sources[0x0b] 1076 1 T21 1 T13 3 T67 1
valid_sources[0x0c] 1036 1 T22 11 T146 2 T139 1
valid_sources[0x0d] 1024 1 T6 1 T21 2 T74 1
valid_sources[0x0e] 1158 1 T66 1 T89 1 T17 267
valid_sources[0x0f] 999 1 T139 1 T17 287 T18 232
valid_sources[0x10] 985 1 T139 2 T150 1 T17 287
valid_sources[0x11] 1015 1 T2 1 T74 1 T139 2
valid_sources[0x12] 1156 1 T2 2 T7 1 T142 1
valid_sources[0x13] 1199 1 T89 1 T38 1 T149 2
valid_sources[0x14] 1092 1 T136 1 T89 2 T17 289
valid_sources[0x15] 1010 1 T2 5 T74 1 T89 1
valid_sources[0x16] 1010 1 T142 1 T139 1 T151 4
valid_sources[0x17] 987 1 T27 1 T146 2 T139 1
valid_sources[0x18] 1123 1 T139 2 T24 3 T17 271
valid_sources[0x19] 968 1 T21 1 T138 2 T139 2
valid_sources[0x1a] 996 1 T2 3 T6 1 T10 1
valid_sources[0x1b] 1077 1 T3 1 T66 1 T72 1
valid_sources[0x1c] 1047 1 T3 1 T6 1 T17 281
valid_sources[0x1d] 1078 1 T21 1 T139 1 T89 2
valid_sources[0x1e] 1027 1 T21 1 T139 1 T152 10
valid_sources[0x1f] 1120 1 T74 2 T65 128 T153 1
valid_sources[0x20] 1063 1 T2 2 T41 1 T139 1
valid_sources[0x21] 999 1 T154 1 T155 1 T156 5
valid_sources[0x22] 1070 1 T6 1 T66 1 T91 1
valid_sources[0x23] 1128 1 T3 2 T6 1 T13 3
valid_sources[0x24] 1077 1 T66 1 T139 2 T89 1
valid_sources[0x25] 982 1 T3 2 T66 1 T146 1
valid_sources[0x26] 976 1 T21 1 T64 1 T71 1
valid_sources[0x27] 982 1 T17 296 T18 231 T157 1
valid_sources[0x28] 1061 1 T6 1 T74 1 T142 2
valid_sources[0x29] 1013 1 T2 1 T21 1 T142 1
valid_sources[0x2a] 947 1 T3 1 T41 1 T146 1
valid_sources[0x2b] 1066 1 T146 1 T139 1 T89 1
valid_sources[0x2c] 1035 1 T74 1 T66 1 T13 3
valid_sources[0x2d] 1101 1 T138 2 T139 1 T149 1
valid_sources[0x2e] 1103 1 T155 1 T89 2 T158 3
valid_sources[0x2f] 1002 1 T6 4 T146 1 T154 1
valid_sources[0x30] 1088 1 T64 1 T139 2 T159 1
valid_sources[0x31] 1109 1 T142 1 T17 289 T160 1
valid_sources[0x32] 954 1 T91 2 T17 260 T148 1
valid_sources[0x33] 977 1 T142 1 T89 2 T158 7
valid_sources[0x34] 1080 1 T16 1 T161 1 T150 1
valid_sources[0x35] 1027 1 T3 1 T17 288 T57 2
valid_sources[0x36] 986 1 T154 1 T138 1 T139 1
valid_sources[0x37] 998 1 T2 1 T17 253 T61 1
valid_sources[0x38] 1058 1 T6 1 T139 1 T150 1
valid_sources[0x39] 1068 1 T6 1 T7 6 T21 1
valid_sources[0x3a] 1073 1 T10 1 T12 2 T41 2
valid_sources[0x3b] 983 1 T2 1 T17 280 T54 1
valid_sources[0x3c] 979 1 T139 1 T89 1 T17 263
valid_sources[0x3d] 1042 1 T146 1 T17 280 T61 2
valid_sources[0x3e] 1027 1 T154 1 T91 1 T17 287
valid_sources[0x3f] 1031 1 T142 1 T13 2 T41 1
valid_sources[0x40] 1081 1 T74 1 T154 1 T159 1
valid_sources[0x41] 1029 1 T162 1 T158 4 T159 2
valid_sources[0x42] 1030 1 T6 3 T142 1 T17 294
valid_sources[0x43] 1080 1 T23 1 T74 1 T27 1
valid_sources[0x44] 978 1 T6 1 T64 1 T146 1
valid_sources[0x45] 1053 1 T6 1 T71 2 T146 1
valid_sources[0x46] 1170 1 T146 2 T89 1 T147 1
valid_sources[0x47] 1081 1 T21 1 T22 3 T139 1
valid_sources[0x48] 1081 1 T163 1 T17 279 T18 258
valid_sources[0x49] 1041 1 T41 2 T155 1 T17 252
valid_sources[0x4a] 1040 1 T2 3 T153 1 T89 1
valid_sources[0x4b] 1100 1 T41 1 T89 1 T17 249
valid_sources[0x4c] 1087 1 T64 1 T12 2 T28 12
valid_sources[0x4d] 1066 1 T6 1 T21 1 T91 1
valid_sources[0x4e] 1013 1 T21 2 T92 1 T17 284
valid_sources[0x4f] 1046 1 T6 1 T142 1 T17 289
valid_sources[0x50] 1114 1 T6 2 T17 270 T59 1
valid_sources[0x51] 1108 1 T4 4 T153 1 T17 280
valid_sources[0x52] 1051 1 T72 1 T17 267 T18 250
valid_sources[0x53] 1092 1 T6 1 T23 1 T15 6
valid_sources[0x54] 1045 1 T2 1 T3 1 T6 1
valid_sources[0x55] 1098 1 T6 1 T13 1 T146 1
valid_sources[0x56] 1062 1 T64 1 T17 263 T148 1
valid_sources[0x57] 1030 1 T2 1 T164 1 T154 1
valid_sources[0x58] 1042 1 T13 1 T71 1 T146 1
valid_sources[0x59] 1035 1 T2 2 T17 271 T53 1
valid_sources[0x5a] 1077 1 T2 1 T89 1 T91 1
valid_sources[0x5b] 1031 1 T21 1 T67 1 T71 1
valid_sources[0x5c] 1064 1 T6 2 T12 2 T122 8
valid_sources[0x5d] 1049 1 T2 2 T23 2 T139 2
valid_sources[0x5e] 1014 1 T6 3 T122 1 T146 1
valid_sources[0x5f] 1077 1 T10 3 T64 1 T139 3
valid_sources[0x60] 904 1 T142 1 T154 1 T147 10
valid_sources[0x61] 1179 1 T74 1 T89 1 T150 1
valid_sources[0x62] 1003 1 T6 1 T122 3 T153 1
valid_sources[0x63] 1012 1 T2 1 T152 4 T91 1
valid_sources[0x64] 1065 1 T10 2 T17 289 T148 1
valid_sources[0x65] 1008 1 T3 1 T154 1 T89 1
valid_sources[0x66] 1042 1 T6 1 T22 2 T41 1
valid_sources[0x67] 1099 1 T13 3 T91 1 T17 249
valid_sources[0x68] 1010 1 T41 2 T67 1 T153 1
valid_sources[0x69] 1059 1 T155 1 T17 307 T18 245
valid_sources[0x6a] 1099 1 T139 1 T93 56 T17 266
valid_sources[0x6b] 1024 1 T41 1 T154 1 T138 1
valid_sources[0x6c] 1034 1 T21 1 T64 1 T154 1
valid_sources[0x6d] 1073 1 T122 4 T68 1 T155 1
valid_sources[0x6e] 1070 1 T2 4 T66 1 T165 1
valid_sources[0x6f] 1086 1 T4 1 T6 2 T153 1
valid_sources[0x70] 981 1 T71 2 T154 1 T17 261
valid_sources[0x71] 1041 1 T139 1 T162 2 T89 1
valid_sources[0x72] 1069 1 T7 2 T12 1 T142 1
valid_sources[0x73] 996 1 T17 301 T54 1 T18 284
valid_sources[0x74] 1037 1 T74 1 T149 1 T17 314
valid_sources[0x75] 1138 1 T41 1 T139 1 T162 3
valid_sources[0x76] 1026 1 T64 1 T12 2 T42 30
valid_sources[0x77] 1173 1 T139 1 T150 1 T17 253
valid_sources[0x78] 958 1 T2 1 T21 2 T161 2
valid_sources[0x79] 1084 1 T23 2 T91 1 T147 4
valid_sources[0x7a] 1082 1 T12 4 T41 1 T68 2
valid_sources[0x7b] 1031 1 T71 1 T138 1 T89 1
valid_sources[0x7c] 1021 1 T3 1 T4 1 T11 1
valid_sources[0x7d] 1081 1 T153 1 T89 3 T92 1
valid_sources[0x7e] 1143 1 T2 2 T153 1 T165 1
valid_sources[0x7f] 1058 1 T153 2 T166 1 T24 1
valid_sources[0x80] 1000 1 T167 2 T17 256 T18 233



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 61242 1 T2 44 T3 11 T4 14
values[0x0] all_enables biggest_size 89804 1 T15 2 T27 1 T28 3
values[0x1] all_enables biggest_size 89197 1 T28 1 T66 1 T67 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%