Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

564594

1

T2

210

T6

125

T8

302

full_word

339562

1

T2

23

T3

4

T4

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	903866	1			T2	233		T3	4		T4	4
auto[TlIntgErrCmd]	95	1			T50	4		T62	3		T63	2
auto[TlIntgErrData]	104	1			T50	3		T62	3		T63	4
auto[TlIntgErrBoth]	91	1			T50	3		T62	4		T63	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159356

1

T2

233

T3

4

T4

4

auto[1]

744800

1

T17

217461

T18

200799

T19

100590

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	77494	1			T2	210		T6	125		T8	302
auto[TlIntgErrNone]	partial	auto[1]	486840	1			T17	142309		T18	132946		T19	65614
auto[TlIntgErrNone]	full_word	auto[0]	81714	1			T2	23		T3	4		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	257818	1			T17	75152		T18	67853		T19	34976
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T50	1		T62	1		T63	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T50	3		T62	2		T63	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T133	1		T134	1		T135	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T135	1		T126	3		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T62	2		T125	2		T128	6
auto[TlIntgErrData]	partial	auto[1]	44	1			T50	1		T63	4		T125	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T62	1		T129	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T50	2		T129	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T50	2		T62	3		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T50	1		T63	3		T125	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T129	1		T135	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T62	1		T131	1		T133	1