Unified Coverage Report :: Module :: rom_ctrl_fsm

Module : rom_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.67	100.00	96.36		100.00	96.97	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm	93.67	100.00	96.36		100.00	96.97	75.00

---

Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.67	100.00	96.36		100.00	96.97	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.92	100.00	96.30	90.00	100.00	98.31	90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.06	100.00	98.28	97.33		100.00	69.70	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_compare	97.56	100.00	95.35	90.00	100.00	100.00	100.00
u_counter	100.00	100.00	100.00			100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		58	58	100.00
ALWAYS	138	3	3	100.00
ALWAYS	141	19	19	100.00
ALWAYS	209	3	3	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
ALWAYS	261	5	5	100.00
ALWAYS	270	3	3	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	312	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	3	3
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
			MISSING_ELSE
154	1	1
155	1	1
156	1	1
157	1	1
163	2	2
			MISSING_ELSE
167	2	2
			MISSING_ELSE
171	2	2
			MISSING_ELSE
194	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
			MISSING_ELSE
209	3	3
216	1	1
217	1	1
220	1	1
223	1	1
224	1	1
231	1	1
232	1	1
233	1	1
239	1	1
241	1	1
242	1	1
243	1	1
247	1	1
251	1	1
261	1	1
262	1	1
263	1	1
			MISSING_ELSE
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
277	1	1
278	1	1
279	1	1
288	1	1
289	1	1
291	1	1
304	1	1
307	1	1
309	1	1
310	1	1
312	1	1

---

Cond Coverage for Module : rom_ctrl_fsm

	Total	Covered	Percent
Conditions	55	53	96.36
Logical	55	53	96.36
Non-Logical	0	0
Event	0	0

 LINE       148
 EXPRESSION (counter_lnt && kmac_rom_rdy_i && kmac_rom_vld_o)
             -----1-----    -------2------    -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (kmac_err_i ? Invalid : KmacAhead)
             -----1----

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T43,T44

 LINE       157
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----

-1-	Status	Tests
0	Covered	T3,T14,T40
1	Not Covered

 LINE       163
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T11,T16,T45

 LINE       194
 EXPRESSION 
 Number  Term
      1  (checker_done && ((!(state_q inside {Checking, Done})))) || 
      2  (counter_done && (state_q == ReadingLow)) || 
      3  (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead})))))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T3,T4,T7
1	0	0	Covered	T3,T4,T7

 LINE       194
 SUB-EXPRESSION (checker_done && ((!(state_q inside {Checking, Done}))))
                 ------1-----    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       194
 SUB-EXPRESSION (counter_done && (state_q == ReadingLow))
                 ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       194
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 SUB-EXPRESSION (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead}))))
                 -----1-----    ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION (((state_q == ReadingHigh) || (state_q == KmacAhead)) & ((~counter_done)))
             --------------------------1-------------------------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION ((state_q == ReadingHigh) || (state_q == KmacAhead))
                 ------------1-----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (state_q == ReadingHigh)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (state_q == KmacAhead)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       265
 EXPRESSION (counter_read_req && (state_q == ReadingLow) && ((!counter_lnt)))
             --------1-------    -----------2-----------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       265
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (kmac_rom_rdy_i | (state_q inside {ReadingHigh, KmacAhead}))
             -------1------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       291
 EXPRESSION ((state_q != Checking) && (state_d == Checking))
             ----------1----------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (state_q != Checking)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       291
 SUB-EXPRESSION (state_d == Checking)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       312
 EXPRESSION (fsm_alert | checker_alert | unexpected_counter_change)
             ----1----   ------2------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T9,T10
0	1	0	Covered	T3,T4,T7
1	0	0	Covered	T1,T3,T4

---

FSM Coverage for Module : rom_ctrl_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Checking	157	Covered	T1,T2,T3
Done	171	Covered	T1,T2,T3
Invalid	156	Covered	T1,T3,T4
KmacAhead	156	Covered	T1,T3,T7
ReadingHigh	149	Covered	T1,T2,T3
ReadingLow	145	Covered	T1,T2,T3
RomAhead	155	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
Checking->Done	171	Covered	T1,T2,T3
Checking->Invalid	197	Covered	T3,T4,T7
Done->Invalid	197	Covered	T3,T4,T7
KmacAhead->Checking	167	Covered	T1,T3,T7
KmacAhead->Invalid	197	Covered	T10,T39,T41
ReadingHigh->Checking	157	Covered	T3,T14,T40
ReadingHigh->Invalid	156	Covered	T1,T3,T4
ReadingHigh->KmacAhead	156	Covered	T1,T3,T7
ReadingHigh->RomAhead	155	Covered	T2,T3,T4
ReadingLow->Invalid	197	Covered	T3,T4,T7
ReadingLow->ReadingHigh	149	Covered	T1,T2,T3
RomAhead->Checking	163	Covered	T2,T3,T4
RomAhead->Invalid	163	Covered	T3,T4,T7

---

Branch Coverage for Module : rom_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		33	32	96.97
IF	138	2	2	100.00
CASE	144	17	16	94.12
IF	194	2	2	100.00
IF	203	2	2	100.00
IF	209	2	2	100.00
IF	262	2	2	100.00
IF	265	2	2	100.00
IF	270	2	2	100.00
IF	288	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	148	if (((counter_lnt && kmac_rom_rdy_i) && kmac_rom_vld_o))
-3-:	154	case ({kmac_done_i, counter_done})
-4-:	156	(kmac_err_i) ? 
-5-:	157	(kmac_err_i) ? 
-6-:	163	if (kmac_done_i)
-7-:	163	(kmac_err_i) ? 
-8-:	167	if (counter_done)
-9-:	171	if (checker_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ReadingLow	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadingLow	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadingHigh	-	2'b01	-	-	-	-	-	-	Covered	T2,T3,T4
ReadingHigh	-	2'b10	1	-	-	-	-	-	Covered	T1,T43,T44
ReadingHigh	-	2'b10	0	-	-	-	-	-	Covered	T1,T3,T7
ReadingHigh	-	2'b11	-	1	-	-	-	-	Not Covered
ReadingHigh	-	2'b11	-	0	-	-	-	-	Covered	T3,T14,T40
ReadingHigh	-	default	-	-	-	-	-	-	Covered	T1,T2,T3
RomAhead	-	-	-	-	1	1	-	-	Covered	T11,T16,T45
RomAhead	-	-	-	-	1	0	-	-	Covered	T2,T3,T4
RomAhead	-	-	-	-	0	-	-	-	Covered	T2,T3,T4
KmacAhead	-	-	-	-	-	-	1	-	Covered	T1,T3,T7
KmacAhead	-	-	-	-	-	-	0	-	Covered	T1,T3,T7
Checking	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
Checking	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
Done	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	194	if ((((checker_done && (!(state_q inside {Checking, Done}))) || (counter_done && (state_q == ReadingLow))) || (kmac_done_i && (!(state_q inside {ReadingHigh, RomAhead})))))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if (alert_o)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if (kmac_rom_rdy_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	if (((counter_read_req && (state_q == ReadingLow)) && (!counter_lnt)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	270	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LastImpliesValid_A	270867919	16092	0	0
RelAddrWide_A	270867919	10251	0	0
SecCmCFILinear_A	270867919	0	0	1240
u_state_regs_A	270867919	270692293	0	0

LastImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	270867919	16092	0	0
T1	32980	2	0	0
T2	803323	58	0	0
T3	606782	330	0	0
T4	516026	269	0	0
T5	281432	8	0	0
T6	958931	56	0	0
T7	586682	32	0	0
T8	107664	5	0	0
T9	851249	620	0	0
T10	280954	15	0	0

RelAddrWide_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	270867919	10251	0	0
T1	32980	9	0	0
T2	803323	16	0	0
T3	606782	114	0	0
T4	516026	122	0	0
T5	281432	8	0	0
T6	958931	24	0	0
T7	586682	100	0	0
T8	107664	8	0	0
T9	851249	164	0	0
T10	280954	109	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	270867919	0	0	1240

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	270867919	270692293	0	0
T1	32980	32865	0	0
T2	803323	803185	0	0
T3	606782	606518	0	0
T4	516026	515727	0	0
T5	281432	281136	0	0
T6	958931	958643	0	0
T7	586682	584677	0	0
T8	107664	107571	0	0
T9	851249	850997	0	0
T10	280954	278742	0	0